Electronic Circuits Analysis and Design

Laboratory Manual

2 Acknowledgements

3 Table of Contents

Experiment 1: Frequency Response of Common-Emitter Amplifiers ...................................... 4 Experiment 2: Frequency Response of JFET Amplifiers........................................................... 9 Experiment 3: Multistage RC Coupled Amplifiers .................................................................. 14 Experiment 4: Class A Power Amplifier.................................................................................... 18 Experiment 5: Class B Push-Pull Amplifier .............................................................................. 23 Experiment 6: Differential Amplifier ......................................................................................... 31 Experiment 7: Operational Amplifiers ...................................................................................... 40 Experiment 8: Op-Amp Summing Amplifiers .......................................................................... 49 Experiment 9: Op-Amp Integrator and Differentiator ............................................................ 53 Experiment 10: Feedback Amplifier: Voltage-Series Feedback using Op-Amp.................... 60 Experiment 11: Oscillator Circuits ............................................................................................ 64 Experiment 12: Familiarization with Digital Circuits .............................................................. 72

7400 Series and 4000 Series ......................................................................................................... 79

Guidelines to Handling and Using CMOS Devices ................................................................... 80

References ..................................................................................................................................... 81

4 EXPERIMENT No. 1 FREQUENCY RESPONSE OF COMMON-EMITTER AMPLIFIERS

I.

OBJECTIVES To calculate and measure the frequency response of common-emitter amplifier circuits BASIC CONCEPT The analysis of the frequency response of an amplifier can be considered in three frequency regions: the low-, mid-, and high-frequency regions. In the low-frequency region the capacitors used for DC isolation (AC coupling) and bypass operation affect the lower cutoff (lower 3-dB) frequency. In the mid-frequency range only resistive elements affect the gain, the gain remaining constant. In the high-frequency region of operation, stray wiring capacitances and device inter-terminal capacitances will determine the circuits upper cutoff frequency. Lower Cutoff (lower 3-dB) Frequency: Each capacitor used will result in a cutoff frequency. The lower cutoff frequency at the network is then the largest of these lower cutoff frequencies. The cutoff frequency due to the input coupling capacitor is Hz with: Ri =R1||R2||re The cutoff frequency due to the output coupling capacitor is Hz The cutoff frequency due to the emitter bypass capacitor is Hz with Re = RE || re Upper Cutoff (upper 3-dB) Frequency: In the high-frequency range the amplifier gain is affected by the transistors parasitic capacitances as follows: At input connection of circuit: Hz where || and Ci is | || |

II.

= input wiring capacitance = voltage gain of amplifier at mid-band frequency = capacitance between transistor base-emitter terminals = capacitance between transistor base-collector terminals

At output connection of circuit: Hz where || and

= output wiring capacitance = capacitance between transistor collector-emitter terminals

III.

MATERIALS AND EQUIPMENT 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2N3904 transistor or equivalent 2.2 k at 0.5 V (RE and RL) 3.9 k at 0.5 V (RC) 100 at 0.5 V (RS) 10 k at 0.5 V (R2) 39 k at 0.5 V (R1) 1 F capacitor (CC) at 25 V 10 F capacitor (CS) at 25 V 20 F capacitor (CE) at 25 V DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires MultiSim (LabVIEW)

IV.

CIRCUIT DIAGRAM
VCC 15V Rc 3.9k R2 10k Rs 100 V1 Cs 10F Q1 Cc 1F RL 2.2k R1 39k 2N3904 RE 2.2k CE 20F Vout

20mVpk 5 jHz 5kHz 0 0 degress

60 mVpk

Figure 1.1

V.

PROCEDURE a. Low-Frequency Response Calculations 1. Using the specification data for the transistor, record values: Cbe (specified) = ___________ Cbc (specified) = ___________ Cce (specified) = ___________ Enter values of typical wiring capacitance: Cwi (approximated) = ___________ Cwo (approximated) = ___________ 2. Calculate the values of DC bias voltage and current for the circuit of Fig. 1.1. VB (calculated) = ____________ VE (calculated) = ____________ VC (calculated) = ____________ IE (calculated) = ____________ Using the value of IE, calculate the transistor dynamic resistance. re (calculated) = ____________ 3. Calculate the magnitude of amplifier midband gain (under load) using: ||

4.

Calculate lower cutoff frequencies due to coupling capacitors and due to bypass capacity.

b. Low-Frequency Response Measurements 1. Construct the network of Figure 1.1. Record the actual resistor values in the space provided in Figure 1.1, if desired. Adjust VCC = 15 V. Apply input AC signal, Vsig = 60 mV, at a peak frequency of f = 5 kHz. Observe the output voltage using a scope. If VO shows any distortion, reduce Vsig until the output is undistorted. 2. Measure and record signals for undistorted operation. Vsig (measured) = ___________ VO (measured) = ___________ Calculate the circuits mid-frequency voltage gain. AVmid = __________

7 3. Maintaining the input voltage at the level set above, vary the frequency and measure and record VO to complete Table 1.1. Calculate the amplifier voltage gain for each frequency and complete Table 1.2.

4.

c. High-Frequency Response Calculations 1. Calculate the upper cutoff frequencies and record below. fHi (calculated) = ____________ fHo (calculated) = ____________ 2. Applying an input voltage which provides non-distorted output voltage, complete Table 1.3 measuring the resulting output voltage over a range of high frequency values. Vi (measured) = ____________ Calculate the amplifier voltage gain (in dB units) and complete Table 1.4.

3.

VI. f VO f AV f VO

DATA AND RESULTS Table 1.1 50 100 Hz Hz 200 Hz 400 Hz 600 Hz 1 kHz 2 kHz 3 kHz 5 kHz 10 kHz

Table1.2 50 100 Hz Hz

200 Hz

400 Hz

600 Hz

1 kHz

2 kHz

3 kHz

5 kHz

10 kHz

Table1.3 10 50 kHz kHz

300 kHz

500 kHz

600 kHz

1 kHz

700 kHz

900 kHz

1 MHz

2 MHz

f AV

Table1.4 10 50 kHz kHz

300 kHz

500 kHz

600 kHz

1 kHz

700 kHz

900 kHz

1 MHz

2 MHz

8 VII. SAMPLE COMPUTATIONS

VIII.

GRAPH

IX.

QUESTIONS AND PROBLEMS 1. Perform the same experiment using NI Elvis II. Verify the laboratory data obtained. 2. Using Multisim, determine the frequency response of Vo/Vs for the BJT amplifier of Figure 1.1. ANALYSIS AND INTERPRETATION OF RESULTS

X.

XI.

CONCLUSION

10 EXPERIMENT No. 2 FREQUENCY RESPONSE OF JFET AMPLIFIER

I.

OBJECTIVES To calculate and measure the frequency response of JFET amplifier circuits BASIC CONCEPT The analysis of the FET amplifier in the low-frequency region will be quite similar to that of the BJT amplifier. There are again three capacitors of primary concern: CG, CC, and CS. The analysis of the frequency response of an amplifier can be considered in three frequency regions: the low-, mid-, and high-frequency regions. In the low-frequency region the capacitors used for DC isolation (AC coupling) and bypass operation affect the lower cutoff (lower 3-dB) frequency. In the midfrequency range only resistive elements affect the gain, the gain remaining constant. In the high-frequency region of operation, stray wiring capacitances and device interterminal capacitances will determine the circuits upper cutoff frequency. Lower Cutoff (lower 3-dB) Frequency: Each capacitor used will result in a cutoff frequency. The lower cutoff frequency at the network is then the largest of these lower cutoff frequencies. The cutoff frequency due to the input coupling capacitor is

II.

The cutoff frequency due to the output coupling capacitor is with Ro = RD || rd. The cutoff frequency due to the source bypass capacitor is with
( )

||

Upper Cutoff (upper 3-dB) Frequency: In the high-frequency range the amplifier gain is affected by the transistors parasitic capacitances as follows: At input connection of circuit:

where

||

with

and

At the output connection of circuit:

11

where

||

||

with

and

III.

MATERIALS AND EQUIPMENT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2N3819 or equivalent 1 M (RG) 4.7 k (RD) 1 k (RS) 2.2 k (RL) 10 k (Rsig) 0.01 F (CG) 0.5 F (CC) 2 F (CS) DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires MultiSim (LabVIEW)

IV.

CIRCUIT DIAGRAM
RD VDD CC

Rsig

CG

Q1 RG RL RS CS

Vs

Figure 2.1 JFET Amplifier

12 V. PROCEDURE a. Low-Frequency Response Calculations 1. Using the specification data for the transistor, record values: Cgd (specified) = ___________ Cgs (specified) = ___________ Cds (specified) = ___________ Enter values of typical wiring capacitance: Cwi (approximated) = ___________ Cwo (approximated) = ___________ 2. Calculate the values of DC bias voltage and current for the circuit of Fig. 2.1. VGS (calculated) = ____________ VDS (calculated) = ____________ VG (calculated) = ____________ ID (calculated) = ____________ Using the value of ID, calculate the transistor transconductance. gm (calculated) = ____________ Calculate the magnitude of amplifier midband gain (under load) using: ||

3.

4.

Calculate lower cutoff frequencies due to coupling capacitors and due to bypass capacitor.

b. Low-Frequency Response Measurements 1. Construct the network of Figure 2.1. Record the actual resistor values in the space provided in Figure 2.1, if desired. Adjust VDD = 20 V. Apply input AC signal, Vsig = 60 mV, at a peak frequency of f = 5 kHz. Observe the output voltage using a scope. If VO shows any distortion, reduce Vsig until the output is undistorted. 2. Measure and record signals for undistorted operation. Vsig (measured) = ___________ VO (measured) = ___________ Calculate the circuits mid-frequency voltage gain. AVmid = __________ 3. Maintaining the input voltage at the level set above, vary the frequency and measure and record VO to complete Table 2.1.

13

4.

Calculate the amplifier voltage gain for each frequency and complete Table 2.2.

c. High-Frequency Response Calculations 1. Calculate the upper cutoff frequencies and record below. fHi (calculated) = ____________ fHo (calculated) = ____________ 2. Applying an input voltage which provides non-distorted output voltage, complete Table 2.3 measuring the resulting output voltage over a range of high frequency values. Vi (measured) = ____________ Calculate the amplifier voltage gain (in dB units) and complete Table 2.4.

3.

VI. f VO f AV f VO

DATA AND RESULTS Table 2.1 50 100 Hz Hz 200 Hz 400 Hz 600 Hz 1 kHz 2 kHz 3 kHz 5 kHz 10 kHz

Table 2.2 50 100 Hz Hz

200 Hz

400 Hz

600 Hz

1 kHz

2 kHz

3 kHz

5 kHz

10 kHz

Table 2.3 10 50 kHz kHz

300 kHz

500 kHz

600 kHz

1 kHz

700 kHz

900 kHz

1 MHz

2 MHz

f AV VII.

Table 2.4 10 50 kHz kHz

300 kHz

500 kHz

600 kHz

1 kHz

700 kHz

900 kHz

1 MHz

2 MHz

SAMPLE COMPUTATIONS

14 VIII. GRAPH

IX.

QUESTIONS AND PROBLEMS 1. Perform the same experiment using NI Elvis II. Verify the laboratory data obtained. 2. Using Multisim, determine the frequency response of Vo/Vs for the BJT amplifier of Figure 2.1. ANALYSIS AND INTERPRETATION OF RESULTS

X.

XI.

CONCLUSION

15 EXPERIMENT No. 3 MULTISTAGE RC COUPLED AMPLIFIER

I.

OBJECTIVES Perform DC and AC signal analysis in a multistage amplifier then obtain the gain of the system.

II.

BASIC CONCEPT An amplifier system can be composed of multi-stage connections in order to achieve higher gains. This is so because a single amplifiers output is not enough to provide the required power. Instead, several amplifiers are in cascade or cascode with each other, such that the output of one stage is the input of the next, and so on. This kind of interconnectioin would provide a much higher gain for the entire circuit or system. The overall gain of the system could be calculated as

III.

MATERIALS AND EQUIPMENT 3 4 3 3 4 3 3 50 k, W (R1) 10 k, W (R2, RL) 5 k, W (RC) 1 k, W (RF) 10 F, 25 V (C) 0.01 F, 25 V (CE) 2N222 or equivalent

1 1 1 1 1

DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires Multisim (LabVIEW)

16 IV. CIRCUIT DIAGRAM

Rc 5k VCC 15V Rc1 5k Rc2 5k Cc3 Vout C Vin 10F R2 10k 2N2222A RE 1k 10F R4 10k CE1 0.01F 2N2222A RE1 1k 10F R6 10k CE2 0.01F 2N2222A RE2 1k CE3 0.01F Q1 Cc1 Q2 Cc2 Q3 10F

R1 50k

R3 50k

R5 50k

GND

Figure 3.1 Multistage RC Coupled Amplifier

V.

PROCEDURE 1. Using a breadboard, connect the circuit as shown in Figure 3.1. Make sure all wires are in place. 2. Using the VOM or multi-tester, set the DC power supply to 15 V. 3. Using the VOM, measure the DC voltages on the base, emitter, and collector of each transistor. Compute the expected voltage across each transistor terminal. Record the results in Table 3.1. Compute the AC emitter resistance and voltage gain of each transistor.

Using the oscilloscope, measure the input and output voltage amplitude of each stage. 4. Disconnect the 10-k load resistance. Measure the voltage gain of stage 3 using the oscilloscope. Av3 = _________ Then, compute for the total voltage gain (loaded and unloaded). Record the results in Table 3.3.

17 VI. DATA AND RESULTS

Table 3.1 DC Bias Voltages across Transistor Terminals Parameter Expected Value Measured Value VB1 VC1 VE1 VB2 VC2 VE2 VB3 VC3 VE3 Table 3.2 Output Voltage and Gains Parameter Expected Value Vin Vout1 Vout2 Vout3 A1 A2 A3

% Difference

Measured Value

% Difference

Table 3.3 Overall Voltage Gain Parameter Expected Value AVt (unloaded) AVt (loaded) VII. SAMPLE COMPUTATIONS

Measured Value

% Difference

18 VIII. GRAPH

IX.

QUESTIONS AND PROBLEMS A microphone puts out a peak voltage of 1 mV and has an output resistance of 10 k. Design an amplifier system to drive an 8- speaker, producing a 2-W signal power. Use a 24-V power supply to bias the circuit. Assume a current gain of = 50 for the available transistors. Specify the current and power ratings of the transistors. 2. Perform the same experiment using NI Elvis II. Verify the laboratory data obtained. 3. Compare the results obtained in problem 2 using multisim. 1.

X.

ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

19 EXPERIMENT No. 4 CLASS A POWER AMPLIFIER

I.

OBJECTIVES To calculate and measure DC and AC voltages, and power input and outpuf for class A power amplifier BASIC CONCEPT A class A amplifier draws the same power from a voltage supply regardless of the signal applied. The input power is calculated from

II.

The signal power provided by the amplifier can be calculated using

with the amplifiers efficiency being

III.

MATERIALS AND EQUIPMENT 1 1 1 1 2 1 1 1 1 1 1 1 20 (RE) 120 , 0.5 W (R3) 180 (R2) 1 k, 0.5 W (R1) 10 F (C1, C2) 100 F (C3) npn medium power, 15-W (2N3904 or equivalent) DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires Multisim (LabVIEW)

20

IV.

CIRCUIT DIAGRAM
VCC

R3 R1 C1 Vi R2 RE C3 Q2 C2 Vo

Figure 4.1 Class A Amplifier V. PROCEDURE 1. Construct the circuit shown in Figure 4.1. Set the supply voltage to V CC = 10 V and measure and record the DC bias voltages in Table 4.1 2. Based on the voltages recorded in Step 1, calculate the value of the DC bias currents, IE and IC. Also, calculate VCE. Use Table 4.1 3. Draw the DC load line in the space provided on the data sheet. Based on the data in Step 2, locate the operating point (Q-point) on the dc load line. 4. Calculate the DC bias values for the circuit of Figure 4.1. Compare the results obtained in Steps 1 and 2. 5. Using the DC bias values calculated in Step 4, calculate the output voltage, power and efficiency values for the largest signal swing in the Class A amplifier of Figure 4.1. Use Table 4.2. 6. Using the oscilloscope, adjust the input signal (f = 10 kHz) to obtain the largest undistorted output signal. Measure and record these input and output voltages. Use Table 4.2. 7. Based on the measured values obtained in Step 6, calculate the power and efficiency for the Class A amplifier of Figure 4.1. Compare the measured and calculated values of power and efficiency obtained in Table 4.2. 8. Reduce the input signal to one-half the level of Step 6. Measure and record the input and output voltages in Table 4.3. 9. Calculate the input power, output power, and efficiency using half the input voltage used in Step 5. Use Table 4.3. 10. Using the measured values, calculate the power and efficiency for the Class A amplifier of Figure 4.1. 11. Compare the measured and calculated values of power and efficiency obtained in Steps 9 and 10.

21

VI.

DATA AND RESULTS

Table 4.1 DC Bias Voltages and Currents Parameter Expected Value Measured Value VB VC VE VCE IC IE Table 4.2 AC Operation: Largest Signal Swing Parameter Vi Vo Pi Po % Table 4.3 Parameter Vi Vo Pi Po % Expected Value Measured Value

% Difference

% Difference

Expected Value

Measured Value

% Difference

VII.

SAMPLE COMPUTATIONS

22 VIII. GRAPH

IX.

QUESTIONS AND PROBLEMS 1. From the obtained data, is the Q-point approximately in the center of the load line? Explain.

2.

Is the voltage VCE about one-half the voltage VCC? Explain.

23 3. What is the DC power delivered by VCC to the circuit of Figure 4.1? Explain.

4.

What is the phase relationship between Vi and Vo? Explain.

X.

ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

24 EXPERIMENT No. 5 CLASS B PUSH-PULL AMPLIFIER

I.

OBJECTIVES 1. 2. 3. 4. 5. 6. 7. 8. Determine the dc load line and locate the operating (Q-point) on the dc load line for a class B push-pull amplifier. Determine the ac load line for a class B push-pull amplifier Observe crossover distortion of the output wave shape and learn how to estimate it Determine the maximum ac peak-to-peak output voltage swing before peak clipping occurs and compare the measured value with the expected value Compare the maximum undistorted ac peak-to-peak output voltage swing for a class B amplifier with the maximum for a class A amplifier Measure the large-signal voltage gain of class B push-pull amplifier Measure the maximum undistorted output power for a class B push-pull amplifier Determine the amplifier efficiency

II.

BASIC CONCEPT The circuit in Figure 5.1 is a class B push-pull amplifier with the transistors biased at cutoff. The dc biasing network in Figure 5.2 will eliminate crossover distortion by biasing the transistors slightly above cutoff. The dc collector-emitter voltages for the two transistors in Figure 5.2 can be calculated from and The complete class B push-pull amplifier is shown in Figure 5.3. The dc load line . The for each transistor is a vertical line crossing the horizontal axis at Q-point should be very close to cutoff for each transistor. The ac load line for each transistor should pass through the Q-point and cross the vertical axis at .

Where

Amplifier voltage gain is measured by dividing the ac peak-to-peak output voltage by the ac peak-to-peak input voltage. Therefore,

The amplifier output power (Po) can be calculated as follows:

25 Where is the peak-to-peak voltage and .

The efficiency of a class B amplifier is equal to the maximum output power (Po) divided by the power supplied by the source (Ps) times 100%. Mathematically,

Where

= (VCC)(ICC). The supply current (ICC) is determined from

Where III. MATERIALS AND EQUIPMENT 1 1 2 2 1 1 2 1 1 1 1 1 1 1 2N3904 npn bipolar transistor (Q1) 2N3906 pnp bipolar transistor (Q2) 1N4001 diodes (D1, D2) 10 F capacitors (C1, C2) 100 F capacitor (C3) 100 (RL) 5 k (R1, R2) DC power supply DMM Oscilloscope Function Generator 0-1 mA milliammeter 0-50 mA milliammeter Breadboard for constructing circuit Connecting Wires

IV.

CIRCUIT DIAGRAM

VCC 20V R1 5k

C1 10F Vin C2 10F

Q1

2N3904

C3 Vout 100F R3 100

Q2

R2 5k

2N3906

GND

Figure 5.1 Class B Push-Pull Amplifier With Crossover Distortion

26

VCC 20V R1 5k

Q3

D1 1N4001GP

2N3904

D2 1N4001GP

Q4

R2 5k

2N3906

Figure 5.2 Class B Push-Pull Amplifier, DC Analysis

VCC 20V R1 5k C1 10F Vin C2 10F Q2 Q1

2N3904

C3 Vout 100F R3 100

R2 5k

2N3906

GND

Figure 5.3 Class B Push-Pull Amplifier, AC Analysis

27

V.

PROCEDURE 1. 2. Set up the circuit shown in Figure 5.1. Use a 20-V DC supply. Notice the crossover distortion of the output wave shape (blue curve). Draw this wave shape in the space provided on the data sheet and note the crossover distortion. 3. Set up the network shown in Figure 5.2. Maintain the 20 V supply. 4. Record the dc base voltage of the two transistors. Also measure the emitter voltage. Record data in Table 5.1. 5. Based on the voltages recorded in Step 4, calculate the dc collector-emitter voltage (VCE) for both transistors on the data sheet. Use Table 5.1. 6. Draw the dc load line in the space provided on the data sheet. Based on the data in Step 5, locate the operating point (Q-point) on the dc load line. 7. Set up the circuit shown in Figure 5.3. Based on the values of VCC and RL, draw the ac load line on the graph in Step 6. 8. Notice that there is no longer any crossover distortion of the output wave shape. Keep increasing the input signal voltage until output peak clipping occurs. Then reduce the input signal level slightly until there is no longer any clipping. Record the maximum undistorted ac peak-to-peak output voltage, the ac peakto-peak input voltage, and the dc collector current (IC) on the data sheet. Adjust the oscilloscope settings as needed. Used Table 5.2. 9. Based on the ac load line and Q-point located on the graph in Step 6, estimate what is the maximum ac peak-to-peak output voltage should be before output clipping occurs. 10. Based on the maximum undistorted ac peak-to-peak output voltage measured in Step 8, calculate the maximum undistorted output power (Po) on the load (RL). Use Table 5.3. 11. Based on the supply voltage (VCC), the dc collector current (IC) measured in Step 8, and the bias resistor current (IRb1), calculate the power supplied by the dc voltage source. Use Table 5.3. 12. Based on the power supplied by the dc voltage source (PS) calculated in Step 11 and the output power (Po) calculated in Step 10, calculate the efficiency ( ) of the amplifier. Use Table 5.3.

VI.

DATA AND RESULTS

Table 5.1 Parameter VB(Q1) VB(Q2) VE VCE(Q1) VCE(Q2)

Expected Value

Measured Value

% Difference

28

Table 5.2 Parameter VIN(p-p) Vout(p-p) (undistorted) IC

Expected Value

Measured Value

% Difference

Table 5.3 Parameter Vp-p before clipping Po PIN(dc) Efficiency ( )

Expected Value

Measured Value

% Difference

VII.

SAMPLE COMPUTATIONS

VIII.

GRAPH Draw the output waveform below. (From Step 2) Highlight the crossover distortion.

29 Draw the DC load line below.

IX.

QUESTIONS AND PROBLEMS 1. What caused the crossover distortion in Figure 5.1? What does the addition of diodes D1 and D2 accomplish?

2.

Where is the location of the operating point (Q-point) on the dc load line? On the ac load line? Explain.

3.

What is the relationship between the dc load line and the ac load line? Explain.

30 4. Compare the measured amplifier voltage and the expected voltage? Explain.

5.

Compare the efficiency of a push-pull amplifier with that of the class A amplifier. Explain.

X.

ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

31 EXPERIMENT No. 6 DIFFERENTIAL AMPLIFIERS

I.

OBJECTIVES 1. Calculate the dc tail current (It) for a differential amplifier and compare the calculated value with the measured value 2. Calculate the dc collector currents in the balanced transistors for a differential amplifier and compare the calculated voltages and compare the calculated and measured values 3. Calculate the balance transistor dc collector voltages and compare the calculated and measured values 4. Calculate the differential voltage gain of a differential amplifier and compare the calculated value with the measured value 5. Determine the phase relationship between the output sine wave and the input on each base of a differential amplifier 6. Determine the peak-to-peak sine wave output voltage between the transistor collectors of a differential amplifier and compare it to the peak-to-peak sine wave output voltage between one collector and ground 7. Calculate the differential amplifier common-mode voltage gain and compare the calculated value with the measured value 8. Determine the common-mode rejection ratio (CMRR) for a differential amplifier and explain what it means regarding noise rejection BASIC CONCEPT The differential amplifier dc tail current (It) in Figure 6.1 is calculated by first determining the voltage across the emitter resistor (RE) and then dividing by the value of RE. Assuming that the dc base current in each transistor is negligible, the dc voltage on each base (VB) is approximately zero. Therefore, VE = VB VBE = 0

II.

The differential amplifier dc collector currents (IC1 and IC2) are approximately equal to the dc emitter currents (IE1 and IE2). The dc emitter currents (IE1 and IE2) will be equal to each other if the two transistors are in perfect balance. The tail current is equal to the sum of the emitter currents; and assuming perfect balance, and

The differential amplifier dc collector voltages (VC1 and Vc2) will be equal if the two transistors are in perfect balance because the two collector currents will be equal and the two collector resistors (RC1 and RC2) are equal. Each dc collector voltage can be

32 found by calculating the voltage across each collector resistor and subtracting this value from the dc supply voltage (VCC). Therefore,

The differential voltage gain (Ad) of the differential amplifier shown in Figure 6.2 is found by measuring the ac peak-to-peak voltage on one collector (Vc2) and the ac peak-to-peak voltage between the transistor bases (Vb1 Vb2). The differential voltage gain is

Because base2 is grounded through the 100 resistor

The expected differential voltage gain (Ad) of the differential amplifier can be calculated based on the value of the collector resistors (RC) and the transistor ac emitter resistance (re). The differential voltage gain is

where Ad is the voltage gain between collector c2 and base b1. The differential amplifier common-mode voltage gain (Acm) is the voltage gain between one collector and the bases connected together with a signal voltage applied to the bases. The common-mode voltage gain is found by dividing the ac peak-topeak voltage of the collectors (Vc2) by the ac peak-to-peak voltage on the bases (Vb1 Vb2). Therefore,

The expected common-mode voltage gain can be calculated from

Wheare RC is the collector resistor value and RE is the emitter resistor value. The common-mode rejection ratio (CMRR) is the ratio of the differential voltage gain (Ad) divided by the common-mode voltage gain (Acm). It is a measure of how well the amplifier rejects noise entering at the transistor bases. Therefore,

33 The common-mode rejection ratio in dB is

III.

MATERIALS AND EQUIPMENT 2 2 2 2 3 2 2 1 1 1 2N3904 bipolar npn transistors 100 resistors (RB1 and RB2 in Figure 6.1) 2 k resistors (RC1 and RC2) 1 k resistors (RB1 and RB2in Figure 6.2) 0.10 mA milliammeters DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires

IV.

CIRCUIT DIAGRAM
Rc1 2k Vcc1 15 V Rc2 2k

Q1

Q2

2N3904 RB1 100

2N3904 RB2 100 RE1 2k VEE1 15 V

100 Vrms 1 Hz 0

Figure 6.1

34

Rc1 2k Vout2 Vcc 15 V Q1 Vout1

Rc2 2k

Q2

100 Vrms 1 Hz 0 RB1 100

2N3904

2N3904 RB2 100 RE 2k VEE 15 V

Figure 6.2

V.

PROCEDURE 1. Set up the circuit shown in Figure 6.1. With a VOM set both power supplies to 15 V. When steady state is reached, record the dc tail current (It), the dc collector currents (IC1 and IC2), and the dc collector voltages (VC1 and VC2) in Table 6.1. 2. Calculate the expected dc tail current (It) from the circuit component values. 3. Calculate the expected dc collector currents (IE1 and IE2) for balanced transistors. 4. Set up the circuit shown in Figure 6.2. Record the ac peak-to-peak output voltage on collector 2 (Vc2) and the ac peak-to-peak input voltage as base 1 (Vb1) in Table 6.2. 5. Based on the readings in Step 4, calculate the differential voltage gain (Ad) of the amplifier. 6. Based on the value of the circuit components and the value of the transistor ac emitter resistance, calculate the expected differential voltage gain (Ad) between base 1 (b1) and collector 2 (c2). 7. Record the phase difference between the input sine wave (Vb1) and the output sine wave (Vc2) in Table 6.3. Move the function generator output and the oscilloscope red lead to base 2 (b2). Record the phase difference between the input sine wave (Vb2) and the output sine wave (Vc2). 8. Move the oscilloscope ground lead to collector 1 (c1). Change the oscilloscope Channel B input 1 V/div, and change the Channel A input from AC to 0. Record the ac peak-to-peak output voltage between collectors. 9. Move the oscilloscope ground lead back to a ground terminal and connect both bases (b1 and b2) together. Change the oscilloscope Channel A input back to AC and the Channel B input to 2 mV/div. Record the ac peak-to-peak output voltage (Vc2) and input voltage (Vb2) on the data sheet. 10. Based on the voltages measured in Step 10, calculate the common-mode gain (Acm). 11. Based on the circuit components, calculate the expected common-gain (Acm).

35 12. Based on the differential voltage gain (Ad) measured in Steps 5 and 6 and the common-mode gain (Acm) measured in Steps 10 and 11, calculate the commonmode rejection ratio (CMRR). Express your answer in decibels (dB). VI. DATA AND RESULTS Table 6.1 Parameter IT IC1 I2 VC1 VC2 Expected Value Measured Value % Difference

Table 6.2 Parameter Vc2 ac (p-p) Vb1 ac (p-p) Diff. Voltage gain, Ad

Expected Value

Measured Value

% Difference

Table 6.3 Parameter Phase difference Vb1 and Vc2 Common-Mode Gain (Acm) Common-Mode Rejection Ratio (CMRR) in dB VII. Expected Value Measured Value % Difference

SAMPLE COMPUTATIONS

36 VIII. GRAPH

IX.

QUESTIONS AND PROBLEMS 1. How did your calculated value for the dc tail current (It) compare with the measured value?

2.

What is the relationship between the dc tail current and the dc collector currents in the balanced transistors? Explain.

3.

Are the dc collector currents equal? What does this tell you about the balance between the two transistors?

37

4.

Are the dc collector voltages equal? What does this tell you about the balance between the two collector resistors?

5.

How did your calculated values for the dc collector currents and dc collector voltages compare the measured values?

6.

How did the calculated values for the differential voltage gain (Ad) compare with the measured value? Explain any difference.

7.

Based on the data collected in Step 8, which base is the inverting input and which base is the noninverting input for the differential amplifier circuit in Figure 6.2?

38

8.

How did the ac peak-to-peak output voltage between collectors, in Step 9, compare with the ac peak-to-peak output voltage between one collector and ground, in Step 5? Explain.

9.

How did the calculated value for the common-mode gain (Acm) compare with the measured value?

10.

How did the common-mode gain compare with the differential voltage gain? What implication does this have regarding differential amplifier noise rejection?

11.

What is the meaning of common-mode rejection ratio (CMRR) for a differential amplifier? What is the advantage of a high CMRR?

39

X.

ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

40 EXPERIMENT No. 7 OPERATIONAL AMPLIFIERS

A. NONINVERTING VOLTAGE AMPLIFIER I. OBJECTIVES 1. Calculate the expected voltage gain of an op-amp noninverting voltage amplifier and compare the calculated value with the measured value 2. Determine the phase difference between the output and input sine waves for a noninverting voltage amplifier 3. Calculate the expected dc output offset voltage based on the op-amp input offset voltage and compare the calculated output offset with the measured output offset 4. Determine the significance of the dc output for different levels of signal inputs BASIC CONCEPT Based on the ac peak-to-peak output and input voltages, the voltage gain (Av) of an amplifier is calculated by dividing the ac peak-to-peak output voltage (Vout) by the ac peak-to-peak input voltage (Vin). Therefore,

II.

The expected voltage gain of the noninverting op-amp voltage amplifier shown in Figure 7.1 is the inverse of the amplifier feedback ratio (). Therefore,

The amplifier output offset voltage (VOoff) is equal to the op-amp input offset voltage (VOs) multiplied by the amplifier voltage gain (Av). Therefore,

+ Vcc 2 7 6 3 4 - Vcc

Schematic Diagram of an OP-AMP where +Vcc = 15 V - Vcc = 15V

41 III. MATERIALS AND EQUIPMENT 1 1 1 2 1 1 1 1 1 LM741 op-amp 1 k (R2) 10 k 100 k (RL and R1) DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires Multisim (LabVIEW)

IV.

CIRCUIT DIAGRAM
+ Vcc Vin 3 7 6 2 4 - Vcc Vout

RF 100k

R1

RL 100k

R1 1k GND

R2

Figure 7.1 V. PROCEDURE 1. Set up the circuit shown in Figure 7.1. With a VOM, set the DC supplies to 15 V then connect to the circuit. Record the ac peak-to-peak input voltage (Vin) also the ac peak-to-peak output voltage (Vout) on the data sheet. Also record the dc output offset voltage (VOoff) and the phase difference between the input and output sine waves. Based on the measured data in Step 1, calculate the voltage gain (Av) of the amplifier. Based on the circuit component values, calculate the expected voltage gain (Av). Change the value of R1 from 100 k to 10 k. Change the function generator amplitude to 100 mV, oscilloscope Channel A input to 100 mV/div, and oscilloscope Channel B input to 500 mV/div. Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout), and the dc output offset voltage (VOoff) on the data sheet.

2. 3. 4.

42 5. 6. 7. Based on the measured data in Step 4, calculate the new voltage gain (Av) of the amplifier. Based on the circuit component values, calculate the expected voltage gain (Av). Based on the input offset voltage (VOS) for the op-amp, calculate the dc output offset voltage (VOoff) expected for this amplifier gain.

VI.

DATA AND RESULTS Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout), the dc output offset voltage (VOoff), and the phase diference between the input and output sine waves. Vin = ___________ VOoff = __________ Vout = __________ Phase Diff. = ____

Based on the measured data in Step 1, calculate the voltage gain (Av) of the amplifier. (R1 = 100 k) (measured)

Based on the circuit component values, calculate the expected voltage gain (Av) (R1 = 100 k).

Based on the input offset voltage (VOs) for the op-amp, calculate the dc output offset voltage (VOoff) expected for this amplifier gain.

Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout), and the dc output offset voltage (VOoff). Vin = _________ Vout = _________ VOoff = __________

Based on the measured data in Step 5, calculate the new voltage gain (Av) of the amplifier. (R1 = 10 k) (measured)

43 Based on the circuit component values, calculate the expected voltage gain (Av). R1 = 10 k (calculated)

Based on the input offset voltage (VOs) for the op-amp, calculate the dc output offset voltage (VOoff) expected for this amplifier gain.

VII.

SAMPLE COMPUTATIONS

VIII.

GRAPH

44 IX. QUESTIONS AND PROBLEMS 1. Compare the output voltages. Are there any differences? Explain.

2.

What was the phase difference between the output sine wave and the input sine wave? Explain.

3.

Compare the output offset voltage gains. What do you observe?

4.

When R1 was changed, what effect did it have on the amplifier voltage gain? Explain.

5. X.

Redo the experiment using NI Elvis II. Compare the results obtained.

ANALYSIS AND INTERPRETATION OF RESULTS

45

B. INVERTING VOLTAGE AMPLIFIER I. OBJECTIVE To demonstrate the characteristics of inverting voltage amplifier and significance of the dc output offset for different level of signal inputs BASIC CONCEPT Based on the peak-to-peak output voltage gain (Av) of an amplifier is calculated by dividing the ac peak-to-peak input voltage gain (Vin). Therefore,

II.

The expected voltage gain of the inverting op-amp voltage amplifier shown in Figure 7.2 is the inverse of the amplifier feedback ratio (). Therefore,

The amplifier output offset voltage (VOoff) is equal to the op-amp input offset voltage (VOs) multiplied by the amplifier gain (Av). Therefore,

III.

MATERIALS 1 2 1 2 1 1 1 1 1 LM741 op-amp 1 k (R1, R) 10 k (RFnew) 100 k (RL and RForig) DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires Multisim (LABVIEW)

46

IV.

CIRCUIT DIAGRAM
RF + Vcc Vin R1 2 7 6 3 R 4 - Vcc RL Vout

Figure 7.2 V. PROCEDURE 1. Set the circuit as shown in Figure 7.2. Set the DC power supply to 15 V then connect to the circuit. Note: Use either a function generator for the input or DC input if using a DC input, set the voltage to 1 V. Record the ac peak-to-peak input voltage (Vin) and the ac peak-to-peak output voltage. Set the circuit in dc. Record the dc output offset and the difference between the input and output sine waves. Solve for the expected voltage gain (Av) of the amplifier. Set the value of RF from 100 k to 10 k, the function generator amplitude to 100 mV, oscilloscope channel A input to 100 mV/div and oscilloscope channel B input to 300 mV/div. Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout) and the dc output offset voltage (VOoff). Record the new voltage gain (Av) then solve for the expected voltage gain (Av) of the amplifier. Solve for the expected dc output offset voltage (VOoff).

2. 3. 4.

5. 6. 7.

VI.

DATA AND RESULTS Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout), the dc output offset voltage (VOoff), and the phase diference between the input and output sine waves. Vin = ___________ VOoff = __________ Vout = __________ Phase Diff. = ____

Based on the measured data, calculate the voltage gain (Av) of the amplifier. (R1 = 100 k) (measured)

47

Based on the circuit component values, calculate the expected voltage gain (Av) (R1 = 100 k).

Based on the input offset voltage (VOs) for the op-amp, calculate the dc output offset voltage (VOoff) expected for this amplifier gain.

Record the ac peak-to-peak input voltage (Vin), the ac peak-to-peak output voltage (Vout), and the dc output offset voltage (VOoff). Vin = _________ Vout = _________ VOoff = __________

Based on the measured data, calculate the new voltage gain (Av) of the amplifier. (RF = 10 k) (measured)

Based on the circuit component values, calculate the expected voltage gain (Av). RF = 10 k (calculated)

Based on the input offset voltage (VOs) for the op-amp, calculate the dc output offset voltage (VOoff) expected for this amplifier gain.

48 VII. SAMPLE COMPUTATIONS

VIII.

GRAPH

IX.

QUESTIONS AND PROBLEMS 1. Compare the calculated voltage gain and the measured voltage gain. Explain.

49 2. What was the phase difference between the output sine wave and the input sine wave? Explain.

3. Compare the measured dc output offset voltage with the calculated offset voltage.

4. What percentage error of the peak-to-peak output voltage was the dc output offset voltage? Explain.

5. What RF was changed, what effect did it have on the amplifier voltage gain? Explain.

6. Using multisim, verify the results obtained in the experiment. X. ANALYSIS AND INTERPRETATION OF DATA

50 XI. CONCLUSION

51 EXPERIMENT No. 8 OP-AMP SUMMING AMPLIFIERS

I.

OBJECTIVE Determine the characteristics of op-amp summing amplifier with different dc input voltages, one dc input and one ac input BASIC CONCEPT In summing amplifier the op-amp inverting input is considered to be at virtual ground. Therefore, the input currents can be calculated from and Fromt KCL, the total current can be determined as IT = I1 + I2 Because of the high op-amp input resistance, the feedback current is IF = IT + I2 Because the op-amp inverting is at virtual ground potential, summing amplifier output voltage is equal to the voltage across the feedback resistor and is negative. Therefore, VO = - (IF)(RF) An all important formula when dealing with summing amplifiers is ( )

II.

III.

MATERIALS AND EQUIPMENT 1 2 3 1 2 4 1 1 1 1 1 LM741 op-amp 2.5 k 5 k (R1, R2, RF) 10 k (RL) 5 k potentiometer (1/2 W) 0-2 mA milliammeter DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires

52 IV. CIRCUIT DIAGRAM

RF + Vcc Signal Gen V2 R1 R2 3 4 - Vcc RL 2 7 6 Vout

Figure 8.1 V. PROCEDURE 1. Connect the circuit in Figure 8.1. Using a VOM, set the dc supply to 9 V, then connect to the circuit. 2. Set the function generator to sinusoidal input (V1), and then measure the amplitude to 500 mV. With the use of the potentiometer, set the DC input (V2) to 1 V. Connect both inputs to the circuit. Note: The voltage divider circuit is not on the manual. Device a voltage divider circuit to have a 1 V reading. 3. Observe the display at the oscilloscope then draw the waveform in Graph 8.1. Read the scope display then record the dc and ac output waveform, then record in Table 8.1. Change the value of R1 to 2.5 k, and then observe the change in the output. Change the input voltage (V1) to a dc input using a potentiometer. Set the voltage readings as required in Table 8.2. Measure the voltage output for each input combination then record in the Table.

4.

VI.

DATA AND RESULTS Table 8.1 Vin (dc) 1V 0.1 V Table 8.2 Oscilloscope Reading Expected Reading

Vin (ac) 500 mV 100 mV

V1 +1V -1V -1V +1V Any value

V2 +2V +2V -2V -2V Any value

Measured

Expected

53 VII. SAMPLE COMPUTATIONS

VIII.

GRAPH

IX.

QUESTIONS AND PROBLEMS 1. What is a summing amplifier?

54 2. Derive the equation for solving the voltage gain of a summing amplifier.

3.

How can you modify a summing amplifier to be an averaging and scaling amplifier?

X.

ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

55

EXPERIMENT No. 9 OP-AMP INTEGRATOR AND DIFFERENTIATOR

I.

OBJECTIVE Determine and

analyze

the

characteristics

of

op-amp

integrator

circuit

II.

BASIC CONCEPT The slope of the output ramp, for a step input voltage, is proportional to the input step voltage and is inverted in an op-amp integrator circuit. Therefore,

wherein Vin is the step value of the input voltage. The feedback resistor prevents the op-amp from going into saturation. The output voltage is proportional to the rate of change of the input voltage and is inverted in an op-amp differentiator circuit. The input resistors prevent oscillation. III. MATERIALS AND EQUIPMENT 1 2 1 1 1 1 1 1 1 1 1 1 1 1 LM741 op-amp 0.01 F 0.05 F 0.02 F 500 k 5 k 10 k 1000 k 15 k DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires

56 IV. CIRCUIT DIAGRAM

RF 5k C1 0.01F + Vcc Signal Gen R1 10k 3 4 - Vcc 2 7 6 Vout

Figure 9.1
RF + Vcc Signal Gen R1 C1 2 7 6 3 4 - Vcc Vout

Figure 9.2 V. PROCEDURE 1. Set the circuit as shown in Figure 9.1. Record the input voltage and the output slope in V/ms. Solve for the value of the output slope in V/ms. Record in Table 9.1. 2. Change the function generator amplitude to 2 V and the oscilloscope channel A and Channel B to 2 V/div. Record the input voltage and the output slope in V/ms. Observe. 3. Change R1 from 10 k to 15 k. Record the input voltage and the new output slope in V/ms. Solve for the expected value of the output slope in V/ms. Record in Table 9.2. 4. Change capacitor to 0.02 F. Measure the input voltage and the output slope in V/ms. Solve for the expected value of the output slope in V/ms. Record in Table 9.3. 5. Change R1 to 10 k and capacitor back to 0.01 F and the oscilloscope time base to 1 ms/div. Draw the input and output wave shape. Record in Table 9.4. 6. Change the oscilloscope channel B to 5 V/div and remove the resitor RF from the circuit. Observe.

57 7. Set the circuit in Figure 9.2. Draw the input and output wave shape. Record the input slope in V/ms and the output voltage. Solve for the expected output voltage. Record in Table 9.5. Change the function generator frequency to 2 kHz and the oscilloscope time base to 0.05 ms/div. Record the new input slope in V/ms and the output voltage. Observe. Return the frequency of the function generator to 1 kHz and the time base of the oscilloscope to 1 ms/div. Change the feedback resistor to 10 k. Record the input slope in V/ms and the output voltage. Solve for the expected output voltage. Record in Table 9.6. Change the feedback resistor back to 5 k and change capacitor to 0.1 F. Record the input slope in V/ms and the output voltage. Calculate the expected output voltage. Record in Table 9.7. Change the capacitor back to 0.05 F. Remove the resistor and replace it with a short circuit. Describe what happen. Record in Table 9.8.

8.

9.

10.

11.

VI.

DATA AND RESULTS

Table 9.1 (R1 = 10 k; CF = 0.01 F) Parameters Measured Vin Vout Table 9.2 (R1 = 15 k; CF = 0.01 F) Parameters Measured Vin Vout Table 9.3 (R1 = 10 k; CF = 0.02 F) Parameters Measured Vin Vout Table 9.4 (R1 = 15 k; CF = 0.02 F) Parameters Measured Vin Vout Table 9.5 (RF = 2 k; C1 = 0.05 F) Parameters Measured Vin Vout Table 9.6 (RF = 10 k; C1 = 0.05 F) Parameters Measured Vin Vout

Expected

% Difference

Expected

% Difference

Expected

% Difference

Expected

% Difference

Expected

% Difference

Expected

% Difference

58 Table 9.7 (RF = 5 k; C1 = 0.01 F) Parameters Measured Vin Vout

Expected

% Difference

Table 9.8 (RF = short circuit; C1 = 0.05 F) Parameters Measured Expected Vin Vout

% Difference

VII.

SAMPLE COMPUTATIONS

VIII.

GRAPH

59 IX. QUESTIONS AND PROBLEMS 1. Was the output wave shape for the integrator circuit the integral of the input wave shape? Explain.

2.

How did the calculated value of the integrator output slope compare with the measured value?

3.

Was the value of integrator output slope dependent upon Vin?

4.

Was the value of the integrator output dependent upon input resistor?

5.

Was the value of the integrator output slope dependent upon capacitor? Explain.

6.

Explain why the integrator output slope inverted.

60 X. ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

61 EXPERIMENT No. 10 FEEDBACK AMPLIFIER: Voltage-Series Feedback using Op-Amp

I.

OBJECTIVES To determine and analyze the trade-off of gain for improved input and output resistance for voltage-series feedback BASIC CONCEPT Depending on the relative polarity of the signal being fed back into a circuit, one may have negative or positive feedback. If the feedback signal is of opposite polarity to the input signal, then negative feedback results. A negative feedback results in decreased voltage gain, for which a number of circuit features are improved. Although negative feedback results in reduced overall voltage gain, a number of improvements are obtained. The overall gain with feedback for a voltage-series feedback type is

II.

which shows that the gain with feedback is the amplifier gain reduced by the factor (1 + A). This factor will be seen also to affect input and output impedance among other circuit features.

III.

MATERIALS AND EQUIPMENT 1 1.8 k (R1) 1 200 (R2) 1 LM741 op-amp (or equivalent) 1 1 1 1 1 DC power supply Standard or digital voltmeter Oscilloscope (dual trace preferred) Function Generator Breadboard for constructing circuit Connecting Wires Multisim (LabVIEW)

62

IV.

CIRCUIT DIAGRAM

Vcc1 Vs U1 Vo

Vcc2 R1 R2

Figure 10.1 Voltage-series feedback in an op-amp connection V. PROCEDURE 1. Connect the circuit in Figure 10.1. Using a VOM, set the dc supply to 10 V, then connect to the circuit. 2. Set the function generator to sinusoidal input (V1), and then measure the amplitude to 1 mV. 3. Observe the display at the oscilloscope then draw the waveform in the space provided. 4. Using the values of the components, calculate the voltage gain, A, of the circuit of Figure 10.1. Then, calculate the voltage gain with feedback, A f. Record the data in Table 10.1. 5. Measure Vo and V1 then calculate the voltage gain, A, of the circuit of Figure 10.1. Also, calculate the voltage gain with feedback, Af. Use Table 10.1. 6. Complete Table 10.1 and then compare the measured and calculated values.

VI.

DATA AND RESULTS

Table 10.1 Parameter Expected Value Vi Vo A Af Zif Zof

Measured Value

% Difference

63

VII.

SAMPLE COMPUTATIONS

VIII.

GRAPH

64 IX. 1. 2. X. QUESTION AND PROBLEMS Repeat the experiment using NI Elvis II. Compare the results obtained. Using multisim, verify the results and compare with the data obtained in problem 1. ANALYSIS AND INTERPRETATION OF RESULTS

XI.

CONCLUSION

65 EXPERIMENT No. 11 OSCILLATOR CIRCUITS

I.

OBJECTIVES To generate and measure voltage waveforms in various oscillator circuits BASIC CONCEPT A. Phase Shift Oscillator Oscillator circuits can be built using op-amps with feedback to phase-shift the output signal by 180 . In a phase-shift oscillator, as shown in Figure 11.1, three sections of resistor-capacitor combinations are used. The resulting oscillator frequency can be calculated using For the op-amp to cause the circuit to oscillate requires that the op-amp gain be of magnitude 29. B. Wien-Bridge Oscillator A bridge network can be used to provide the 180 phase shift as shown in Figure 11.2. The circuits resulting frequency can be calculated from If R1 = R2 = R, and C1 = C2 = C, then

II.

C. Square-wave Oscillator A 555 timer IC is a versatile linear digital IC which can be wired for operation as an oscillator, as shown in Figure 11.3. The output resulting from this circuit is a pulse clock waveform of frequency

D. Schmitt-Trigger Oscillator A single Schmitt-trigger IC, resistor, and capacitor can be used to build a pulsetype oscillator circuit, as shown in Figure 11.4. The oscillator frequency is generally calculated using

where k is typically 0.3 to 0.7, depending on the internal triggering levels of the Schmitt-trigger IC.

66 III. MATERIALS AND EQUIPMENT 3 1 1 1 1 3 3 1 1 1 1 1 1 1 1 1 10 k 51 k 100 k 220 k 500 k 0.001 F 0.01 F 15 F 7414 Schmitt-trigger IC 741 op-amp 555 timer IC DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires

IV.

CIRCUIT DIAGRAM

100% VCC

C4 Vo

R1

C1

C2 R2

C3 R3

Figure 11.1 Phase-Shift Oscillator

67

R2 C1 R4 R1 Vo R3 C4

VCC

Figure 11.2 Wien Bridge Oscillator

VCC

RA
4 7 6 2

Vo

555

RB

Figure 11.3 Square-Wave Oscillator

R Vcc
1

68

14 7

Vo

Figure 11.4 Schmitt-Trigger Oscillator V. PROCEDURE a. Phase-Shift Oscillator 1. Construct the circuit shown in Figure 11.1 with RF = 500 k potentiometer, R1 = 22 k, R = 100 k, and C = 0.001 F. 2. Use the oscilloscope to record the output waveform of the oscillator in the space provided in the data sheet. Adjust RF for maximum undistorted output waveform, Vo. Record the value of RF for this undistorted condition. Use Table 11.1. 3. Measure and record the time for one cycle of the waveform. Use Table 11.1. 4. Calculate the frequency of the waveform. Use Table 11.1. 5. Replace the capacitors with C = 0.01 F and repeat Steps 3 and 4. Used Table 11.2. 6. Compare the measured and calculated frequencies for both capacitor values. b. Wien Bridge Oscillator 1. Construct the circuit of Figure 11.2. 2. Using the oscilloscope, observe and record the output waveform in the space provided in the data sheet. 3. Measure the time for one cycle. Use Table 11.3. 4. Calculate the signal frequency. Use Table 11.3. 5. Change both capacitors to C = 0.01 F and repeat Steps 3 and 4. Use Table 11.4. 6. Compare the measured and calculated frequencies for both capacitor values. c. 555 Timer Oscillator 1. Construct the oscillator circuit of Figure 11.3. 2. Observe and record the output waveforms at pins 3 and 4 in the space provided in the data sheet. 3. Measure the period of the output waveform. 4. Calculate the signal frequency. Use Table 11.5.

69 5. Replace the capacitor with C = 0.01 F, and repeat Steps 3 and 4. Use Table 11.6.

d. Schmitt-Trigger Oscillator 1. Construct the oscillator circuit of Figure 11.4. 2. Observe and record the output waveforms at pins 1 and 2 in the space provided in the data sheet. 3. Measure the period of the output waveform. Use Table 11.7. 4. Calculate the signal frequency. Use Table 11.7. 5. Replace the capacitor with C = 0.01 F, and repeat Steps 3 and 4. Use Table 11.8. 6. Compare the calculated value of f for each capacitor with those measured. VI. DATA AND RESULTS Table 11.1 (C = 0.001 Parameter RF T f Table 11.2 (C = 0.01 Parameter T f ) Measured Expected % Difference ) Measured Expected % Difference

Table 11.3 (C = 0.001 Parameter T f

) Measured Expected % Difference

Table 11.4 (C = 0.01 Parameter T f Table 11.5 (C = 0.001 Parameter T f

) Measured Expected % Difference

) Measured Expected % Difference

Table 11.6 (C = 0.01 Parameter T f

) Measured Expected % Difference

70

Table 11.7 (C = 0.001 Parameter T f

) Measured Expected % Difference

Table 11.8 (C = 0.01 Parameter T f

) Measured Expected % Difference

VII.

SAMPLE COMPUTATIONS

VIII.

GRAPH Graph (Phase-Shift Oscillator)

71

Graph (Wien Bridge Oscillator)

Graph (555 Timer Oscillator)

72 Graph (Schmitt-Trigger Oscillator)

IX.

ANALYSIS AND INTERPRETATION OF RESULTS

X.

CONCLUSION

73 EXPERIMENT No. 12 FAMILIARIZATION WITH DIGITAL CIRCUITS

I.

OBJECTIVES

II.

BASIC CONCEPT a. Resistor-Transistor Logic (RTL) RTL circuits consist of resistors and transistors. The basic RTL gate is a NOR gate as shown in Figure 12.1. For the sake of simplicity, a two-input NOR gate driving N similar gates is shown in the figure, which can be extended to accommodate a larger number of inputs. The number of terminals is referred to as the fan-in. b. Direct-Coupled Transistor Logic (DCTL) Removing the base resistors (RB) in Figure 12.1, we obtain what is known as the direct-coupled transistor logic gate, in which the inputs are directly coupled to the bases. c. Diode-Transistor Logic (DTL) DTL circuit using discrete components was made using input diodes and a transistor inverter (NOT), which was modified for integrated circuit implementation as shown in Figure 12.2. d. Transistor-Transitor Logic (TTL) It is possible in TTL gates to hasten the charging of output capacitance without corresponding increase in power dissipation with the help of an output circuit arrangement shown in Figure 12.3. e. Emitter-Coupled Logic (ECL) Basically, ECL is realized using difference amplifier in which the emitters of the two transistors are connected. A 3-input ECL gate is shown in Figure 12.4, which has three parts: The middle part is the difference amplifier which performs the logic operation.

III.

MATERIALS AND EQUIPMENT 11 14 1 1 1 1 1 1N3491 or equivalent 2N2222 or equivalent DC power supply DMM Oscilloscope Function Generator Breadboard for constructing circuit Connecting Wires

74 IV. CIRCUIT DIAGRAM

VCC RC1 640 VCC RC2 640

Vo output

RB3 450

G1

VCC T1 T2 RC3 640

GN RB4 RB1 450 RB2 450 450

Figure 12.1 RTL

VCC

VCC R 5k

Rc 2.2k R 5k DA A DB B RB C DC DA 5k D1 D2 T Vo DA

VCC

D1

D2

R 5k

D1

D2

Figure 12.2 DTL

75

Figure 12.3 TTL gate with totem-pole output driver

Figure 12.4 3-input ECL OR/NOR Gate

V.

PROCEDURE Note: Before handling the ICs (see page ), it is a must that you have read and understood the guidelines listed in page . 1. Construct the circuits shown in part (IV). 2. Set Vcc = 3.6 V for the circuit in Figure 12.1. Set Vcc = 5 V for the circuit in Figure 12.2 and 12.3. Set VEE = -5.2 V for the circuit in Figure 12.4. 3. Using oscilloscope, obtain the graph for each of the circuits shown in part (IV). Observe the behavior of the graph then draw. Use graphs 12.1 to 12.4 for RTL, DTL, TTL, and ECL, respectively in the data sheet provided. Indicate period (duty cycle), T.

76

VI.

DATA AND RESULTS

VII.

GRAPH 12.1

GRAPH 12.2

77

GRAPH 12.3

GRAPH 12.4

78

VIII.

QUESTIONS AND PROBLEMS 1. How is it that perfume can be bad for digital designers?

2. Under what circumstances is it safe to allow an unused CMOS input to float?

3. Explain why putting all the decoupling capacitors in one corner of a printedcircuit board is not a good idea.

4. When is it important to hold hands with a friend?

5. Describe the main benefit and the main drawback of TTL gates that used Schottcky transistors.

79

6. Why is ECL called nonsaturating logic? What is the main advantage accruing from this? With the help of a relevant circuit schematic, briefly describe the operation of ECL OR/NOR logic.

7. Reconstruct Figures 12.1 to 12.4 using the ICs listed in page . Compare the results obtained in part (VI). Explain.

IX.

ANALYSIS AND INTERPRETATION OF RESULTS

X.

CONCLUSION

80

81

82 Guidelines to Handling and Using CMOS Devices The following guidelines should be adhered to while using CMOS family devices: 1. Proper handling of CMOS ICs before they are used and also after they have been mounted on the PC boards is very important as these ICs are highly prone to damage by electrostatic discharge. Although all CMOS ICs have inbuilt protection networks to guard them against electrostatic discharge, precautions should be taken to avoid such an eventuality. While handling unmounted chips, potential differences should be avoided. It is good practice to cover the chips with a conductive foil. Once the chips have been mounted on the PC board, it is good practice again to put conductive clips or conductive tape on the PC board terminals. Remember that PC board is nothing but an extension of the leads of the ICs mounted on it unless it is integrated with the overall system and proper voltages are present. 2. All unused inputs must always be connected to either VSS or VDD depending upon the logic involved. A floating input can result in a faulty logic operation. In the case of highcurrent device types such as buffers, it can also lead to the maximum power dissipation of the chip being exceeded, thus causing device damage. A resistor (typically 220 k to 1M should preferably be connected between input and the VSS or VDD if there is a possibility of device terminals becoming temporarily unconnected or open. 3. The recommended operating supply voltage ranges are 312V for A-series (315V being the maximum rating) and 315V for B-series and UB-series (318V being the maximum). For CMOS IC application circuits that are operated in a linear mode over a portion of the voltage range, such as RC or crystal oscillators, a minimum VDD of 4V is recommended. 4. Input signals should be maintained within the power supply voltage range VSS< Vi < VDD (0.5 V Vi < VDD + 0.5V being the absolute maximum). If the input signal exceeds the recommended input signal range, the input current should be limited to 100 mA. 5. CMOS ICs like active pull-up TTL ICs cannot be connected in WIRE-OR configuration. Paralleling of inputs and outputs of gates is also recommended for ICs in the same package only. 6. The majority of CMOS clocked devices have maximum rise and fall time ratings of normally 515 s. The device may not function properly with larger rise and fall times. The restriction, however, does not apply to those CMOS ICs that have inbuilt Schmitt trigger shaping in the clock circuit.

83 References Boylestad, Robert L., Nashelsky, Louis., Monssen, Franz J. Laboratory Manual (PSpice Emphasis) to Accompany Electronic Devices and Circuit Theory, Ninth Edition. 2006. Laboratory Manual for Electronics 2 Boylestad, Robert L., Nashelsky, Louis. Electronic Devices and Circuit Theory, 10th Edition. 2009. http://highered.mcgraw-hill.com