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A

ZZZ4

LS-4764P

PCB
1

DA80000CG00

Compal Confidential
KIU10 LS-4764P
Schematics Document

Menlow-Silverthorne with Poulsbo


3

REV:1.0
2008/12/02

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


Cover Sheet

Size Document Number


Custom KIU10 LS-4764P

Rev
1.0

Date:

Sheet
E

of

20

Compal Confidential

CPU-Silverthrone
1.33G/1.6G

Model Name : KIU10


File Name : LS-4764P

H_A#(3..35)
H_D#(0..63)

+1.8V

CPU Regulator
Clock Gen.
9UMS9610

FSB

+1.05VS

533MHz

DDR2-533

SCH- Poulsbo

DDR2 64MX16X8pcs
K4T1G164QD

+0.9VS

SingleChannel

+1.5VS

1 SDIO I/F

LVDS I/F

SDVO I/F

PCIE

LPC BUS

PCIE

ATA100 USB2.0 AZALIA

200Pin Golden-Finger

LVDS I/F

LVDS
Connector

SDVO I/F

SDVO to HDMI
Sil1392

PCIE

PCIE

LPC BUS

ATA100 USB2.0

AZALIA

Audio Jack
Audio Codec
ALC 269

LAN RTL8102EL

Port 5

EC
ENE KB926

WLAN/WiMAX

Mono-Speaker

Camera

page33

DCIN/CHARGER

Port 0,1,3

USB Conn X 3
3

BIOS
HDMI
Connector

SPI

TP

BATT Conn/OTP

USB Card Reader


RTS5158
SD/MMC/MS

Port 6

PS/2

+3VALW
Int.KBD

Port 4

3G-Module

LS-4764P
Main-Board

+5VALW
BlueTooth

Port 2

Port 7

SATA HDD
GL831

TV Turner

2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Compal Secret Data

Security Classification

SIM
Connector

Title

Compal Electronics, Inc.


Block Diagram

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
E

of

20

Voltage Rails

O MEANS ON

SKU ID Table

X MEANS OFF

Vcc
Ra

power
plane

+5VS

Board ID

+3VS

* 0

+1.8VS

+VBAT
+5VALW

+1.8V

+3VALW

+0.9V

+1.5VS
+CPU_CORE

1
2
3
4
5
6
7

CLOCK

+VCCP

State

S0

S3

S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery


don't exist

3.3V +/- 5%
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

SKU ID
0
* 1
2
3
4
5
6
7

V AD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

MB ID(H)

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

MB ID(L)

IEL10
IDL11
HDL10

IDL01
HDL00
HDL20
HDL30

IDL12

TBD

MB ID
H
L
O MEANS ON

15"
14"

S3 : STR
S4 : STD
S5 : SOFT OFF

X MEANS OFF

BOM Structure

MARK
@

FUNCTION
NC FOR ALL

USB PORT LIST


PORT

DEVICE

0
1
2
3
4
5
6
7

2A POWER USB
USB (right)
BT
USB(lEFT)
3G, GPS
Camera
Card reader
TV Turner

Address

EC SM Bus1 address
Device
EEPROM(24C16/02)

Address

EC SM Bus2 address
Device

Address

ADM1032

1001 100X b

1010 000X b

Poulsbo SM Bus address


Device

Address

Clock Generator
( ICS954226)

1101 001Xb

Compal Secret Data

Security Classification
2008/07/15

Issued Date

Deciphered Date

2011/07/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


Notes List

Size Document Number


Custom KIU10 LS-4764P
Date:

Tuesday, December 02, 2008

Rev
1.0
Sheet

of

20

P31
T31

CPU_BSEL2

6,14 CPU_BSEL2

R30
M31
U28

GTLREF

MISC

TEST1
TEST2

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
RSVD12

BSEL[0]
BSEL[1]
BSEL[2]

AE14
AD13
E16
F15

COMP0
COMP1
COMP2
COMP3

G2
G6
V31
G4
J2
K27

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGOOD
H_CPUSLP#

R11
R15
R13
R14

H_DSTBN#2 6
H_DSTBP#2 6
H_DINV#2 6
H_D#[48..63] 6

H_ADSTB#0

6
6
6
6
6
6

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#[17..31]

1
1
1
1

2
2
2
2

CPU_BSEL1

CPU_BSEL0

100

133

Resistor placed within


0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

H_ADSTB#1
H_A20M#
H_PBE#

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

B25
D23
E20
A24
B21

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_ADSTB#1

B5
A12
D5
E12
B9
A6
B13
E14
A10
B7
D13
A8
C4
A14
B11
D11

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
ADSTB[1]#

H_A20M#
H_PBE#
H_IGNNE#

G30
J28
H27

H_STPCLK#
H_INTR
H_NMI
H_SMI#

K1
H31
L28
J26

H_STPCLK#
H_INTR
H_NMI
H_SMI#

+1.05VS_C6

1K_0402_1%

R3
D

R16
1
2
10K_0402_5%

Close to CPU pin AD26


within 500mils.
+1.05VS_C6

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#

RSVD7
RSVD8
RSVD9
RSVD10
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

K29

B27
W28
D29

H_DEFER#
H_DRDY#
H_DBSY#

H_ADS# 6
H_BNR# 6
H_BPRI# 6

C28

IERR#
INIT#

H1
F31

H_IERR#
H_INIT#

LOCK#

D25

H_LOCK#

M5
D27
E28
E26
F25

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

E30
F29

H_HIT#
H_HITM#

F1
E2
F5
D3
E4
F7
L2
N2
M1
P1
J4
G26

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#

BR0#

HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
RSVD14

T1

PROCHOT#
THRMDA
THRMDC

H5
T5
U4

THERMTRIP#

T1

STPCLK#
LINT0
LINT1
SMI#

AE16
AF17
AD15
AD17
D9
D7
E8
E10
L30
J30

H_ADS#
H_BNR#
H_BPRI#

H_BR0#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

A20M#
FERR#
IGNNE#

C26
H25
G24

H_DEFER# 6
H_DRDY# 6
H_DBSY# 6
H_BR0#
H_INIT#

H_HIT# 6
H_HITM# 6

R12
2
1
56_0402_5%

PROCHOT# 8,18

H_THERMDA
H_THERMDC

H_THERMDA, H_THERMDC routing together,


Trace width / Spacing = 10 / 10 mil

H_THERMTRIP#

H_THERMTRIP# 6
CLK_CPU_BCLK 14
CLK_CPU_BCLK# 14

K31

VSS0

+1.05VS_C6
A26
E6

RSVD11
RSVD6

V27
AE26

TEST3
CMREF[1]

RSVD13

R17
1K_0402_1%

G28
U30

RSVD15
TEST4

+CMREF
C1

JP13
2

XDP_BPM#3
XDP_BPM#2

XDP_BPM#1
XDP_BPM#0

R27
2K_0402_1%

2
2

C4
0.1U_0402_25V4K

8,15

+1.05VS

XDP_TDI

R19

56_0402_5%

XDP_TMS

R21

56_0402_5%

XDP_TDO

R23

2 @ 56_0402_5%

2 @ 56_0402_5%

XDP_BPM#5

R25

SLPIOVR#

H_RESET#

XDP Reserve
A

R96

H_PWRGOOD
2 1K_0402_5%

TPC24 T4
TPC24 T10
+1.05VS
R122 1
2 1K_0402_1%
TPC24 T11
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_TCK

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

+1.05VS

TPC12

SILVERTHORNE_FCBGA8-441

XDP_BPM#5
XDP_BPM#4

+1.05VS

H_RESET# 6
H_RS#0 6
H_RS#1 6
H_RS#2 6
H_TRDY# 6

P29
R28

BCLK[0]
BCLK[1]

R5
2
1
56_0402_5%

H_LOCK# 6

R20
1K_0402_1%
+CPU_GTLREF

6
6,13

6
13
6
6
6
6
6

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL2

E22
A22
D21
E24
B17
A18
B23
A16
E18
D15
B19
A20
D17
B15
D19

27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
H_DPRSTP# 6,18
H_DPSLP# 6
H_DPWR# 6
H_PWRGOOD 6
H_CPUSLP# 6

+1.05VS_C6

U2A
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

H_DSTBN#3 6
H_DSTBP#3 6
H_DINV#3 6

SILVERTHORNE_FCBGA8-441

CPU_BSEL

H_A#[3..16]

H_INIT#

CONTROL

DATA GRP 2

COMP[0]
COMP[1]
COMP[2]
COMP[3]

AH5
AB5
AJ6
Y1
AF5
AG4
AF3
AC6
AE6
AE4
W4
AC2
AE2
AD1
AA2
AC4
AB1
AA4
Y5

Intel CRB1_5

R1 1
2 H_PBE#
120_0402_5%
R2 1
2 H_A20M#
1K_0402_1%
R4 1
2 H_IGNNE#
1K_0402_5%

1.6G@
SA00002M42L

AJ26

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

+1.05VS_C6

0.1U_0402_25V4K
2
1
2

+CPU_GTLREF

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

THERM
XDP/ITP SIGNALS

H_DSTBN#1
H_DSTBP#1
H_DINV#1

AE24
AC24
AJ20
AE20
AJ22
AF25
AH25
AH23
AH19
AF23
AE18
AH17
AD19
AJ24
AJ18
AF19
AF21
AH21
AE22

AE8
AD7
AH15
AF9
AH9
AE10
AJ16
AF13
AF7
AF15
AH13
AJ14
AJ12
AH7
AJ8
AJ10
AH11
AF11
AE12

ADDR GROUP 1

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

DATA GRP 1

6
6
6

H_DSTBN#0
H_DSTBP#0
H_DINV#0
H_D#[16..31]

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

ADDR GROUP
0

6
6
6
6

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 0

Y27
AH27
Y31
AC30
AE30
AF29
AA26
AB31
W30
AC28
AD31
AF27
AD27
AG28
AB25
AC26
AA28
AA30
AE28

U2

H_D#[32..47] 6

U2B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

H CLK

H_D#[0..15]

DATA GRP 3

Silverthrone Host Data Interface

NC

Silverthrone Host Data Interface

R18
1K_0402_1%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G1
G2

Thermal Sensor
+3VS

C2
1

+3VS

U3

0.1U_0402_16V4Z
H_THERMDA
2200P_0402_50V7K
H_THERMDC
1
2
C3
THERM#
1
2
R26
10K_0402_5%

VDD

SMCLK

EC_SMB_CK2

DP

SMDATA

EC_SMB_DA2

DN

ALERT#

THERM#

GND

THERM_SCI#

EC_SMB_CK2 13
EC_SMB_DA2 13

2
R24
1
10K_0402_5%

1
@ 0_0402_5%
2
+3VS
R22

EC_THERM# 7,8,13

Check : to sb
A

EMC1402-1-ACZL-TR_MSOP8

Address:100_1100

ACES_87151-24051-S
XDP_TRST#

R28

56_0402_5%

XDP_TCK

R29

56_0402_5%

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Silverthorne(1/2)-AGTL+/XDP

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
1

of

20

+1.05VS_C6
+CPU_CORE

VSS1
VSS2
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS41
VSS42
VSS45
VSS46
VSS48
VSS49
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84

VSS162
VSS161
VSS160
VSS159
VSS158
VSS157
VSS156
VSS155
VSS154
VSS153
VSS152
VSS151
VSS149
VSS148
VSS147
VSS146
VSS145
VSS144
VSS143
VSS142
VSS141
VSS140
VSS139
VSS138
VSS137
VSS136
VSS135
VSS134
VSS133
VSS132
VSS131
VSS130
VSS129
VSS128
VSS127
VSS126
VSS125
VSS124
VSS123
VSS122
VSS121
VSS120
VSS119
VSS118
VSS117
VSS116
VSS115
VSS114
VSS113
VSS112
VSS111
VSS110
VSS109
VSS108
VSS107
VSS106
VSS105
VSS104
VSS103
VSS102
VSS101
VSS100
VSS99
VSS98
VSS97
VSS96
VSS95
VSS94
VSS93
VSS92
VSS91
VSS90
VSS89
VSS88
VSS87
VSS86
VSS85

Y29
Y25
Y23
Y21
Y19
Y17
Y15
Y13
Y11
Y9
Y7
Y3
W6
V29
V25
V23
V21
V19
V17
V15
V13
V11
V9
V7
V5
V3
T29
T27
T25
T23
T21
T19
T17
T15
T13
T11
T9
T7
T3
P27
P25
P23
P21
P19
P17
P15
P13
P11
P9
P7
P3
N28
M29
M25
M23
M21
M19
M17
M15
M13
M11
M9
M7
M3
L6
K25
K23
K21
K19
K17
K15
K13
K11
K9
K7
K3
J24

+1.05VS
2
0.1U_0402_16V7K
2
0.1U_0402_16V7K

1
C6
1
C7

AA14
J16

VCCP35
VCCP36

M27

VCCP0

H7
H9
J8

VCCPC61
VCCPC62
VCCPC63

+1.05VS_C6

2
1
0.1U_0402_16V7K C16
2
1U_0402_6.3V6K

1
C18

2
1U_0402_6.3V6K

1
C20

2
1U_0402_6.3V6K

1
C22

2
1U_0402_6.3V6K

1
C24

AA8
AA10
AA12
AA16
AA18
AA20
AA22
AB7
AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23
H11
H13
H15
H17
H19
H21
H23
J10
J12
J14
J18
J20
J22
L26
N26
R26
U26
W26

VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48

L8
L10
L12
L14
L16
L18
L20
L22
L24
N6
N8
N10
N12
N14
N16
N18
N20
N22
N24
R6
R8
R10
R12
R14
R16
R18
R20
R22
R24
U6
U8
U10
U12
U14
U16
U18
U20
U22
U24
W8
W10
W12
W14
W16
W18
W20
W22
W24

VCCA

N30

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE

1
C5

2
330U_D2_2V_Y

2
220U_B2_2.5VM

A4
A28
AA6
AA24
AB3
AB27
AB29
AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22
AD3
AD5
AD9
AD11
AD21
AD23
AD25
AD29
AF1
AF31
AG2
AG6
AG8
AG10
AG12
AG14
AG16
AG18
AG20
AG22
AG24
AG26
AG30
AH3
AH29
AJ4
AJ28
B3
B29
C2
C6
C8
C10
C12
C14
C16
C18
C20
C22
C24
C30
D1
D31
F3
F9
F11
F13
F17
F19
F21
F23
F27
G8
G10
G12
G14
G16
G18
G20
G22
H3
H29
J6

+CPU_CORE

U2C
+

U2D

1
C8

1
2
C136 10U_0603_6.3V6M
<BOM Structure>
1
2
C9
10U_0603_6.3V6M

2
1
10U_0603_6.3V6M C123

1
C10

2
10U_0603_6.3V6M

2
1
10U_0603_6.3V6M C122

1
C14

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C11

1
C15

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C12

1
C17

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C13

1
C19

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C140

1
C21

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C139

1
C23

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C138

1
C25

2
1U_0402_6.3V6K

2
1U_0402_6.3V6K

1
C137

2
1
10U_0603_6.3V6M C121

+1.5VS

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

P5
R4
N4
K5
L4
R2
U2

Length match within 25 mils.


The trace width/space/other is
20/7/25.

C26
0.1U_0402_16V7K
+CPU_CORE

W2

VCCSENSE

V1

VSSSENSE

CPU_VID[0..6]

18

Near pin N30

SILVERTHORNE_FCBGA8-441
<NO_STUFF>

R30
100_0402_1%
1
2

VCCSENSE

R31
100_0402_1%
1
2

VSSSENSE

VCCSENSE 18

VSSSENSE 18

Close to CPU pin


within 500mils.

SILVERTHORNE_FCBGA8-441
<NO_STUFF>
SA00002M42L

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Silverthorne(2/2)-PWR/GND

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
1

of

20

H_STPCLK#

V8
AF4
V2
AA1
AC1
AD2
V4
Y2
U1
Y8
AB2
AF2
AB4
AF8
AE1
AB8
AJ1
AH2
AM8
AN1
AK4
AG1
AH8
AK8
AP8
AK2
AR1
AT8
AT2
AH4
AP4
AP2
AV4
BB6
AV6
AY8
BA1
AU1
AT6
AV8
BB4
AT4
AY6
AV10
AV2
BC1
BB2
AY2
BD2
BH4
BD10
BK10
BD6
BD4
BF2
BE1
BD8
BF4
BH10
BK6
BB8
BF6
BF10
BH6

H_D0#
H_D1#
H_D2#
H_D3#
H_D4#
H_D5#
H_D6#
H_D7#
H_D8#
H_D9#
H_D10#
H_D11#
H_D12#
H_D13#
H_D14#
H_D15#
H_D16#
H_D17#
H_D18#
H_D19#
H_D20#
H_D21#
H_D22#
H_D23#
H_D24#
H_D25#
H_D26#
H_D27#
H_D28#
H_D29#
H_D30#
H_D31#
H_D32#
H_D33#
H_D34#
H_D35#
H_D36#
H_D37#
H_D38#
H_D39#
H_D40#
H_D41#
H_D42#
H_D43#
H_D44#
H_D45#
H_D46#
H_D47#
H_D48#
H_D49#
H_D50#
H_D51#
H_D52#
H_D53#
H_D54#
H_D55#
H_D56#
H_D57#
H_D58#
H_D59#
H_D60#
H_D61#
H_D62#
H_D63#

AB10
AB6
1 R33
2 24_0402_5% AH6
+H_SWNG
V6
AD10
AK6
+H_RCOMP
T10
AT10
AP10
H_THERMTRIP_R# AM6

H_NMI
H_SMI#
H_PBE#
H_SWING
H_STPCLK#
H_TESTIN#
H_RCOMPO
RESERVED5
RESERVED4
H_THRMTRIP#

4,13
4

AF10
AF6

H_INIT#
H_INTR

H_A3#
H_A4#
H_A5#
H_A6#
H_A7#
H_A8#
H_A9#
H_A10#
H_A11#
H_A12#
H_A13#
H_A14#
H_A15#
H_A16#
H_A17#
H_A18#
H_A19#
H_A20#
H_A21#
H_A22#
H_A23#
H_A24#
H_A25#
H_A26#
H_A27#
H_A28#
H_A29#
H_A30#
H_A31#

M2
M8
K4
P2
F4
G1
M4
F6
H6
D2
H2
J1
F2
D4
D12
H12
G11
A7
A9
A11
B6
H8
F10
B10
D6
D10
B12
B4
D8

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

H_ADS#
H_ADSTB0#
H_ADSTB1#
H_GVREF
H_BNR#
H_BPRI#
H_BREQ0#
H_CPURST#
H_CGVREF

K6
H4
B8
Y10
R1
P10
L1
M6
AD4

H_ADS#
H_ADSTB#0
H_ADSTB#1
+H_VREF
H_BNR#
H_BPRI#
H_BR0#
H_RESET#
+H_CGVREF

H_CLKINN
H_CLKINP
H_DBSY#
H_DEFER#
H_DINV0#
H_DINV1#
H_DINV2#
H_DINV3#
H_DPWR#
H_DRDY#
H_DSTBN0#
H_DSTBN1#
H_DSTBN2#
H_DSTBN3#
H_DSTBP0#
H_DSTBP1#
H_DSTBP2#
H_DSTBP3#

K10
M10
H10
AD6
AD8
AM2
AY10
BK8
P6
J9
Y4
AL1
AW1
BH8
W1
AM4
AY4
BF8

CLK_MCH_BCLK#
CLK_MCH_BCLK
H_DBSY#
H_DEFER#
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DPWR#
H_DRDY#
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_HIT#
H_HITM#
H_LOCK#
H_REQ0#
H_REQ1#
H_REQ2#
H_REQ3#
H_REQ4#
H_RS0#
H_RS1#
H_RS2#
H_CPUSLP#
H_TRDY#

V10
T6
Y6
P4
N1
K8
P8
K2
T4
T2
T8
AH10
F12

H_HIT#
H_HITM#
H_LOCK#
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
H_CPUSLP#
H_TRDY#

H_CPUPWRGD
H_DPSLP#
H_DPRSTP#

H_INIT#
H_INTR
CFG0
CFG1
BSEL2

11,12 DDR_A_D[0..63]

U4D
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

H_ADS# 4
H_ADSTB#0 4
H_ADSTB#1 4
H_BNR# 4
H_BPRI# 4
H_BR0#
4
H_RESET# 4
CLK_MCH_BCLK# 14
CLK_MCH_BCLK 14
H_DBSY# 4
H_DEFER# 4
H_DINV#0 4
H_DINV#1 4
H_DINV#2 4
H_DINV#3 4
H_DPWR# 4
H_DRDY# 4
H_DSTBN#0 4
H_DSTBN#1 4
H_DSTBN#2 4
H_DSTBN#3 4
H_DSTBP#0 4
H_DSTBP#1 4
H_DSTBP#2 4
H_DSTBP#3 4
H_HIT#
4
H_HITM# 4
H_LOCK# 4
H_REQ#0 4
H_REQ#1 4
H_REQ#2 4
H_REQ#3 4
H_REQ#4 4
H_RS#0
4
H_RS#1
4
H_RS#2
4
H_CPUSLP# 4
H_TRDY# 4

AP6
F8
AK10

J27
B34
F28

BG49
BG47
BE45
BC43
BE47
BC47
BC45
BK44
BK42
BG41
BK40
BC41
BG43
BJ43
BJ39
BG39
BC39
BK38
BG37
BK36
BJ37
BG35
BJ35
BC35
BK34
BG31
BG33
BK30
BC33
BJ33
BJ31
BC31
BJ29
BG29
BK28
BC29
BE27
BK26
BG25
BJ25
BC25
BG23
BK22
BJ21
BK24
BJ23
BG21
BC21
BK20
BJ19
BG17
BJ17
BG19
BC19
BC17
BK16
BG15
BC15
BJ13
BK12
BK14
BJ15
BC13
BC11

SM_DQ0
SM_DQ1
SM_DQ2
SM_DQ3
SM_DQ4
SM_DQ5
SM_DQ6
SM_DQ7
SM_DQ8
SM_DQ9
SM_DQ10
SM_DQ11
SM_DQ12
SM_DQ13
SM_DQ14
SM_DQ15
SM_DQ16
SM_DQ17
SM_DQ18
SM_DQ19
SM_DQ20
SM_DQ21
SM_DQ22
SM_DQ23
SM_DQ24
SM_DQ25
SM_DQ26
SM_DQ27
SM_DQ28
SM_DQ29
SM_DQ30
SM_DQ31
SM_DQ32
SM_DQ33
SM_DQ34
SM_DQ35
SM_DQ36
SM_DQ37
SM_DQ38
SM_DQ39
SM_DQ40
SM_DQ41
SM_DQ42
SM_DQ43
SM_DQ44
SM_DQ45
SM_DQ46
SM_DQ47
SM_DQ48
SM_DQ49
SM_DQ50
SM_DQ51
SM_DQ52
SM_DQ53
SM_DQ54
SM_DQ55
SM_DQ56
SM_DQ57
SM_DQ58
SM_DQ59
SM_DQ60
SM_DQ61
SM_DQ62
SM_DQ63

MEMORY

H_NMI
H_SMI#
H_PBE#

H_A#[3..31] 4

U4A
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

4
4
4

SYSTEM

H_D#[0..63]

HOST

DDR

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

SM_BS0
SM_BS1
SM_BS2

BC27
BE25
BA35

SM_CK0
SM_CK1

BG45
BE11

M_CLK_DDR0 11,12
M_CLK_DDR1 11,12

SM_CK0#
SM_CK1#

BJ45
BG11

M_CLK_DDR#0 11,12
M_CLK_DDR#1 11,12

SM_CKE0
SM_CKE1

BE39
BE37

M_CKE0
M_CKE1

SM_DQS0
SM_DQS1
SM_DQS2
SM_DQS3
SM_DQS4
SM_DQS5
SM_DQS6
SM_DQS7

BJ47
BJ41
BC37
BK32
BG27
BE23
BK18
BG13

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

SM_MA0
SM_MA1
SM_MA2
SM_MA3
SM_MA4
SM_MA5
SM_MA6
SM_MA7
SM_MA8
SM_MA9
SM_MA10
SM_MA11
SM_MA12
SM_MA13
SM_MA14

BJ27
BA19
BA27
BA25
BE29
BC23
BE31
BA31
BA33
BA29
BE17
BE35
BE33
BE19
BA37

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

SM_VREF

BE43

+SM_VREF

SM_RAS#
SM_CAS#

BE21
BA13

DDR_A_RAS#
DDR_A_CAS#

BA17

DDR_A_WE#

SM_WE#
SM_CS0#
SM_CS1#

BA23
BA15

SM_RCOMPO

BE13

SM_RCVENIN
SM_RCVENOUT

BA39
BE41

DDR_A_BS#0 11,12
DDR_A_BS#1 11,12
DDR_A_BS#2 11,12

11
12

DDR_A_DQS[0..7]

11,12

DDR_A_MA[0..13] 11,12

DDR_A_RAS# 11,12
DDR_A_CAS# 11,12
DDR_A_WE# 11,12
M_CS#0
M_CS#1

R32

2
30.1_0402_1%

11
12
+0.9VS

C173
2

0.1U_0402_16V4Z

C172
10U_0603_6.3V6M

C172,C173 close SM_RCOMPO pin

POULSBO_FCBGA1249

H_PWRGOOD 4
H_DPSLP# 4
H_DPRSTP# 4,18
R35
R36
R37

CFG0

2 10K_0402_5%
2@ 10K_0402_5%
2 10K_0402_5%

1
1
1

+1.05VS

CPU_BSEL2 4,14

POULSBO_FCBGA1249

layout note:

FSB DDR

100

100

100

133

133

133

133

100

+H_CGVREF

1
R42

R41
1K_0402_1%

within 100 mils from NB


5

R39
10K_0402_1%

+SM_VREF
R40
C28

R43
10K_0402_1%
0.1U_0402_16V4Z
2
<BOM Structure>

within 2" from R48

1
C27

+1.8V

H_THERMTRIP_R# 1

2
24_0402_5%
<BOM Structure>

H_THERMTRIP# 4

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Near B3 pin
4

In pre-ES R571=2k H_CGVREF=2/3VCCP


In ES R571 choose 1k

R44
120_0402_5%
R48
2

2
1
R47

0.1U_0402_16V4Z
C30

2K_0402_1%

+H_SWNG
100_0402_1%

C29

+H_RCOMP
R46
24.9_0402_1%
2
1

2
1

R45

+1.05VS_C6

<BOM Structure>

0.1U_0402_16V4Z
+H_VREF

10K pull-down is required.

221_0603_1%

CFG1

0.1U_0402_16V4Z

+1.05VS
+1.05VS

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

R38

CFG0

FSB

FSB DDR

BSEL2

2
1
1K_0402_1%

FSB

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

2
1
1K_0402_1%

+1.05VS

Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces

Title

Compal Electronics, Inc.


Poulsbo(1/5)-HOST/DDR

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Saturday, December 06, 2008

Sheet
1

of

20

13 LPC_FRAME#

K40

ENBKL

+3VS

13
13

LVDSAC+
LVDSAC-

13
13
13

LVDSA0LVDSA1LVDSA2-

13
13
13

13
13
13

13 MINSD_DATA[0..3]

AF48
AF50

LVDSA0LVDSA1LVDSA2-

AJ43
AK48
AH48
AG45

LVDSA0+
LVDSA1+
LVDSA2+

AJ45
AK50
AH50
AG43

+3VS

R118 1

2 10K_0402_5%

+3VS

R175 1
R179 1
R117 1

2@ 47_0402_5%
2@ 47_0402_5%
2 39K_0402_5%

MINSD_CD#
MINSD_CLK
MINSD_CMD

13 MINSD_WP
13 MINSD_PWR#

LVDSA0+
LVDSA1+
LVDSA2+

LVDSAC+
LVDSAC-

MINSD_DATA0
MINSD_DATA1
MINSD_DATA2
MINSD_DATA3

R174
R176
R177
R178

MINSD_CD#
MINSD_CLK_R
MINSD_CMD_R

MINSD_DATA0_R
MINSD_DATA1_R
MINSD_DATA2_R
MINSD_DATA3_R

2@ 47_0402_5%
2@ 47_0402_5%
2@ 47_0402_5%
2@ 47_0402_5%

1
1
1
1

+3VS

+3VS

1
R116

2
10K_0402_5%

1
R62

2
10K_0402_5%

1
R63
1
R64

2
10K_0402_5%
SD2_CMD_R
2
39K_0402_5%

+3VS

T16
T17
T18
T19

R65
B

0_0402_5%

L_BKLTCTL
L_BKLTEN
L_CTLA_CLK
L_CTLB_DATA
L_DDCCLK
L_DDCDATA
L_VDDEN
LA_CLKP
LA_CLKN

SD0_CD#
SD0_CLK
SD0_CMD
SD0_LED
SD0_WP
SD0_PWR#
SD0_DATA0
SD0_DATA1
SD0_DATA2
SD0_DATA3
SD0_DATA4
SD0_DATA5
SD0_DATA6
SD0_DATA7

B22
H22
F20
A21
B20
D20
F22
J19
K22
D22

SD1_CD#
SD1_CLK
SD1_CMD
SD1_LED
SD1_WP
SD1_PWR#
SD1_DATA0
SD1_DATA1
SD1_DATA2
SD1_DATA3

K24
D26
B24
D24
B26
A19
J23
A25
F26
A23
F24
H24
H26
E25
G21

ICH_RTCRST#

SD2_CD#
SD2_CLK
SD2_CMD
SD2_LED
SD2_WP
SD2_PWR#
SD2_DATA0
SD2_DATA1
SD2_DATA2
SD2_DATA3
SD2_DATA4
SD2_DATA5
SD2_DATA6
SD2_DATA7
RESERVED18

ICH_RTCRST# 13

RESERVED0
RESERVED1
RESERVED2
RESERVED3

C31
1U_0402_6.3V6K

R58

E49
B32
BE15
BA21

2
ICH_RTCX1

10K_0402_5%

R67
10M_0402_5%

LA_DATAP0
LA_DATAP1
LA_DATAP2
LA_DATAP3

B18
D18
J15
H18
F18
H20
H16
A17
K18
F16
K16
B16
D16
K20

R54
1

20K_0402_5%

LA_DATAN0
LA_DATAN1
LA_DATAN2
LA_DATAN3

SDIO / MMC

TPC12
TPC12
TPC12
TPC12

LPC_FRAME#

LVDS

13 EDID_CLK_LCD
13 EDID_DAT_LCD
13 GMCH_LVDDEN

R53 1
2 10K_0402_5%
R57 1
2 10K_0402_5%
EDID_CLK_LCD
EDID_DAT_LCD
GMCH_LVDDEN

A33
A31
D28
K26
A27
H28
D30

LPC_CLKRUN#
LPC_SERIRQ

+RTCVCC

15P_50V_0402_NPO

C36

LPC_CLKRUN# D36
SIRQ
B38

LPC_CLKOUT0
LPC_CLKOUT1
LPC_CLKOUT2

BK50

RTC_X1
RTC_X2
INTVRMEN
RTCRST#
EXTTS
PWROK
SLPRDY#
DPRSLPVR
SLPMODE
RSMRST#
SDVO_CTRLCLK
SDVO_CTRLDATA
SDVOB_CLK
SDVOB_CLK#
SDVOB_INT
SDVOB_INT#
SDVOB_STALL
SDVOB_STALL#
SDVOB_TVCLKIN
SDVOB_TVCLKIN#
SDVOB_RED
SDVOB_RED#
SDVOB_GREEN
SDVOB_GREEN#
SDVOB_BLUE
SDVOB_BLUE#
PCIE_PERn1
PCIE_PERp1
PCIE_PETn1
PCIE_PETp1
PCIE_PERn2
PCIE_PERp2
PCIE_PETn2
PCIE_PETp2
PCIE_CLKINN
PCIE_CLKINP
PCIE_ICOMPI
PCIE_ICOMPO

ICH_RTCX1
ICH_RTCX2

F48
F50
F46
H48
D32
C49
J49

32.768KHZ_12.5P_1TJE125DP1A000M
2 R59
10K_0402_5%

ICH_RTCRST#
R60
R61
ICH_POK

2 10K_0402_5%
2 10K_0402_5%

1
1

+RTCVCC

ICH_RTCX2

!!Input
EC_THERM# 4,8,13

L45

PM_SLPMODE 13

L43

11/07:change C36, C37 from 10P to 15P

EC_RSMRST# 13
SDVO_CTRLCLK
SDVO_CTRLDATA
SDVO_CLK
SDVO_CLK#

SDVO_CTRLCLK 13
SDVO_CTRLDATA 13
SDVO_CLK 13
SDVO_CLK# 13
SDVO_INT 13
SDVO_INT# 13

AM50 SDVO_RED
AM48 SDVO_RED#
AT50 SDVO_GREEN
AT48 SDVO_GREEN#
AR45 SDVO_BLUE
AR43 SDVO_BLUE#

SDVO_RED 13
SDVO_RED# 13
SDVO_GREEN 13
SDVO_GREEN# 13
SDVO_BLUE 13
SDVO_BLUE# 13

AW45 PCIE_PTX_C_IRX_N1
AW43 PCIE_PTX_C_IRX_P1
BB48 PCIE_ITX_PRX_N1
BB50 PCIE_ITX_PRX_P1

C32
C33

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1

BA43 PCIE_WLANTX_IRX_C_N2
BA45 PCIE_WLANTX_IRX_C_P2
BE49 PCIE_ITX_WLANRX_N2 C34
BD50 PCIE_ITX_WLANRX_P2 C35

1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

PCIE_WLANTX_IRX_C_N2
PCIE_WLANTX_IRX_C_P2
PCIE_ITX_C_WLANRX_N2
PCIE_ITX_C_WLANRX_P2

BA47
BA49

C37

ICH_POK 13
PM_SLPRDY# 13
DPRSLPVR 18

AY48
AY50

15P_50V_0402_NPO

from CPU thermal sensor

+3VS

D34

F30
A29
AV48
AV50
AU47
AU49
AN45
AN43
AP48
AP50

X1
2

13

F38
B36
D38

ENBKL
2
100K_0402_5%
GMCH_LVDDEN
2
100K_0402_5%

LPC_CLKOUT0

SIRQ

13
1
R56
1
R115

2 22_0402_5%

RESERVED8

R55

13 CLK_PCI_LPC

U4B
K38 LPC_AD0
J39 LPC_AD1
A35
LPC_AD2
L39 LPC_AD3

MISC SIGNALS

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

SYSTEM MGMT RTC

LPC_CLKRUN#
2
10K_0402_5%
SIRQ
2
8.2K_0402_5%
EDID_CLK_LCD
2
10K_0402_5%
EDID_DAT_LCD
2
10K_0402_5%

LPC BUS

1
R49
1
R50
1
R51
1
R52

SDVO

13 LPC_AD[0..3]
+3VS

PCIE

CLK_PCIE_ICH#
CLK_PCIE_ICH

13
13
13
13

LAN
13
13
13
13

WLAN

CLK_PCIE_ICH# 14
CLK_PCIE_ICH 14

+PCIE_ICOMP

R66
1

24.9_0402_1%
2

+1.5VS

POULSBO_FCBGA1249

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Poulsbo(2/5)-LVDS/SDVO/SDIO/PCIE

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Saturday, December 06, 2008

Sheet
1

of

20

U4C

+3VS
+3VS

PD_A2
PD_A1
PD_A0

K42
J45
H40

PATA_DA2
PATA_DA1
PATA_DA0

B40
E43
H42
D42
F40
A43
A41
J41
A39
B42
F42
D44
L41
B44
G43
D40

PATA_DD15
PATA_DD14
PATA_DD13
PATA_DD12
PATA_DD11
PATA_DD10
PATA_DD9
PATA_DD8
PATA_DD7
PATA_DD6
PATA_DD5
PATA_DD4
PATA_DD3
PATA_DD2
PATA_DD1
PATA_DD0

PD_D15
PD_D14
PD_D13
PD_D12
PD_D11
PD_D10
PD_D9
PD_D8
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

C41
10U_0603_6.3V6M

+3VALW

SCH_PCIE_WAKE# 1
R71

EC_THERM#

TRST#
TMS
TDI
TDO
TCK

N49
M50
K48
M48
N47

STPCPU#

H30

No-Connect

CLOCK I/F
SMB

RSTRDY#
RESET#
RSTWARN
GPIOSUS0
GPIOSUS1
GPIOSUS2
GPIOSUS3
WAKE#
SMI#
THRM#
GPE#
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
SPKR
HDA_CLK
HDA_SYNC
HDA_RST#
HDA_SDI0
HDA_SDI1
HDA_SDO
HDA_DOCKEN#
HDA_DOCKRST#
RESERVED6
RESERVED7
DA_REFCLKINN
DA_REFCLKINP
DB_REFCLKINNSSC
DB_REFCLKINPSSC
CLKREQ#
CLK14
USB_CLK48
SUSCLK
SMB_ALERT#
SMB_DATA
SMB_CLK

H50
BA41
K50
U41
N43
N45
R41
N41
B30
F32
P50
G29
K30
F34
G33
K36
H36
F36
J31
H34
K28
J35
K14
E13
A13
F14
B14
D14
E15
H14

2 R125
1
10K_0402_5%

@ 1
R72

2
8.2K_0402_5%

+1.05VS
T12
T13
T14
T15

TPC12
TPC12
TPC12
TPC12

GPIO3
100_0402_1%
R73 1
2
PLT_RST#

FFFB0000h

PM_RSTRDY# 13
PLT_RST# 13
PM_RSTWARN 13

FFFC0000h(for 2G)

FFFD0000h(Default)

FFFE0000h

*
+3VS

EC_SMI# 13
EC_THERM# 4,7,13
EC_SCI# 13

GPIO0

R74
10K_0402_5%
GPIO3
BT_DET# 13

1
1
1
1

R81
C45
1

AU43
AU45
AL45
AL43
AE45
AE43
B28
H32
W41
J47

SLPIOVR# 4,15
PROCHOT# 4,18
+3VS

1
2
R76 10K_0402_5%
R180
R78
R79
R80

2
2
2
2

39_0402_5%
39_0402_5%
39_0402_5%
39_0402_5%

1
2
39_0402_5%

R82
2
1

2 R124
1
10K_0402_5%

CLK_MCH_DREFCLK# 14
CLK_MCH_DREFCLK 14
MCH_SSCDREFCLK# 14
MCH_SSCDREFCLK 14

PAD

K32
G37
H38

SMB_DAT 14
SMB_CLK 14
R85

+3VS

1
R126 @

CMC
CMC
CMC
CMC

GPIO0 GPIO3
0
0
0
1
1
0
1
1

+3VS

2008/07/15

1
2
GPIO3L@ 1K_0402_1%

RAM_Vendor RAM_Type R131 R75


Samsung
1Gbx8
X
V
Hynix
1Gbx8
X
X *(Default)
Nanya
1Gbx8
V
V
Micron
2Gbx8
V
X

GPIO0: Internal pull-down 22k


GPIO3: Internal Pull-high 22k

Compal Secret Data

Security Classification

GPIO3
2
1K_0402_1% R75

2
1K_0402_1%

R84

GPIO0
1
2
1
R131 GPIO0H@ 1K_0402_1% R127 @

CLK_14M_SCH 14
T5

+3VS

+3VS

2.7K_0402_5% 2.7K_0402_5%

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

R77
10K_0402_5%

SPKR
13
HDA_BITCLK_AUDIO 13
HDA_SYNC_AUDIO 13
HDA_RST_AUDIO# 13
HDA_SDIN0 13
HDA_SDIN1 13
HDA_SDOUT_AUDIO 13

10_0402_5% @
2

10P_0402_50V8J @

R83
10K_0402_5%

Issued Date

CMC Base Address

SB_INT_FLASH_SEL 13
PBTN_OUT# 13
EC_LID_OUT# 13
SCH_PCIE_WAKE#
EC_SMI#

GPIO0

H_STP_CPU# 14

POULSBO_FCBGA1249

2
1K_0402_5%

+3VS

R70
2
1 PD_IORDY
4.7K_0402_5%
R123
2
1 PD_IRQ
10K_0402_5%

1
C40

PD_D15
PD_D14
PD_D13
PD_D12
PD_D11
PD_D10
PD_D9
PD_D8
PD_D7
PD_D6
PD_D5
PD_D4
PD_D3
PD_D2
PD_D1
PD_D0

PATA_DDREQ
PATA_IORDY
PATA_IDEIRQ
PATA_DDACK#
PATA_DIOW#
PATA_DIOR#
PATA_DCS3#
PATA_DCS1#

1
C39

13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13

USB_RBIASN
USB_RBIASP

J43
D46
G45
B46
A37
F44
C47
E47

1
C38

PD_A2
PD_A1
PD_A0

AC45
AC43

PD_DREQ
PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#
PD_CS#3
PD_CS#1

13
13
13

+USB_RBIAS

AW13
AV12
AU13
AT12
AR13
AP12
AN13
AM12
AL13
AK12
AJ13
AH12
AG13
AF12
AE13
AC13
AB12
AA13
Y12
W13
V12
U13
T12
R13
P12
N13
M14
M12
AD12

PD_DREQ
PD_IORDY
PD_IRQ
PD_DACK#
PD_IOW#
PD_IOR#
PD_CS#3
PD_CS#1

PATA/IDE

13
13
13
13
13
13
13
13

JTAG

R69
1
2
22.6_0402_1%

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_16

2
10K_0402_5%

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

SYSTEM GPIOs

+1.05VS

R43
W45
R45
U43
AA45
AA43
W43
U45

R68

USB_DN0
USB_DP0
USB_DN1
USB_DP1
USB_DN2
USB_DP2
USB_DN3
USB_DP3
USB_DN4
USB_DP4
USB_DN5
USB_DP5
USB_DN6
USB_DP6
USB_DN7
USB_DP7

Termination Voltage

+3VALW

AE47
AE49
AD48
AD50
AB50
AB48
AA49
AA47
Y48
Y50
V50
V48
U47
U49
T50
T48

HD AUDIO

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N5
USB20_P5
USB20_N6
USB20_P6
USB20_N7
USB20_P7

USB (right)

USB I/F

13
13
13
13
13
BT
13
13
USB (Left)
13
13
USB (WWAN)
13
USB (int-Camera)13
13
13
Crard reader
13
USB (TV Turner) 13
13

2A USB power

Title

Compal Electronics, Inc.


Poulsbo(3/5)-HDA/PATA/USB

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Saturday, December 06, 2008

Sheet
1

of

20

5
4

C67

Place under Poulsbo

Issued Date

1
1

2
2

Security Classification

2008/07/15
1

2
C70
2

1
1

Compal Secret Data

C64

C69
C72

C71

R90
1

Deciphered Date

C73
1

+1.5VS

R89
0_0402_5%
+1.5VS

C75
2

2011/07/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C74
1

+VCCADPLL

+3VALW
C65 1

Title

Date:

C66 1

C68
1
2

2
+1.5VS

+V5_5REF_SCH
2

T7

AW41
AY42

+1.5VS
T6

1
1
C51
+
C50
4.7U_0603_6.3V6K
2
2

+1.5VS

C54
+
1

R86
0_0402_5%

+1.8V

+V5_5REFSUS_SCH
D1

+V5_5REFSUS_SCH

R88

0_0402_5%

2
D2

+V5_5REF_SCH

Saturday, December 06, 2008


1

Sheet
9

150U_B2_6.3VM_R35M

10U_0603_6.3V6M

C57

1U_0402_6.3V6K

C55

150U_B2_6.3VM_R35M

0.1U_0402_16V7K

C49

AB38
AA37
W37

+3VALW

R87

+3VS

R132

of

10_0402_5%

1U_0402_6.3V6K

VCCAPCIEBG
VSSAPCIEBG

CH751H-40PT_SOD323-2

RESERVED12
RESERVED11
RESERVED13

0.1U_0402_16V7K

VCC15USB_1
VCC15USB_2
VCC15USB_3
VCC15USB_4
VCC15USB_5
VCC15USB_6

0.1U_0402_16V7K

0.1U_0402_16V7K
2

0.1U_0402_16V7K

VCC5REFSUS

P38
P36

0.1U_0402_16V7K

AA41

VCCADPLLA
VCCAPCIEPLL
VCCADPLLB
VCC5REF_1

C47

+3VS

RESERVED10
RESERVED9

T8 T9
PAD PAD

AE39
AN49
AG39
K34

C46

10_0402_5%

CH751H-40PT_SOD323-2

150U_B2_6.3VM_R35M
C63

VSSAUSBBGSUS
VCCAUSBBGSUS

0.1U_0402_16V7K

+
AC41
AE41

VCC
R33
R31
R29
R27
R25
R23
R21
R19
R17
R15
P34
P32
N33
N31
M38
M36
M34
M32

2
C62
+VCCAHPLL

+RTCVCC

0.1U_0402_16V7K

VCC15_1
VCC15_2
VCC15_3
VCC15_4
VCC15_5
VCC15_6
VCC15_7
VCC15_8
VCC15_9
VCC15_10
VCC15_11
VCC15_12
VCC15_13
VCC15_14
VCC15_15
VCC15_16
VCC15_17
VCC15_18

2
1

1U_0402_6.3V6K

V22
V20
V18
AB18
AB16
Y30
Y28
Y26
Y24
Y22
T34
T32
T30
T28
T26
T24
T22
T20
T18
T16
AK22
AK20
AK18
AK16
AH34
AH32
AH30
AH28
AH26
AH24
AH22
AH20
AH18
AH16
AF34
AF32
AF30
AF28
AF26
AF24
AF22
AF20
AF18
AF16
AD30
AD28
AD26
AD24
AD22
AD20
AD18
AD16
AB30
AB28
AB26
AB24
AB22
AB20
AM34
AM32
AM30
AM28
AM26
AM24
AM22
AM20
AM18
AM16
AK34
AK32
AK30
AK28
AK26
AK24
V16
Y18
Y16
V34
V32
V30
V28
V26
V24
Y20

0.1U_0402_16V7K

C61

2
1

C60

1U_0402_6.3V6K

2
1

+VCCAUSBPLL

C59
+3VALW

0.1U_0402_16V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

VCCSDVO_110
VCCSDVO_100
VCCSDVO_101
VCCSDVO_103
VCCSDVO_106
VCCSDVO_105

VCC33_15
VCC33_14
VCC33_13
VCC33_12
VCC33_11
VCC33_10
VCC33_9
VCC33_6
VCC33_8
VCC33_7
VCC33_5
VCC33_4
VCC33_3
VCC33_2
VCC33_1
VCC33_16
VCC33RTC
VCCHDA_1
VCCHDA_2
VCCAUSBPLL
VCCDHPLL
VCCAHPLL

AK36
AJ37
AH38
AH36
AK38
AL37

M18
M20
M22
M24
M26
M28
M30
N19
N15
N17
N21
N23
N25
N27
N29
M16
A45
K12
J11
AC39
BB10
BA11

2
VCCPCIE_4
VCCPCIE_5
VCCPCIE_6
VCCPCIE_7
VCCPCIE_8
VCCPCIE_9
VCCPCIE_1
VCCPCIE_2
VCCPCIE_3
VCCPCIE_100
VCCPCIE_101

0.1U_0402_16V7K

+1.5VS
AT34
AT32
AR37
AP38
AP36
AN37
AU37
AT38
AT36
AM36
AV38

RESERVED14
RESERVED15
RESERVED16
RESERVED17
VCCP33USBSUS_2
VCCP33USBSUS_1
VCCP33USBSUS_3
VCC33SUS_3
VCC33SUS_2
VCC33SUS_1

C56
VCCLVDS_101
VCCLVDS_100
VCCLVDS_1
VCCLVDS_2
VCCLVDS_3

0.1U_0402_16V7K

N37
N35
AC37
AB36
Y38
AA39
W39
T38
U37
R39

1
AG37
AF38
AF36
AE37
AD36

10U_0603_6.3V6M

+1.5VS
VCC_79
VCC_80
VCC_81
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_10
VCC_9
VCC_8
VCC_7
VCC_6
VCC_5
VCC_4
VCC_3
VCC_2
VCC_1
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_120
VCC_121
VCC_82
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_70

U4E

1U_0402_6.3V6K

VCCSM_43
VCCSM_100
VCCSM_101
VCCSM_102
VCCSM_103
VCCSM_104
VCCSM_105
VCCSM_106
VCCSM_107
VCCSM_108
VCCSM_10
VCCSM_1
VCCSM_2
VCCSM_3
VCCSM_4
VCCSM_5
VCCSM_6
VCCSM_7
VCCSM_21
VCCSM_22
VCCSM_23
VCCSM_24
VCCSM_25
VCCSM_26
VCCSM_27
VCCSM_28
VCCSM_29
VCCSM_30
VCCSM_31
VCCSM_32
VCCSM_33
VCCSM_34
VCCSM_35
VCCSM_36
VCCSM_37
VCCSM_38
VCCSM_39
VCCSM_40
VCCSM_41
VCCSM_42

1U_0402_6.3V6K

AP16
AW35
AW33
AW31
AW29
AW27
AW25
AW23
AW21
AW19
AW37
AW17
AV36
AV34
AV32
AV30
AV28
AV26
AV24
AV22
AV20
AV18
AV16
AT30
AT28
AT26
AT24
AT22
AT20
AT18
AT16
AP34
AP32
AP30
AP28
AP26
AP24
AP22
AP20
AP18

2
1U_0402_6.3V6K

+1.5VS
C53

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

5
1

+1.05VS

C48

C52

Place under Poulsbo

Place under Poulsbo

AD34
AD32
AB34
AB32
Y34
Y32

PAD
C

+3VS

PAD

C58
1

POULSBO_FCBGA1249
+5VALW

Size Document Number


Custom KIU10 LS-4764P
20

+5VS

1 0_0402_5%
A

Poulsbo(4/5)-PWR

Compal Electronics, Inc.


Rev
1.0

U4F

VSS

BB24
BB22
BA7
BA5
BA3
AY46
AY44
AY40
AY38
AY36
AY34
AY32
AY30
AY28
AY26
AY24
AY22
AY20
AY18
AY16
AY14
AY12
AW49
AW47
AW39
AW15
AW11
AW9
AW7
AW5
AW3
AV46
AV44
AV42
AV40
AV14
AU41
AU39
AU35
AU33
AU31
AU29
AU27
AU25
AU23
AU21
AU19
AU17
AU15
AU11
AU9
AU7
AU5
AU3
AT46
AT44
AT42
AT40
AT14
AR49
AR47
AR41
AR39
AR35
AR33
AR31
AR29
AR27
AR25
AR23
AR21
AR19
AR17
AR15
AR11
AR9
AR7
AR5
AR3
AP46
AP44
AP42
AP40
AP14
AN47
AN41
AN39
AN35
AN33
AN31
AN29
AN27
AN25
AN23
AN21
AN19
AN17
AN15
AN11
AN9
AN7
AN5
AN3
AM46
AL7
AL5

U4G
W35
W33
W31
W29
W27
W25
W23
W21
W19
W17
W15
W11
W9
W7
W5
W3
V46
V44
V42
AJ41
AJ47
AJ49
AK14
AK40
AK44
AJ5
AJ7
AJ9
AJ11
AJ15
AJ17
AJ19
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AJ33
AJ35
AJ39
L9
L7
L5
L3
K46
K44
J37
J33
J29
J25
J21
U27
U25
G47
G41
G39
G35
G31
G27
G25
G23
C19
C17
C15
C13
G3
E45
BJ1
BH50
BH48
BH46
BH44
BH42

VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_157
VSS_179
VSS_178
VSS_177
VSS_176
VSS_175
VSS_174
VSS_173
VSS_172
VSS_171
VSS_170
VSS_169
VSS_168
VSS_167
VSS_166
VSS_165
VSS_164
VSS_323
VSS_324
VSS_325
VSS_326
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_709
VSS_710
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_504
VSS_503
VSS_502
VSS_501
VSS_505
VSS_506
VSS_1014
VSS_1015
VSS_1016
VSS_1017
VSS_1018
VSS_1019

AJ3
AH46
AH44
AH42
AH40
AH14
AG49
AG47
AG41
AG35
AG33
AG31
AG29
AG27
AG25
AG23
AG21
AG19
AG17
AG15
AG11
AG9
AG7
AG5
AG3
AF46
AF44
AF42
AF40
AF14
AE35
AE33
AE31
AE29
AE27
AE25
AE23
AE21
AE19
AE17
AE15
AE11
AE9
AE7
AE5
AE3
AD46
AD44
AD42
AD40
AD38
AD14
AC49
AC47
AC35
AC33
AC31
AC29
AC27
AC25
AC23
AC21
AC19
AC17
AC15
AC11
AC9
AC7
AC5
AC3
AB46
AB44
AB42
AB40
AB14
AA35
AA33
AA31
AA29
AA27
AA25
AA23
AA21

VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262

VSS_76
VSS_77
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_384
VSS_385
VSS_386
VSS_387
VSS_388
VSS_389
VSS_390
VSS_391
VSS_392
VSS_393
VSS_394
VSS_395
VSS_396
VSS_397
VSS_398
VSS_399
VSS_400
VSS_401
VSS_402
VSS_522
VSS_405
VSS_406
VSS_407
VSS_408
VSS_409
VSS_410
VSS_411
VSS_412
VSS_413
VSS_510
VSS_511

VSS

VSS_1023
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_292
VSS_291
VSS_290
VSS_289
VSS_288
VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
VSS_280
VSS_279
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_158
VSS_404
VSS_403
VSS_383
VSS_378
VSS_379
VSS_380
VSS_381
VSS_382
VSS_508
VSS_507
VSS_882
VSS_881
VSS_1003
VSS_1000
VSS_1001
VSS_1004
VSS_1005
VSS_1006
VSS_1007
VSS_1008
VSS_1009
VSS_1010
VSS_1011
VSS_1012
VSS_1013

BH34
AA19
AA17
AA15
AA11
AA9
AA7
AA5
AA3
Y46
Y44
Y42
Y40
Y36
Y14
W49
W47
N9
N7
N5
N3
M46
M44
M42
M40
L49
L47
L37
L35
L33
L31
L29
L27
L25
L23
L21
L19
L17
L15
L13
L11
G19
G17
G15
G13
G9
G7
G5
AK42
E21
E23
E27
E29
E31
E33
E35
E37
E39
E41
A49
B2
A15
A5
A3
BK48
BK46
BK4
BK2
BJ49
BJ11
BJ9
BJ7
BJ5
BJ3

VSS_1022
VSS_701
VSS_702
VSS_703
VSS_704
VSS_705
VSS_706
VSS_707
VSS_708
VSS_736
VSS_737
VSS_738
VSS_800
VSS_801
VSS_802
VSS_803
VSS_804
VSS_805
VSS_806
VSS_807
VSS_711
VSS_712
VSS_713
VSS_714
VSS_715
VSS_716
VSS_717
VSS_718
VSS_719
VSS_720
VSS_721
VSS_722
VSS_723
VSS_724
VSS_725
VSS_726
VSS_727
VSS_728
VSS_729
VSS_730
VSS_731
VSS_733
VSS_734
VSS_735
VSS_732
VSS_850
VSS_851
VSS_852
VSS_853
VSS_854
VSS_751
VSS_750
VSS_749
VSS_748
VSS_747
VSS_746
VSS_745
VSS_744
VSS_743
VSS_742
VSS_741
VSS_740
VSS_739
VSS_700
VSS_855
VSS_856
VSS_857
VSS_858
VSS_859
VSS_860
VSS_861
VSS_862
VSS_863
VSS_864
VSS_865
VSS_866
VSS_867
VSS_868
VSS_869
VSS_870
VSS_871
VSS_872
VSS_873
VSS_874
VSS_875
VSS_876
VSS_877
VSS_878
VSS_879
VSS_880
VSS_883
VSS_1024
VSS_1021
VSS_1020

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_83
VSS_82
VSS_81
VSS_80
VSS_79
VSS_78
VSS_420
VSS_421
VSS_422
VSS_423
VSS_424
VSS_425
VSS_426
VSS_427
VSS_521
VSS_520
VSS_523
VSS_519
VSS_518
VSS_517
VSS_516
VSS_515
VSS_514
VSS_416
VSS_417
VSS_418
VSS_419
VSS_414
VSS_415
VSS_513
VSS_512

POULSBO_FCBGA1249

BH36
V38
V36
V14
U39
U35
U33
U31
U29
P48
P46
P44
J17
J13
J7
J5
J3
H46
H44
G49
U23
U21
U19
U17
U15
U11
U9
U7
U5
U3
T46
T44
T42
T40
T36
T14
R49
R47
R37
R35
R11
R7
R5
R3
R9
E19
E17
E11
E9
E7
N11
N39
P14
P16
P18
P20
P22
P24
P26
P28
P30
P40
P42
V40
E5
E3
E1
D50
D48
C45
C43
C41
C39
C37
C35
C33
C31
C29
C27
C25
C23
C21
C11
C9
C7
C5
C3
C1
B50
B48
A47
BH32
BH38
BH40

BH30
BH28
BH26
BH24
BH22
BH20
BH18
BH16
BH14
BH12
BH2
BG9
BG7
BG5
BG3
BG1
BF50
BF48
BF46
BF44
BF42
BF40
BF38
BF36
BF34
BF32
BF30
BF28
BF26
BF24
BF22
BF20
BF18
BF16
BF14
BF12
BE9
BE7
BE5
BE3
BD48
BD46
BD44
BD42
BD40
BD38
BD36
BD34
BD32
BD30
BD28
BD26
BD24
BD22
BD20
BD18
BD16
BD14
BD12
BC49
BC9
BC7
BC5
BC3
BB46
BB44
BB42
BB40
BB38
BB36
BB34
BB32
BB30
BB28
BB26
BA9
BB12
BB14
BB16
BB18
BB20
AM44
AM42
AM40
AM38
AM14
AM10
AL49
AL47
AL41
AL39
AL35
AL33
AL31
AL29
AL27
AL25
AL23
AL21
AL19
AL17
AL15
AL11
AL9
AK46
AL3

POULSBO_FCBGA1249

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Poulsbo(5/5)-GND

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Saturday, December 06, 2008

Sheet
1

10

of

20

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

6,12 M_CLK_DDR#0
6,12 M_CLK_DDR0
6 M_CKE0

6,12 DDR_A_WE#
6,12 DDR_A_RAS#
6,12 DDR_A_CAS#

M_CLK_DDR#0
M_CLK_DDR0

K8
J8

CK
CK

M_CKE0

K2

CKE

L8

DDR_A_WE#

K3

DDR_A_RAS#

K7

DDR_A_CAS#

L7
F3
B3

M_ODT

12 M_ODT

+VRAM_VREFA

R92

1K_0402_1%

0.1U_0402_16V4Z 1K_0402_1%
1
2

+1.8V

DDR_A_DQS0

DDR_A_DQS1

R91

BA0
BA1
A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CS#0

6 M_CS#0

L2
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

(SSTL-1.8) VREF = .5*VDDQ

C76
DDR_A_BS#2

Close to U7 DDR_A_MA13

K9
F7
E8

B7
A8

CS
WE
RAS
CAS
LDM
UDM

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

DDR_A_D11
DDR_A_D8
DDR_A_D13
DDR_A_D14
DDR_A_D9
DDR_A_D12
DDR_A_D15
DDR_A_D10
DDR_A_D5
DDR_A_D6
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D0
DDR_A_D2
DDR_A_D1

DDR_A_BS#0
DDR_A_BS#1

Group1

Group0

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CLK_DDR#0
M_CLK_DDR0

K8
J8

CK
CK

K2

CKE

M_CS#0

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

L8

DDR_A_WE#

K3

DDR_A_RAS#

K7

DDR_A_CAS#

L7
F3
B3

J1
J7

M_ODT
DDR_A_DQS2

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

M_CKE0

A1
E1
J9
M9
R1

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

L2
L3

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

ODT
LDQS
LDQS

U6

DDR_A_DQS3

(SSTL-1.8) VREF = .5*VDDQ

+VRAM_VREFA
C77

DDR_A_BS#2
DDR_A_MA13

Close to U7

HY5PS1G1631CFP-S6 _FBGA84
1GB@

K9
F7
E8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

+1.8V

0.1U_0402_16V4Z

DDR_A_BS#0
DDR_A_BS#1

U8

CS
WE
RAS

VDD1
VDD2
VDD3
VDD4
VDD5

CAS
LDM
UDM

VDDL
VSSDL

DDR_A_D26
DDR_A_D31
DDR_A_D24
DDR_A_D27
DDR_A_D25
DDR_A_D28
DDR_A_D30
DDR_A_D29
DDR_A_D20
DDR_A_D23
DDR_A_D17
DDR_A_D21
DDR_A_D19
DDR_A_D16
DDR_A_D22
DDR_A_D18

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

DDR_A_BS#0
DDR_A_BS#1

Group3

L2
L3

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

Group2

6,12 M_CLK_DDR#1
6,12 M_CLK_DDR1

A1
E1
J9
M9
R1

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CLK_DDR#1
M_CLK_DDR1

K8
J8

CK
CK

M_CKE0

K2

CKE

M_CS#0

L8

DDR_A_WE#

K3

DDR_A_RAS#

K7

DDR_A_CAS#

L7
F3
B3

J1
J7

M_ODT

ODT

K9

DDR_A_DQS5

LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

+1.8V

F7
E8

DDR_A_DQS4

+VRAM_VREFA

(SSTL-1.8) VREF = .5*VDDQ

C78

0.1U_0402_16V4Z

U5

DDR_A_BS#2

Close to U7 DDR_A_MA13

HY5PS1G1631CFP-S6 _FBGA84
1GB@

CS
WE
RAS

VDD1
VDD2
VDD3
VDD4
VDD5

CAS
LDM
UDM

DDR_A_D34
DDR_A_D38
DDR_A_D32
DDR_A_D39
DDR_A_D36
DDR_A_D35
DDR_A_D37
DDR_A_D33
DDR_A_D47
DDR_A_D40
DDR_A_D46
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D45
DDR_A_D44

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

Group4

Group5
D

+1.8V

A1
E1
J9
M9
R1

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

ODT
LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

HY5PS1G1631CFP-S6 _FBGA84
1GB@

U11

M_CLK_DDR#1
M_CLK_DDR1

K8
J8

M_CKE0

K2

M_CS#0

L8

CS

DDR_A_WE#

K3

WE

DDR_A_RAS#

K7

RAS

DDR_A_CAS#

L7
F3
B3

DDR_A_DQS6

DDR_A_DQS7
+VRAM_VREFA
A

(SSTL-1.8) VREF = .5*VDDQ

C95
DDR_A_BS#2

Close to U7 DDR_A_MA13

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

DDR_A_D61
DDR_A_D62
DDR_A_D57
DDR_A_D63
DDR_A_D58
DDR_A_D56
DDR_A_D59
DDR_A_D60
DDR_A_D55
DDR_A_D51
DDR_A_D50
DDR_A_D52
DDR_A_D48
DDR_A_D53
DDR_A_D49
DDR_A_D54

Group7

+1.8V

6,12 DDR_A_D[0..63]

K9

CK
CK
CKE

CAS
LDM
UDM

VDDL
VSSDL

LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10
VSS1
VSS2
VSS3
VSS4
VSS5

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C84
C85
C86

C83

6,12 DDR_A_MA[0..13]
2
2
0.01U_0402_16V7K

Group6

2
1U_0402_6.3V6K

2
2
0.01U_0402_16V7K

2
1U_0402_6.3V6K

M_ODT
+1.8V

R93
10K_0402_5%

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C88
C89
C90

C87

2
2
0.01U_0402_16V7K

+1.8V

2
1U_0402_6.3V6K

M_CLK_DDR0
+1.8V

J1
J7

1
R94
100_0402_1%

ODT

F7
E8

+1.8V

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C79
C80
C81
C82

6,12 DDR_A_DQS[0..7]

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C92
C93
C94

C91

2
2
0.01U_0402_16V7K

2
1U_0402_6.3V6K

M_CLK_DDR#0

A3
E3
J3
N1
P9

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HY5PS1G1631CFP-S6 _FBGA84
1GB@
5

6,12 DDR_A_BS#[0..2]

M_ODT

0.1U_0402_16V4Z

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

BA0
BA1

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

L2
L3

DDR_A_BS#0
DDR_A_BS#1

Title

Compal Electronics, Inc.


DDRII-DEVICE DOWN(1/2)

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
1

11

of

20

U12
DDR_A_BS#0
DDR_A_BS#1
DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

6,11 M_CLK_DDR#0
6,11 M_CLK_DDR0
6 M_CKE1

6 M_CS#1
6,11 DDR_A_WE#
6,11 DDR_A_RAS#
6,11 DDR_A_CAS#

L2
L3
R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8
K8
J8

CK
CK

M_CKE1

K2

CKE

M_CS#1

L8

CS

DDR_A_WE#

K3

DDR_A_RAS#

K7

RAS

DDR_A_CAS#

L7

CAS

M_ODT
DDR_A_DQS0

DDR_A_DQS1

+VRAM_VREFA

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CLK_DDR#0
M_CLK_DDR0

F3
B3

11 M_ODT

BA0
BA1

(SSTL-1.8) VREF = .5*VDDQ

DDR_A_BS#2
DDR_A_MA13

K9
F7
E8

WE

LDM
UDM

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

DDR_A_D8
DDR_A_D11
DDR_A_D14
DDR_A_D13
DDR_A_D12
DDR_A_D9
DDR_A_D10
DDR_A_D15
DDR_A_D6
DDR_A_D5
DDR_A_D3
DDR_A_D4
DDR_A_D0
DDR_A_D7
DDR_A_D1
DDR_A_D2

DDR_A_BS#0
DDR_A_BS#1

Group1

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

L2
L3

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

Group0

M_CLK_DDR#0
M_CLK_DDR0

VSS1
VSS2
VSS3
VSS4
VSS5

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

K8
J8

CK
CK

M_CKE1

K2

CKE

M_CS#1

L8

CS

DDR_A_WE#

K3

DDR_A_RAS#

K7

RAS

DDR_A_CAS#

L7

CAS

F3
B3

J1
J7

M_ODT
DDR_A_DQS2

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

U14

BA0
BA1

+1.8V

ODT

B7
A8

U13
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VDDL
VSSDL

LDQS
LDQS

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

DDR_A_DQS3

+VRAM_VREFA

A3
E3
J3
N1
P9

(SSTL-1.8) VREF = .5*VDDQ

DDR_A_BS#2
DDR_A_MA13

HY5PS1G1631CFP-S6 _FBGA84
1GB@

K9
F7
E8

WE

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

LDM
UDM

VDDL
VSSDL

DDR_A_D31
DDR_A_D26
DDR_A_D27
DDR_A_D24
DDR_A_D28
DDR_A_D25
DDR_A_D29
DDR_A_D30
DDR_A_D23
DDR_A_D20
DDR_A_D21
DDR_A_D17
DDR_A_D16
DDR_A_D19
DDR_A_D18
DDR_A_D22

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

DDR_A_BS#0
DDR_A_BS#1

Group3

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

Group2

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CLK_DDR#1
M_CLK_DDR1

K8
J8

CK
CK

M_CKE1

K2

CKE

M_CS#1

L8

CS

DDR_A_WE#

K3

DDR_A_RAS#

K7

RAS

DDR_A_CAS#

L7

CAS

F3
B3

J1
J7

M_ODT

K9

DDR_A_DQS5
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

BA0
BA1

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

+1.8V

ODT
LDQS
LDQS

L2
L3

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

F7
E8

DDR_A_DQS4

+VRAM_VREFA

(SSTL-1.8) VREF = .5*VDDQ

A3
E3
J3
N1
P9

DDR_A_BS#2
DDR_A_MA13

HY5PS1G1631CFP-S6 _FBGA84
1GB@

WE

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

VDD1
VDD2
VDD3
VDD4
VDD5

A1
E1
J9
M9
R1

LDM
UDM

DDR_A_D38
DDR_A_D34
DDR_A_D39
DDR_A_D32
DDR_A_D35
DDR_A_D36
DDR_A_D33
DDR_A_D37
DDR_A_D40
DDR_A_D47
DDR_A_D41
DDR_A_D46
DDR_A_D43
DDR_A_D42
DDR_A_D44
DDR_A_D45

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

VDDL
VSSDL

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

Group4

Group5
D

+1.8V

ODT
LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VREF

A2
E2
L1
R3
R7
R8

NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

VSS1
VSS2
VSS3
VSS4
VSS5

A3
E3
J3
N1
P9

HY5PS1G1631CFP-S6 _FBGA84
1GB@

U18

6,11 M_CLK_DDR#1
6,11 M_CLK_DDR1

BA0
BA1

R2
P7
M2
P3
P8
P2
N7
N3
N8
N2
M7
M3
M8

A12
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

M_CLK_DDR#1
M_CLK_DDR1

K8
J8

M_CKE1

K2

M_CS#1

L8

DDR_A_WE#

K3

DDR_A_RAS#

K7

DDR_A_CAS#

L7
F3
B3

M_ODT
DDR_A_DQS6

DDR_A_DQS7
A

+VRAM_VREFA

(SSTL-1.8) VREF = .5*VDDQ

0.1U_0402_16V4Z

C115
DDR_A_BS#2

2
DDR_A_MA13

CK
CK
CKE

CS
WE
RAS
CAS
LDM
UDM
ODT

F7
E8

LDQS
LDQS

B7
A8

UDQS
UDQS

J2

VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDD1
VDD2
VDD3
VDD4
VDD5
VDDL
VSSDL

K9

A2
E2
L1
R3
R7
R8

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

VREF
NC#A2
NC#E2
NC#L1
NC#R3
NC#R7
NC#R8

B9
B1
D9
D1
D3
D7
C2
C8
F9
F1
H9
H1
H3
H7
G2
G8

DDR_A_D62
DDR_A_D61
DDR_A_D63
DDR_A_D57
DDR_A_D56
DDR_A_D58
DDR_A_D60
DDR_A_D59
DDR_A_D51
DDR_A_D55
DDR_A_D52
DDR_A_D50
DDR_A_D53
DDR_A_D48
DDR_A_D54
DDR_A_D49

Group6

A9
C1
C3
C7
C9
E9
G1
G3
G7
G9

DDR_A_BS#0
DDR_A_BS#1
DDR_A_BS#2

R97
R98
R99

2
2
2

1 121_0402_1%
1 121_0402_1%
1 121_0402_1%

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

R100
R101
R102
R103
R104
R105
R106
R107
R108
R109
R110
R111
R112
R114

2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
1
1
1
1
1
1
1
1
1
1
1
1
1

121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%
121_0402_1%

+1.8V

+1.8V

+1.8V

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
1
C101
C102
C103
C104
2
2
0.01U_0402_16V7K

A1
E1
J9
M9
R1

A3
E3
J3
N1
P9

2
1U_0402_6.3V6K

DDR_A_WE#
DDR_A_RAS#
DDR_A_CAS#

R119 2
R120 2
R121 2

1 121_0402_1%
1 121_0402_1%
1 121_0402_1%

M_CLK_DDR1

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C108
C109
C110

C107

2
2
0.01U_0402_16V7K

2
1U_0402_6.3V6K

R113
100_0402_1%

+1.8V
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C112
C113
C114

C111

2
2
0.01U_0402_16V7K

VSS1
VSS2
VSS3
VSS4
VSS5

2
2
0.01U_0402_16V7K

A7
B2
B8
D2
D8
E7
F2
F8
H2
H8

0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
1
C106
C99
C100

C105

+1.8V

J1
J7

VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
VSSQ9
VSSQ10

2
1U_0402_6.3V6K

M_CLK_DDR#1

2
1U_0402_6.3V6K

6,11 DDR_A_BS#[0..2]
6,11 DDR_A_D[0..63]

6,11 DDR_A_DQS[0..7]
6,11 DDR_A_MA[0..13]

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

HY5PS1G1631CFP-S6 _FBGA84
1GB@
5

+0.9VS

Group7

DDR_A_MA12
DDR_A_MA11
DDR_A_MA10
DDR_A_MA9
DDR_A_MA8
DDR_A_MA7
DDR_A_MA6
DDR_A_MA5
DDR_A_MA4
DDR_A_MA3
DDR_A_MA2
DDR_A_MA1
DDR_A_MA0

L2
L3

DDR_A_BS#0
DDR_A_BS#1

Title

Compal Electronics, Inc.


DDRII-DEVICE DOWN(2/2)

Size

Document Number

Rev
1.0

KIU10 LS-4764P
Date:

Tuesday, December 02, 2008

Sheet
1

12

of

20

DDDR2-GOLD FINGER
200
198
196
194
192
190
188
186
184
182
180
178
176
174
172
170
168
166
164
162
160
158
156
154
152
150
148
146
144
142
140
138
136
134
132
130
128
126
124
122
120
118
116
114
112
110
108
106
104
102
100
98
96
94
92
90
88
86
84
82
80
78
76
74
72
70
68
66
64
62
60
58
56
54
52
50
48
46
44
42

7 SDVO_CTRLCLK
7 SDVO_CTRLDATA
1
1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

SDVO_CLK#_C
SDVO_CLK_C

7 SDVO_BLUE#
7 SDVO_BLUE

C44 1
C116 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

SDVO_BLUE#_C
SDVO_BLUE_C

7 SDVO_GREEN#
7 SDVO_GREEN

C119 1
C120 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

SDVO_GREEN#_C
SDVO_GREEN_C

7 SDVO_RED#
7 SDVO_RED

C117 1
C118 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

SDVO_RED#_C
SDVO_RED_C

C42
C43

7 SDVO_CLK#
7 SDVO_CLK
D

1
J2

JUMP_43X39
2 2
2

JUMP_43X39

R181

0_0402_5%
2
1

7 SDVO_INT

0_0402_5%
2
1

J1
1

7 SDVO_INT#

8 USB20_N7
8 USB20_P7

R182

R181,R182 Close to JP12

8 USB20_N0
8 USB20_P0
8 USB20_N1
8 USB20_P1

8 USB20_N2
8 USB20_P2
8 USB20_N6
8 USB20_P6
14 CLK_14M_SIO
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

PD_D7
PD_D8
PD_D6
PD_D9
PD_D5
PD_D10
PD_D4
PD_D11
PD_D3
PD_D12
PD_D2
PD_D13
PD_D1
PD_D14
PD_D0
PD_D15
PD_DREQ
PD_IOW#
PD_IOR#
PD_IORDY
PD_DACK#
PD_IRQ
PD_A1
PD_A0
PD_A2
PD_CS#3
PD_CS#1

7 MINSD_CLK

7
7
7
7
7
7
7
7

MINSD_DATA3
MINSD_DATA2
MINSD_DATA1
MINSD_DATA0
MINSD_CMD
MINSD_CD#
MINSD_WP
MINSD_PWR#

4,6
4
4
4
4,7,8
8
8
8

H_INIT#
H_A20M#
EC_SMB_CK2
EC_SMB_DA2
EC_THERM#
EC_LID_OUT#
PLT_RST#
BT_DET#

40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2

+VL
+1.5VS

+RTCVCC
+3VALW
+3VS

+5VALW
+5VS
A

SA1
SAO
VSS
DQ63
DQ62
VSS
DQS7
DQS7#
VSS
DQ61
DQ60
VSS
DQ55
DQ54
VSS
DM6
VSS
CK1#
CK1
VSS
DQ53
DQ52
VSS
DQ47
DQ46
VSS
DQS5
DQS5#
VSS
DQ45
DQ44
VSS
DQ39
DQ38
VSS
DM4
VSS
DQ37
DQ36
VSS
NC
VDD
NC/A13
ODT0
VDD
S0#
RAS#
BA1
VDD
A0
A2
A4
VDD
A6
A7
A11
VDD
NC/A14
NC/A15
VDD
NC/CKE1
VSS
DQ31
DQ30
VSS
DQS3
DQS3#
VSS
DQ29
DQ28
VSS
DQ23
DQ22
VSS
DM2
NC
VSS
DQ21
DQ20
VSS
VSS
DQ15
DQ14
VSS
CK0#
CK0
VSS
DM1
VSS
DQ13
DQ12
VSS
DQ7
DQ6
VSS
DM0
VSS
DQ5
DQ4
VSS

VDDSPD
SCL
SDA
VSS
DQ59
DQ58
VSS
DM7
VSS
DQ57
DQ56
VSS
DQ51
DQ50
VSS
DQS6
DQS6#
VSS
NC,TEST
VSS
DQ49
DQ48
VSS
DQ43
DQ42
VSS
DM5
VSS
DQ41
DQ40
VSS
DQ35
DQ34
VSS
DQS4
DQS4#
VSS
DQ33
DQ32
VSS
NC/ODT1
VDD
NC/S1#
CAS#
VDD
WE#
BA0
A10/AP
VDD
A1
A3
A5
VDD
A8
A9
A12
VDD
BA2
NC
VDD
CKE0
VSS
DQ27
DQ26
VSS
NC
DM3
VSS
DQ25
DQ24
VSS
DQ19
DQ18
VSS
DQS2
DQS2#
VSS
DQ17
DQ16
VSS
VSS
DQ11
DQ10
VSS
DQS1
DQS1#
VSS
DQ9
DQ8
VSS
DQ3
DQ2
VSS
DQS0
DQS0#
VSS
DQ1
DQ0
VSS
VREF

J3
199
197
195
193
191
189
187
185
183
181
179
177
175
173
171
169
167
165
163
161
159
157
155
153
151
149
147
145
143
141
139
137
135
133
131
129
127
125
123
121
119
117
115
113
111
109
107
105
103
101
99
97
95
93
91
89
87
85
83
81
79
77
75
73
71
69
67
65
63
61
59
57
55
53
51
49
47
45
43
41

JUMP_43X39
2 2

SPKR

CLK_PCIE_WLAN# 14
CLK_PCIE_WLAN 14
PCIE_WLANTX_IRX_C_N2 7
PCIE_WLANTX_IRX_C_P2 7

PCIE_ITX_C_WLANRX_N2 7
PCIE_ITX_C_WLANRX_P2 7
CLK_PCIE_LAN 14
CLK_PCIE_LAN# 14
PCIE_PTX_C_IRX_P1 7
PCIE_PTX_C_IRX_N1 7
PCIE_ITX_C_PRX_P1 7
PCIE_ITX_C_PRX_N1 7
GMCH_LVDDEN 7
EDID_DAT_LCD 7
EDID_CLK_LCD 7
LVDSA0- 7
LVDSA0+ 7
LVDSA1- 7
LVDSA1+ 7
LVDSA2- 7
LVDSA2+ 7
LVDSAC- 7
LVDSAC+ 7
USB20_N4 8
USB20_P4 8
C

USB20_N3 8
USB20_P3 8
USB20_N5 8
USB20_P5 8
CLK_PCI_LPC 7
SIRQ
7
LPC_FRAME# 7
LPC_AD3 7
LPC_AD2 7
LPC_AD1 7
LPC_AD0 7
EC_SCI# 8
PM_SLPRDY# 7
PM_SLPMODE 7
EC_SMI# 8
SUSP
17
PBTN_OUT# 8
PM_RSTWARN 8
EC_RSMRST# 7
ICH_POK 7
PM_RSTRDY# 8
ENBKL
7
SB_INT_FLASH_SEL 8
ICH_RTCRST# 7
CK_PWRGD 14
PM_EN_1.5_1.05 16,17
PM_1.05_PWRGD 16,18
SYSON
16
VR_ON
18
PM_1.8V_PWRGD 16
VGATE
18

HDA_BITCLK_AUDIO 8
HDA_RST_AUDIO# 8
HDA_SDOUT_AUDIO 8
HDA_SYNC_AUDIO 8
HDA_SDIN0 8

39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1

CPU_TMP_SENSE 18
HDA_SDIN1 8

+1.8V

B+

JP12

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


LVDS/FUN_B/PWR_B/USB_B CONN

Size Document Number


Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
1

13

of

20

+3VS_+1.5VS_CK505

L5
+3VS

+3VS_CK505

R95
1

+1.5VS

2
1
0_0402_5%
2

2
FBMA-L11-160808-121LMT_0603
L4

C129

+3VS

0.1U_0402_16V4Z

1
2
@ FBMA-L11-160808-121LMT_0603
1
C124
10U_0603_6.3V6M

C125
0.1U_0402_16V4Z

C126
0.1U_0402_16V4Z

C127
0.1U_0402_16V4Z

C128
0.1U_0402_16V4Z

+3VS_+1.5VS_CK505

+1.5VS +3VS_CK505
U19
5
8
14
15
22
23
29
30
41
42
46

VDDREF_3.3
VDDCORE_1.5
VDDCORE_1.5
VDDIO_1.5
VDDIO_1.5
VDDCORE_1.5
VDDCORE_1.5
VDDIO_1.5
VDDIO_1.5
VDDCORE_1.5
VDDIO_1.5

SCLK_3.3
SDATA_3.3
CPU_STOP#
CPUC0_LPR

CPUT0_LPR

C132
2

SMB_CLK

13

SMB_DAT

SMB_CLK 8
SMB_DAT 8

H_STP_CPU# 8

47

CLK_CPU_BCLK#

48

CLK_CPU_BCLK

43

CLK_MCH_BCLK#

44

CLK_MCH_BCLK

CLK_CPU_BCLK# 4
CLK_CPU_BCLK 4

C133
0.1U_0402_16V7K

0.1U_0402_16V7K

1
C131

0.1U_0402_16V7K

1
C130

0.1U_0402_16V7K

12

CPUC1_LPR
CPUT1_LPR
CPUC2_LPR

CPUT2_LPR

CLK_MCH_BCLK# 6
CLK_MCH_BCLK 6

38
T2

TPC24

T3

TPC24

39

11/07:change C134, C135 from 22P to 15P

4,6

2
15P_0402_50V8J

1
2
15P_0402_50V8J

FSB_L

FSC_L

4
Y1
14.318MHZ_16PF_7A14300083

1
C135

37

*CR#0
*CR#1
*CR#2

X1
X2
SRCC2_LPR

CLK_XTAL_OUT

SRCT2_LPR

SRCC1_LPR
R133 1

2 10K_0402_5%

10

R134 1

2 10K_0402_5%

11

SRCT1_LPR

CLK_14M_SCH

13 CLK_14M_SIO

33_0402_5% 1

2 R128

22_0402_5% 1

2 R130

CLK_REF

34

CLK_PCIE_LAN# 13

35

CLK_PCIE_LAN 13

31

CLK_PCIE_WLAN# 13

32

CLK_PCIE_WLAN 13

26

CLK_PCIE_ICH#

27

CLK_PCIE_ICH

20

MCH_SSCDREFCLK#

21

MCH_SSCDREFCLK

16

CLK_MCH_DREFCLK#

17

CLK_MCH_DREFCLK

TEST_MODE
TEST_SEL
SRCC0_LPR

24
28
36

CLK_XTAL_IN
2

1
C134

CPU_BSEL2

SRCT0_LPR

REF

GNDREF

18

GNDDOT

LCD100C_LPR

GNDLCD

LCD100T_LPR

7
7

25
33
40
45
49

GNDSRC
DOT96C_LPR
GNDSRC
DOT96T_LPR
GNDCPU

1
R129

GNDCPU
THERMAL_PAD

CLKPWRGD/PD#

2
10K_0402_5%

8
8
8
8

+3VS

CLK_ENABLE# 18

2
1

19

ICS9UMS9610BKLF-T_MLF48_6X6
Q4
2N7002_SOT23-3

2
G

CK_PWRGD 13

Compal Secret Data

Security Classification
2008/07/15

Issued Date

2011/07/15

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


Clock Generator CK540

Size

Document Number

Rev
1.0

KIU10 LS-4764P
Date:

Tuesday, December 02, 2008

Sheet
1

14

of

20

+1.05VS_C6
+1.05VS
SI7326DN-T1-E3_PAK1212-8
1
2
3

R172
5

PJ7
2

+0.9VS

+1.5VSP

JUMP_43X79
@

U26

H1

+1.5VS

JUMP_43X79
@

H2

2
1K_0402_5%

H_3P5x4P7
@

H_3P5x4P7
@

74AHCT1G08GW_SOT353-5

PJ6
1

+1.05VSP
C171
0.047U_0402_16V4Z

PJ1
1

+1.05VS

@ JUMP_43X118

+1.8VP

FD1

+1.8V

@ JUMP_43X118

FD2
@

FD3
@

FD4
@
1

1
R173

Y
3

SLPIOVR#

4,8

SLPIOVR#

10K_0402_5%

PJ5

+0.9VSP

Q13
+5VS

+3VS

Compal Secret Data

Security Classification

Issued Date

2008/07/15

Deciphered Date

2011/07/15

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Electronics, Inc.

DC/DC Circuit
Size Document Number
Custom KIU10 LS-4764P
Date:

Tuesday, December 09, 2008

Rev
1.0
Sheet

15

of

20

PJ10

14
TRIP

VFB

V5DRV

11
10

2
PR90
10K_0402_1%

DL_1.8V

PQ21
AO4712_SO8

4
1

DRVL

+5VALW

PC74
4.7U_0805_10V6K

TPS51117RGYR_QFN14_3.5x3.5

+1.8VP

Iocp=7.9A

1
2

LX_1.8V

12

PGND

PGOOD

PC73
@ 47P_0402_50V8J
1
2

GND

6
PC76
1U_0603_10V6K

15

VBST

TP

LL

V5FILT

VOUT

0.1U_0603_25V7K

DH_1.8V

13

BST_1.8V-1
DRVH

5
6
7
8

PR89
422_0603_1%
1
2

TON

+1.8VP
Imax=4.19

PL7
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

PC69

3
2
1

+5VALW

EN_PSV

PU6

B+

PR87
0_0603_1%
BST_1.8V 1
2

PC71
@ 0.1U_0402_16V7K

3
2
1

PR86
0_0402_5%
1
2

SYSON

PQ20
AO4466_SO8

PR85
300K_0402_5%
1
2

13

@ JUMP_43X79

1
+ PC70
220U_D2E_4VM_R15M
2

PR91
28.7K_0402_1%
1
2

PC72
PR88
680P_0603_50V7K @ 4.7_1206_5%

13 PM_1.8V_PWRGD

2
PC75
4.7U_0805_25V6-K

5
6
7
8

+3VALW

PR142
100K_0402_1%
1
2

PC68
4.7U_0805_25V6-K

1.8V_B+

PR92
20.5K_0402_1%

PJ11

V5DRV

11
10

DRVL

2
PR98
11K_0402_1%

DL_1.05V

1
2

B+

+1.05VSP
Imax=5.039A
Iocp=8.2A

+5VALW

PQ23
AO4712_SO8

TPS51117RGYR_QFN14_3.5x3.5

+1.05VSP

0.1U_0603_25V7K

PGND
8

GND

PC82
@ 47P_0402_50V8J
1
2

PGOOD

PC85
1U_0603_10V6K

PC84
4.7U_0805_25V6-K

2
VFB

LX_1.05V

TRIP

DH_1.05V

12

5
6
7
8

LL

V5FILT

3
2
1

14

15

VOUT

13

DRVH

TON

BST_1.05V-1

+5VALW

PL8
2.2UH_PCMC063T-2R2MN_8A_20%
1
2

PC78

VBST

2
PR97
422_0603_1%
1
2

TP

PU7

EN_PSV

PC80
@ 0.1U_0402_16V7K

@ JUMP_43X79

PR95
0_0603_1%
BST_1.05V 1
2
1

13,17 PM_EN_1.5_1.05

PR94
0_0402_5%
1
2

PQ22
AO4466_SO8

PR93
300K_0402_5%
1
2

PC83
4.7U_0805_10V6K

1
+ PC79
220U_D2E_4VM_R15M
2

PR99
9.53K_0402_1%
1
2

PC81
PR96
680P_0603_50V7K @ 4.7_1206_5%

13,18 PM_1.05_PWRGD

3
2
1

+3VALW

5
6
7
8

PR143
100K_0402_1%
1
2

PC77
4.7U_0805_25V6-K

1.05V_B+

PR100
20.5K_0402_1%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/07/15

Deciphered Date

2011/07/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+1.05VSP / +1.8VP
Size
C
Date:

Document Number

Rev
1.0

KIU10 LS-4764P
Tuesday, December 02, 2008
D

Sheet

16

of

20

+1.8VP

+1.5VSP
Imax=1.52A

PC86
1U_0603_6.3V6M

PC89
4.7U_0805_6.3V6K

PJ12
@ JUMP_43X79

+5VALW

PU8
VCNTL
VIN
VIN

3
4

+1.5VSP
1

VOUT
VOUT

PC87
0.01U_0402_25V7K

APL5913-KAC-TRL_SO8

PC90
22U_0805_6.3V6M

PC88
@ 0.1U_0402_16V7K

PR102
2.15K_0402_1%

FB

GND

EN
POK

8
7
1

13,16 PM_EN_1.5_1.05

6
5
9

PR101
0_0402_5%
1
2

PR103
2.43K_0402_1%

PJ13
@ JUMP_43X79

+0.9VSP
Imax=0.19A

+1.8VP

VCNTL

GND

NC

VREF

NC

VOUT

NC

6
5

2
3

7
2

PR104
1K_0402_1%

4
2

PC93
4.7U_0805_6.3V6K

VIN

TP

+3VALW
1

PU9

PC91
1U_0603_6.3V6M

8
9

PR106
1K_0402_1%
S PQ24
SSM3K7002FU_SC70-3

+0.9VSP
1

1
3
2

PC95
@ 0.1U_0402_16V7K

2
G

PC94
0.1U_0402_16V7K
2
1

SUSP

13

APL5331KAC-TRL_SO8
PR105
0_0402_5%
1
2

PC92
10U_0805_6.3V6M

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/07/15

Deciphered Date

2011/07/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

1.5V/0.9VSP
Document Number

Rev
1.0

KIU10 LS-4764P
Tuesday, December 02, 2008
1

Sheet

17

of

20

+5VS

2
1

+CPU_B+
2

PC96
1U_0402_6.3V6K

+CPU_CORE
Imax=3A
Iocp=7A

PR144
10_0402_1%

17

1 0_0402_5%

18

PR151

1 0_0402_5%

19

PR154

1 0_0402_5%

20

D2

PR149
121K_0402_1%
1
2

CPU_VID4

CPU_VID5

CPU_VID6

+CPU_B+

D4
D5

BST

24

BOOT_CPU

PR152
2.2_0603_1%

D6

11

PR155
0_0402_5%

PC101
0.1U_0603_25V7K

DPRSLPVR

4,6 H_DPRSTP#

PR156

1 0_0402_5%

PR157

1 0_0402_5%

PR158

13,16 PM_1.05_PWRGD

PR161
61.9K_0402_1%
1
2

+3VS

1 0_0402_5%

27

PR162
12.7K_0402_1%
1
2

SHDN
DH
DPRSLPVR

29
30
13

LX

TIME
ILIM
V3P3

DL

LX_CPU

25

DL_CPU

22

PQ26
AO4466_SO8

+CPU_COREP
PJ14
2

+CPU_CORE

@ JUMP_43X118
PR160
5.1K_0402_1%

PR163
1.65K_0402_1%
1
2

PC102
680P_0603_50V8J

3
2
1
21
2

PC103
0.1U_0402_16V7K

4
2

CSN

5
MAX8796_CSP

PWRGD

28

VRHOT

12

PR170
0_0402_5%

1
PR173
13K_0402_1%
1
2

PC104
47P_0402_50V8J

CLKEN
FB

PC105
1000P_0402_50V7K

PR171
1.69K_0402_1%

33

GNDS

2
PR169
10_0402_1%
3

THRM

PR172
10_0402_1%
1
2

PWR

PAD

+5VS

32

CSP

CCV
1

VCCSENSE

VSSSENSE

14 CLK_ENABLE#

VGATE

PGND

10

2
1

PROCHOT#

13

PR167
0_0402_5%
1
2

1
4,8

PR168
@ 0_0402_5%
1
2

PR164
10K_0402_1%
PR166
@ 2K_0402_1%

PR159
4.7_1206_5%

+3VS

PR165
@ 56_0402_5%

PL10
2.2UH_MPLC0730L2R2_7.3A_20%
1
2

DPRSLP
PGD_IN

B+

PQ25
AO4466_SO8

DH_CPU

26

3
2
1

VR_ON

5
6
7
8

13

TON

PR153
@ 10K_0402_1%

D3

1 0_0402_5%

31

PR150

VCC

PC100
4.7U_0805_25V6-K

PR148

D1

16

15

1 0_0402_5%

PL9
HCB2012KF-121T50_0805
1
2
PC99
4.7U_0805_25V6-K

1 0_0402_5%

23

PR147

VDD

CPU_VID3

PR146

D0

CPU_VID2

14

1 0_0402_5%

CPU_VID1

5
6
7
8

PR145

CPU_VID0

PC97
1U_0402_6.3V6K
PC98
0.01U_0402_25V_X7R

PU10

PC106
1000P_0402_50V7K

MAX8796GTJ+_TQFN32_5X5

PC107
1000P_0402_50V7K

PR175
10_0402_1%
1

PR174
10_0402_1%
1
2

+VL

PH1
100K_0603_1%_TH11-4H104FT
2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2008/07/15

Deciphered Date

2011/07/15

Title

CPU_CORE

13 CPU_TMP_SENSE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Size
C
Date:

Document Number

Rev
1.0

KIU10 LS-4764P
Tuesday, December 02, 2008
D

Sheet

18

of

20

KIU10 LS-4764P SCHMATIC CHANGE LIST


REVISION CHANGE :
0.1 TO 0.2
NO
DATE
PAGE
1
0907
13
2
0907
06
11/07
07
3
11/07
4
14

MODIFICATION
LIST
PURPOSE
Del J1,J2,J3 Bom structure
Default
add C172,C173
INTEL Suggestion for avoid ripple noise
Change C36, C37 from 10P to 15P
Change C134, C135 from 22P to 15P

2008/07/15

Issued Date

Deciphered Date

2011/07/15

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

PIR
Size Document Number
Custom KIU10 LS-4764P
Date:

Rev
1.0

Tuesday, December 02, 2008

Sheet
1

19

of

20

NO DATE
PAGE
MODIFICATION LIST
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------------------

9/24

16

Change PR99 from 8.2K to 9.53K ohm

3D mark burn-in BSOD issue

11/10

18

Stuff PR159 and PC102

WWAN noise solution from EMI team requirement

11/10

18

Change PC98 from 0.01U_0402_25V_X7R

Voltage rating can not meet application

Compal Secret Data

Security Classification

Issued Date

2005/06/01

Deciphered Date

2006/06/01

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


Power PIR

Size

Document Number

Rev
1.0

LA-3481P
Date:

Tuesday, December 02, 2008

Sheet

20

of

20

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