High-Speed Low-Power Viterbi Decoder Design for TCM Decoders

Abstract
High-speed, low-power design of Viterbi decoders for trellis coded modulation (TCM) systems is presented in this work. It is well known that the Viterbi decoder (VD) is the dominant module determining the overall power consumption of TCM decoders. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can effectively reduce the power consumption without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-3/4 convolutional code used in a TCM system shows that compared with the full trellis VD, the precomputation architecture reduces the power consumption by as much as high without performance loss, while the degradation in clock speed is negligible.

Aim
To design High-Speed Low-Power Viterbi Decoder using FPGA

Objective
The objectives of this works are, 1. Design of High-Speed Low-Power Viterbi Decoder using VHDL 2. Functional verification of High-Speed Low-Power Viterbi Decoder 3. Result analysis in terms of a. Area b. Power c. Speed

Tools to be used:
For functional simulation For synthesis and implementation Mentor Graphics ModelSim 6.5 or later Xilinx Incs Xilinx ISE 13.1or later version

For FPGA based implementation, the FPGA Details are,

Manufacturer Family FPGA Series Xilinx Spartan 3/Spartan 3E XC3S400PQ208/XC3S250EPQ208

For CPLD based implementation, the CPLD Details are,

Manufacturer Family CPLD Series Xilinx XC9500 XC9572-XL

HDL to be used:
VHDL/Verilog HDL

Project Report Details:

Soft copy of documents referred by our guide to do the project will be given to prepare the report.