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Comparator
The comparator is a circuit that compares an analog signal

with another analog signal or reference and outputs a binary signal based on comparison. The output of a comparator is a digital signal (1 or 0 level). The concept of binary signal is too ideal for real world situations, where there is a transition region between the two levels. It is important for the comparator to pass through this transition region quickly. The comparator is widely used in the process of converting analog signal to digital signal and in many other processes where signals are to be compared.
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Comparator
Vo 1 Vth 0 Vi

Vi Vth

Vo (Digital)

Transfer characteristic (ideal)

Circuit symbol

Detects the polarity of the analog input signal and produces a digital output (1 or 0) accordingly threshold-crossing detector

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Applications
Voltage/current level comparison (A/D conversion) Digital communication receivers (slicer or decision circuit)

Sense amplifier in memory readout circuits


Power electronics with digital control (dc-dc converter)

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Characteristics
Static characteristics:
Gain

VOH, VOL
Input Resolution Offset

Noise.

Dynamic characteristics:
Propagation delay Slew Rate
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Different Comparators Type


Open Loop Comparators: These are operational
amplifiers without compensation. Thus they have lesser gain and large bandwidth.

Regenerative Comparators: They use positive feedback


for comparison.

High-Speed Comparators: They are combination of the


above two and have faster response.

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Open Loop Comparators

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The comparator shown above is a two stage open loop comparator. It has two poles of interest, one is the output pole of first stage p1 and the second is the output pole of second stage, p2. These poles are expressed as

P1 =

P 2=

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Where C1 is the sum of capacitances connected to the output of first stage and C2is the sum of capacitances connected to the output of the second stage. The frequency response can be expressed as

AV =

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Linear Step response With Two Poles On Real Axis

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Comparators with Hysteresis


When in a comparator the input signal is near the threshold voltage and varies slowly with respect to the response time, noise can produce oscillations in the output.

The comparator has two fixed threshold levels and the output changes its state only when one of them is crossed. Thus in between there is no change in state. This way the output is unaffected by noise in the circuit.

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Comparator response to noisy input(a)without hysteresis (b)with hysteresis


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Fig 8.4-11 Hysteresis Comparator using internal positive feedback


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Latched Comparators
In latched comparators, comparison is performed at given

time instants (controlled by the Latch signal) and the result is maintained until the next comparison is performed Latched comparators are typically used in sampled-data systems (e.g. data converters), where the latch signal is the clock A latched comparator consists of a gain stage followed by a latch stage and eventually a set-reset flip-flop to hold the output signal while the latch is reset (Latch signal) The latch stage is based on a positive feedback loop Very fast response time
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df

(a) NMOS latch

(b)PMOS latch

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A simple low power latched comparator

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The input voltage Vin+

and Vin- determine current

in M3 and M4.
M9 and M10 are used to reset the latch by setting the source drain voltages of M7 and M8 to zero.
When the latch is enabled the drain of M3 and M4 are connected to the latch outputs. M3 and M4 form a parallel positive feedback path for the latch.

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High Speed Comparator


A high speed comparator must have a propagation dlay as low as possible.

It uses a pre-amplifier to build up the input change to a sufficiently large value and then applying it to the latch. This combines the best aspects of the with a negative exponential rise(pre-amplifier) and positive exponential rise(latch) ,as shown in the next figure.
The use of pre-amplifier also reduces the input offset voltage of the latch by its gain.
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Pre-amplifier and latch step response

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Fully differential three stage comparator and latch


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Example of pre-amplifier and latch


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References
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.

P. Allen and D. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002.

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