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Reg. No.

M.E. DEGREE EXAMINATION, NOVEMBER/DECEMBER 2010 First Semester Applied Electronics

AP 9212 ADVANCED DIGITAL SYSTEM DESIGN (Common to M.E. VLSI Design) (Regulation 2009) Time : Three hours Answer ALL questions

PART A (10 2 = 20 Marks)

2. 3. 4. 5. 6. 7. 8. 9. 10.

Define Class A, B, C, D, E MACHINES.

What is a Unit distance state assignment?

Name the Tolerance techniques. Define MTBF.

What is the difference between FPLA and PROM? Use 4 4 ROM to convert four bit BCD to an Excess -3 code. List the steps involved in VHDL test bench. What is the difference between Behavioral model and test bench?




Discuss using timing diagram, the operation of a binary cell developed around NOR gates. Draw a distinction between NAND and NOR cell. What should be the direct consequence of a SET OPERATION? Or

Write down the design steps involved in designing Traditional synchronous sequential circuits.

Give an example for non critical race.

PART B (5 16 = 80 Marks)


A controlled digital system, a sequential machine and a finite machine one These three are the same or different?

Maximum : 100 Marks

Question Paper Code : 97602




Design a single step pulse circuit whose inputs are system clock and single step. This circuit is to issue one and only one clean positive going clock pulse each time the single step input is cycled.



Or (b)

Prove that in a circuit in which all gates have a fan-out of 1, any set of tests that detects all single faults on the Input wires detects all single faults in the entire circuit. Using the direct addressed ROM or PLA configuration develop the ROM program table for the control logic of vending machine controller.






Write the behavioral model of a multiplier for unsigned binary numbers that multiplies a 4-bit multiplicand by a 4-bit multiplier to give an 68-bit product.


Write the VHDL code for a Dice game simulator.

Or 2

Consider the function f (x1 , x 2 , x 3 ) = x1 x 2 + x1 x 3 + x 2 x3 . Show a circuit using 5 two input look up tables (LUTs ) to implement this expression. Give the truth table implemented in each LUT. You need not show the wires in the FPGA.


Distinguish between different fault table methods and discuss any one in detail.



Illustrate the generation of a hazard with an example. Also show the excitation map of the circuit indicating the hazardous transition and the timing diagram that illustrates the hazard.