EC2203-DE|G.

Karthikeyan, AP|ECE, SKPEC

EC2203-DIGITAL ELECTRONICS

UNIT IV - MEMORY DEVICES PART-I

G.Karthikeyan M.E., AP | ECE, SKP Engineering College, Tiruvannamalai 606611, Tamilnadu, India

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CONTENTS
Introduction Classification of Memory ROM PROM EPROM EEPROM ROM Origination RAM Static RAM Dynamic RAM RAM Organization DRAM organization Memory Cycles and Timing Waveforms Read Cycle Write Cycle Memory Decoding Coincident Decoding Memory Expansion Expanding Word Size Expanding memory Capacity

EC2203-DE|G.Karthikeyan, AP|ECE, SKPEC

Introduction
Name Memory Meaning/Operation It is made up of registers

Memory Location Address

Capacity

Each register in the memory is one storage location. It is also called as memory location Used to identify the memory location
The total no. of bits that a memory can store is its capacity (Most of the types of capacity is specified in terms of bytes. 1 byte=8bits)

Registers

Consists of storage elements {Flip flop or Capacitors =Semiconductor memories Magnetic domain = Magnetic storage}
It is a storage element The process of storing a data in to a memory The process of retrieving the data from the memory

Cell Write Read

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Read & Write operation

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Block diagram of memory unit

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How a communication is takes place between memory and its environment

1. 2.

Data lines
Provides the information stored in the memory

Address selection lines

Specify the particular word

3.

Control Lines
Direction of transfer

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Classification of memory
CLASSIFICATION OF SEMICONDUCTOR MEMORIES NON VOLATILE
READ ONLY MEMORY (ROM) MaskProgrammable ROM Programmable ROM READ/WRITE MEMORY (NVRAM) EPROM

VOLATILE
READ/WRITE MEMORY (PWM)

RANDOM ACCESS SRAM DRAM

NON RANDOM ACCESS FIFO LIFO Shift Registers

EEPROM Flash

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ROM (Read only Memory)

PROM 2. EPROM 3. EEPROM 4. ROM ORGANIZATION
1.

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ROM CELL

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PROM (Programmable Read Only Memory)

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Four Byte PROM

Diode: Initially all 0
Proper current

pulse: to blow the fuse Fuse material: Nichrome & Polycrystalline Current range to blow fuse: 20 to 50mA Time: 5 to 20s Also called as burning of PROM

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EPROM (Erasable Programmable Read Only Memory)

Uses MOS circuitry Store 1s & 0s

Programmed by

user Erasing the date: by using Ultraviolet light through its quartz window Time: 20minutes Erasing: Entire information lost

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EEPROM (Electrically Erasable Programmable Read Only Memory)

Very Similar to EPROM The insulating layer: very thin (i.e) <200Ao Voltage: 20 to 25 V for programming or erasing Selective information can be erased Time: 10ms

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ROM Organization
Simple Four Byte Diode ROM

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ROM ORGANIZATION (CONTD)

Contents of ROM
Address in binary
00 01 10

Binary Data
D0 1 0 0 D1 0 1 1 D2 1 0 0 D3 0 1 0 D4 0 0 0 D5 1 0 1 D6 0 0 1 D7 1 1 0

Data in Hexa decimal

A5 51 46

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ROM ORGANIZATION (CONTD)

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RAM (Random Access Memory)

Static RAM (SRAM) Static RAM Cell
Read Operation Write operation

Bipolar RAM Cell

MOSFET RAM Cell

Dynamic RAM (DRAM) Dynamic RAM Cell COMPARISON BETWEEN SRAM AND DRAM

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STATIC RAM CELL

Read Operation
Write Operation

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BIPOLAR RAM CELL

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MOSFET RAM CELL

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Dynamic RAM (DRAM)

Dynamic Ram Cell

Storage Capacitor

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COMPARISON BETWEEN SRAM AND DRAM

Sl.No
1

Static RAM

Dynamic RAM

Static RAM contains less memory Dynamic RAM contains more memory cells per area. cells as compared to static RAM per unit area It has less access time hence Its access time is greater than static faster memories RAMs Static RAM consists of flip-flops. Dynamic RAM stores the data as a Each flip-flop stores one bit charge on the capacitor. It consists of MOSFET and the capacitor for each cell. Refreshing required. circuitry is not Refreshing circuitry is required to maintain the charge on the capacitors after every few milliseconds. Extra hardware is required to control refreshing. This makes system design complicated. Cost is less

2 3

Cost is more

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RAM Organization
RAM organization: in the

form of Array Each cell: capable of storing one bit information Memory chip: 8191 bit Line decoder
64 rows 128 columns i.e

13 address lines 6 for rows ( 0 to 5 ) 7 for columns ( 0 to 6 )

64x128=8192 memory cells

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DRAM Organization
Two dimensional It is a 16 M-bit DRAM.

Configured as 2M x 8 Cells organized 4Kx4K array 4096 cells addressed by 12 address bits It can store 512x8, i.e 512 bytes 21 address lines
9 for column ( 0 to 8) 12 for row ( 9 to 20)

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DRAM ORGANIZATION (CONTD)

Configured as 2Mx4 Row & Column

address lines multiplexed: To reduce number of pins So, less address pins than SRAM chip 11 address lines: to select one of 2048 lines for output 211=2048

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Read Cycle
1. 2.

Memory Cycles and Timing Waveforms

tRC tAA tOH tLZ tACS tHZ tOE tDF tPU tPD
ADDRESS DATA CS OE SYPPLY CURRENT

3.
4. 5.

6.
7. 8. 9. 10.

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Write Cycle
1. 2.

Memory Cycles and Timing Waveforms

tWC tAW tWR tAS tCW tWP tDW tDH

3.
4. 5.

6.
7. 8.

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Decoder operation

Memory Decoding

16 words of 8 bits each

A memory with 16 words

needs 4 address lines So, 4 x16 decoder is used If memory enable = 0

If memory enable = 1
One of the 16 word is

No memory word is select

Read/write determines the

selected

operation Write operation:

Data transferred in to eight

memory cells If a memory cell is not selected, that is disabled and the previous value remain unchanged

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Coincident Decoding
k input 2k output
2k and gates are needed

with k input to each gate So, 2 decoders used to reduce the no. of inputs So k/2 inputs to each decoder instead of k inputs Instead of 10 x 1024 we use 5 x 32 decoders

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Illustrate The Concept of 16 X 8 Bit ROM Arrange With Diagram

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Explain the Basic Structure of 256 X 4 Static RAM, with neat diagram

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Memory Expansion
2 methods
1. Expanding word size 2. Expanding memory capacity

3. Limitations for memory expansion

4. Example Problems

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Memory Expansion
Expanding Word Size By connecting 2 or
Design 1 K X 8 RAM using two 1 K X4 ICs

more ICs together Data bus: In Series Address bus: In parallel Chip select: common to Both memory ICs Word size is limited: by Data bus width

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Memory Expansion
Expanding Memory

Capacity

Design 16 K X 8 RAM using four 4 K X 8 ICs

By connecting 2 or more

ICs in parallel i.e. The address & data bus connected in parallel Chip select: separate to each cell(generated by address decoder) Capacity is limited: by address bus width

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Memory Expansion
Limitations for memory Expansion Memory devices: Processors accessed using Address,

data & Control bus But Each Processor has limited no. of address lines & data lines Eg:Suppose a processor has 24 address lines & 16 data lines, we can expand memory word size up to 16 Memory capacity up to 224 = 16Mbytes

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How one can make 64x8 ROM using four 32x4 ROMs? Draw such a circuit and explain
64x8 ROM = Four 32x4 ROM Two pair ICs

Data bus: In series

Address bus: In parallel In two pair: The data, address

& control bus: In parallel To address 32 memory locations: 5 address lines(A0 to A4) needed The additional line: used to select the particular pair(A5)

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Given the 32x8 ROM chip with enable input, show the external connection necessary to construct a 128x8 ROM with four chips and a decoder

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SUMMARY