A Pipeline VLSI Architecture for High-Speed Computation of the 1-D Discrete Wavelet Transform Abstract:

A scheme for the design of a high-speed pipeline VLSI architecture for the computation of the 1-D discrete wavelet transform (DWT) is proposed. In order to assess the feasibility and the efficiency of the proposed scheme, the architecture thus designed is simulated and implemented on a field-programmable gate-array board. It is therefore a challenging problem to design an efficient VLSI architecture to implement the DWT computation for real-time applications. Owing to its regular and flexible structure, the design can be extended easily into different resolution levels, and its area is independent of the length of the 1-D input sequence. Compared with other known architectures, our design requires the least computing time for 1-D lifting DWT. Existing System: Performance Limitation of conventional Programmable DSP Fixed inflexible architectureo Limited number of MAC units o Fixed data width Serial processing limits data throughput Multiple DSPs required to meet bandwidth needs

Proposed System:
Performance Advantages of FPGAs Flexible architecture

o Distributed DSP resources (LUT, registers, multipliers, & memory) Parallel processing maximizes data throughput o Support any level of parallelism o Optimal performance/cost tradeoff FPGAs also support serial processing.

Block Diagram:

Tools used: Device

FPGA Spartan3 XC3S200

Software
Xilinx ISE 8.1i Xilinx Platform Studio Matlab

 Visual Basic

Language used
VHDL & System C

Advantages: Huge amount of disk space is required for the storage and manipulation of digital
still and moving images. Hence image compression is very important in order to reduce the storage needs. Efficient bandwidth.