New DSP Core for Digital Signal Processing

Digital and Analog Lee Seung Youl 2002/9/28

Contents
What is Digital Signal Processing? New DSP Core Instruction Set Sample Micro-Code Schedule

What is Digital Signal Processing?

Decimation Interpolation FIR(finite impulse response) Filtering IIR(infinite impulse response) Filtering Digital Signal Processing related with MAC(multiply and accumulate) architecture Most digital signal processing operation can be performed by new DSP Core

What is Digital Signal Processing?(cont)

external device input

DSP
(Digital Signal Processing)

external device output

Example DSP System

What is Digital Signal Processing?(cont)

DIN

...
h(0) * h(1) * h(n-1) * h(n) *

+
y(n) = h(0)*x(n)+h(1)*x(n-1)+h(2)*x(n-2)+ ... + h(n)*x(0)

DOUT

FIR(finite impulse response) Filter

What is Digital Signal Processing?(cont)

DIN * a(1) *

...
a(0)

+
b(0)
* b(1) *

DOUT

...
y(n) = a(0)*x(n)+a(1)*x(n-1)+...a(N)*x(n-N)+b(1)*y(n-1)+b(2)*y(n-2)+...+b(M)*y(n-M)

IIR(infinite impulse response) Filter

New DSP Core

MAC-Based Architecture
multiply and accumulate 24-bit special memory area for MAC operation

Address Generation Unit

circular addressing for FIFO (first in first out) bounded memory area forward addressing for sample data ( 0 1 ... 49 0 ) backward addressing for FIR or IIR operation ( 0 49 48 ... 2 1 0 ) start address register tap register index register input sample address register output sample address register (for IIR filtering)

Special Register Set

New DSP Core(cont)

ROM 1024x24 IR PC
IR data_ready MAC0_done MAC1_done MAC2_done MAC3_done clear load bypass_ROM bypass_RAM

ROM 1024x24
A B

RAM 1024x24

MAC

Instruction Decoder

data_send IIR0 register set

IIR1 register set FIR0 register set FIR1 register set

external devices

IIR0 address generation unit IIR1 address generation unit

FIR0 address generation unit FIR1 address generation unit

special register set

address generation unit

DSP Core Architecture

New DSP Core(cont)

ROM_DATA(A) RAM_DATA(B)

multiply + addition
*

bypass_ROM bypass_RAM load_MAC

MUX

bypass_ROM bypass_RAM load_MAC

CLK RESET LOAD CLEAR

24-bit register

ACC_OUT

MAC(Multiply And Accumulate)

New DSP Core(cont)

RAM_ADDR SAMPLE_ADDR LOAD_SAMPLE

FIR address selector

MAC_RAM_ADDR

IR_IMM next_sample_addr LOAD_SAMPLE

FIR special register set

start_addr tap index sample_addr

FIR address generation unit

ROM_ADDR RAM_ADDR next_sample_addr

other control signals

IR_IMM next_input_sample_addr LOAD_INPUT_SAMPLE next_output_sample_addr LOAD_OUTPUT_SAMPLE

...

RAM_ADDR INPUT_SAMPLE_ADDR LOAD_INPUT_SAMPLE OUTPUT_SAMPLE_ADDR LOAD_OUTPUT_SAMPLE start_addr tap index sample_addr

IIR address selector

MAC_RAM_ADDR

IIR special register set

IIR address generation unit

ROM_ADDR RAM_ADDR
next_input_sample_addr next_output_sample_addr

Address Generation Unit

New DSP Core(cont)

-- FIR address generation FIR_ROM_ADDR = START_ADDR + INDEX; => circular forward addressing if ( (SAMPLE_ADDR-1-INDEX) < START_ADDR ) FIR_RAM_ADDR = SAMPLE_ADDR-1-INDEX+TAP; else FIR_RAM_ADDR = SAMPLE_ADDR-1-INDEX; => circular backward addressing if ( (SAMPLE_ADDR+1) < (START_ADDR+TAP) ) SAMPLE_ADDR_NEXT = SAMPLE_ADDR+1; else SAMPLE_ADDR_NEXT = SAMPLE_ADDR+1-TAP; => circular forward addressing -- IIR address generation IIR_ROM_ADDR = START_ADDR + INDEX; if ( INDEX < (TAP/2) ) //input sample memory area if ( (INPUT_SAMPLE_ADDR-1-INDEX) < START_ADDR ) IIR_RAM_ADDR = INPUT_SAMPLE_ADDR-1-INDEX+TAP/2; else IIR_RAM_ADDR = INPUT_SAMPLE_ADDR-1-INDEX; else //output sample memory area if ( (OUTPUT_SAMPLE_ADDR-1-INDEX) < START_ADDR ) IIR_RAM_ADDR = OUTPUT_SAMPLE_ADDR-1-INDEX+TAP; else IIR_RAM_ADDR = OUTPUT_SAMPLE_ADDR-1-INDEX+TAP/2; if ( (INPUT_SAMPLE_ADDR+1) < (START_ADDR+TAP/2) ) INPUT_SAMPLE_ADDR_NEXT = INPUT_SAMPLE_ADDR+1; else INPUT_SAMPLE_ADDR_NEXT = INPUT_SAMPLE_ADDR+1-TAP/2; if ( (OUTPUT_SAMPLE_ADDR+1) < (START_ADDR+TAP) ) OUTPUT_SAMPLE_ADDR_NEXT = OUTPUT_SAMPLE_ADDR+1; else OUTPUT_SAMPLE_ADDR_NEXT = OUTPUT_SAMPLE_ADDR+1-TAP/2;

=> circular forward addressing

=> circular backward addressing

=> circular backward addressing

=> circular forward addressing

=> circular forward addressing

Address Generation Unit

New DSP Core(cont)

clear_START_ADDR load_START_ADDR clear_TAP load_TAP clear_INDEX load_INDEX incr_INDEX clear_SAMPLE_ADDR load_SAMPLE_ADDR

clear_START_ADDR load_START_ADDR

start address register tap register index register

input sample address register output sample address register

start address register

tap register
index register sample address register

clear_TAP load_TAP clear_INDEX load_INDEX incr_INDEX clear_INPUT_SAMPLE_ADDR load_INPUT_SAMPLE_ADDR clear_OUTPUT_SAMPLE_ADDR load_OUTPUT_SAMPLE_ADDR

FIR register set

IIR register set

Special Register Set

New DSP Core(cont)

1023

sel_ROM_ADDR MAC[2:0]
IR_MEM_ADDR
MAC0_ROM_ADDR MAC1_ROM_ADDR MAC2_ROM_ADDR MAC3_ROM_ADDR M U X ROM_ADDR

M U X

ROM1024x24

ROM_DATA

MAC_ADDR

sel_RAM_ADDR MAC[2:0]
IR_MEM_ADDR 256 MAC0_RAM_ADDR MAC1_RAM_ADDR MAC2_RAM_ADDR MAC3_RAM_ADDR M U X M U X RAM_ADDR

FIR MAC area 3 FIR MAC area 2 IIR MAC area 1 IIR MAC area 0
0

MAC_ADDR

we_RAM sel_RAM_DATA[1:0]
IR_IMM EXT_DATA ACC_DATA

RAM1024x24

RAM_DOUT

ROM and RAM memory layout

M U X

RAM_DIN

Memory Management Unit

New DSP Core(cont)

h(6) h(5) h(4) h(3) h(2) h(1) h(0) 0 0 0 0 x(2) x(1) x(0) h(6) h(5) h(4) h(3) x(6) x(5) x(4) x(3)

h(2)
h(1) h(0)

x(2)
x(8) x(7)

FIR circular addressing -circular forward addressing for sample address -backward addressing for MAC operation

output sample memory area 0 b(2) b(1) b(0) a(2) a(1)

0 0 y(1) y(0) x(2) x(1)

0 b(2) b(1) b(0) a(2) a(1) a(0)

0 y(2) y(1) y(3) x(2) x(4) x(3)

a(0)
input sample memory area

x(0)

IIR circular addressing -circular forward addressing for sample address -backward addressing for MAC operation

Memory & MAC Operation

New DSP Core(cont)

IR[23:0] data_ready
clear_IR load_IR clear_PC load_PC incr_PC bypass_ROM bypass_RAM clear_MAC load_MAC

Instruction Decoder

MAC0_done MAC1_done MAC2_done MAC3_done

clear_START_ADDR_MAC0 load_START_ADDR_MAC0 clear_TAP_MAC0 load_TAP_MAC0 clear_INDEX_MAC0 load_INDEX_MAC0 incr_INDEX_MAC0 clear_INPUT_SAMPLE_ADDR_MAC0 load_INPUT_SAMPLE_ADDR_MAC0 clear_OUTPUT_SAMPLE_ADDR_MAC0 load_OUTPUT_SAMPLE_ADDR_MAC0

data_send

Instruction Decoder

... ...

New DSP Core(cont)

INSTRUCTION ROM1024x24
clear_IR load_IR

INSTRUCTION REGISTER

IR

INSTRUCTION DECODER
IR_MEM_ ADDR

PC

PROGRAM COUNTER

clear_PC load_PC incr_PC

Caution : In this architecture, JUMP instruction takes two clock cycles 1st stage : decode JUMP instruction, clear IR, load IR memory address into PC 2nd stage : execute NOP instruction, load mem[JUMP_ADDR] into IR

Program Counter & Instruction Register

Instruction Set
0. NOP : single clock cycle => 00 000 0000000000000000000 1. MOV : single clock cycle - from IR to RAM : 00 111 IR_IMM(9bit) IR_MEM_ADDR(10bit) - from ROM or RAM to ACC : 00 001 ROM_or_RAM(1bit) 00000000 IR_MEM_ADDR(10bit) - from external input to RAM : 00 010 000000000 IR_MEM_ADDR(10bit) - from immediate to register : 00 011 IR_IMM(9bit) 0000 REG(3bit) MAC(3bit) - from ACC to external output : 00 100 000000000 0000000000 - from ACC to IIR MAC area : 00 101 0000000000000000 MAC(3bit) 2. MAC (multiply and accumulate) : multiple clock cycles => 01 0000000000000000000 MAC(3bit) 3. JUMP : two clock cycles => 10 000000000000 IR_MEM_ADDR(10bit) 4. OTHER : single clock cycles - WAIT : 11 000 0000000000000000000 - clear MAC : 11 001 0000000000000000000 - from ACC to MAC area : 11 010 0000000000000000 MAC(3bit) - from IR to MAC area : 11 011 0000000000000000 MAC(3bit)

Sample Micro-Code
0 - 000110000000000000000000; //from IR(0) to MAC 0 START ADDR register 1 - 000110001100100000001000; //from IR(50) to MAC 0 TAP register 2 - 000110000000000000010000; //from IR(0) to MAC 0 INDEX register 3 - 000110000000000000011000; //from IR(0) to MAC 0 INPUT SAMPLE ADDR register 4 - 000110000110010000100000; //from IR(25) to MAC0 OUTPUT SAMPLE ADDR register 5 - 000110001100100000000010; //from IR(50) to MAC 2 START ADDR register 6 - 000110011001100000001010; //from IR(102) to MAC 2 TAP register 7 - 000110000000000000010010; //from IR(0) to MAC 2 INDEX register 8 - 000110001100100000011010; //from IR(50) to MAC 2 SAMPLE ADDR register 9 - 000110100110000000000011; //from IR(152) to MAC 3 START ADDR register 10 - 000110011010000000001011; //from IR(104) to MAC 3 TAP register 11 - 000110000000000000010011; //from IR(0) to MAC 3 INDEX register 12 - 000110100110000000011011; //from IR(152) to MAC 3 SAMPLE ADDR register 13 - 110000000000000000000000; //WAIT external input data 14 - 001100000000000000000000; //from external input data to MAC 0 15 - 010000000000000000000000; //MAC #0 16 - 001010000000000000000000; //from ACC to IIR MAC 0 17 - 110100000000000000000010; //from ACC to MAC 2 18 - 110010000000000000000000; //CLEAR MAC 19 - 010000000000000000000010; //MAC #2 20 - 110100000000000000000011; //from ACC to MAC 3 21 - 110010000000000000000000; //CLEAR MAC 22 - 010000000000000000000011; //MAC #3 23 - 001000000000000000000000; //from ACC to external output device 24 - 110110000000000000000011; //from IR(0) to MAC area 3 25 - 110010000000000000000000; //CLEAR MAC 26 - 010000000000000000000011; //MAC #3 27 - 001000000000000000000000; //from ACC to external output device 28 - 110110000000000000000011; //from IR(0) to MAC area 3 29 - 110010000000000000000000; //CLEAR MAC 30 - 010000000000000000000011; //MAC #3

Sample Micro-Code
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 001000000000000000000000; 110110000000000000000011; 110010000000000000000000; 010000000000000000000011; 001000000000000000000000; 110110000000000000000010; 110010000000000000000000; 010000000000000000000010; 110100000000000000000011; 110010000000000000000000; 010000000000000000000011; 001000000000000000000000; 110110000000000000000011; 110010000000000000000000; 010000000000000000000011; 001000000000000000000000; 110110000000000000000011; 110010000000000000000000; 010000000000000000000011; 001000000000000000000000; 110110000000000000000011; 110010000000000000000000; 010000000000000000000011; 001000000000000000000000; 100000000000000000001101; //from ACC to external output //from IR(0) to MAC area 3 //CLEAR MAC //MAC #3 //from ACC to external output //from IR(0) to MAC area 2 //CLEAR MAC //MAC #2 //from ACC to MAC area 3 //CLEAR MAC //MAC #3 //from ACC to external output //from IR(0) to MAC area 3 //CLEAR MAC //MAC #3 //from ACC to external output //from IR(0) to MAC area 3 //CLEAR MAC //MAC #3 //from ACC to external output //from IR(0) to MAC area 3 //CLEAR MAC //MAC #3 //from ACC to external output //JUMP #13 device device

device

device

device

device

Schedule
4 Weeks