Bank Switching, Table Processing, Macros and Modules

Chapter 6

Introduction
The CPU has several addressing modes; way of accessing the data in registers or memory. 4 distinct addressing modes:
Immediate Direct Register Indirect Indexed-ROM

Immediate Addressing (literal)

MOVLW SUBLW ANDLW 0X25 D 62 D 55

Direct Addressing
MOVWF MOVFF 0X56 0X40

SFR Registers and Their Addresses

MOVWF 0xF81 Same as MOVWF PORTB

Study Example 6-1

Register Indirect Addressing Mode

This instructions are valid:
MOVLW MOVWF 0x55 0x30 ; (30h) = 55h

Problem: What if the address greater than 0xff ?

MOVLW MOVWF 0x55 0x123 ;(123h) = 55h? WRONG!

limited to 8-bits only!

Register Indirect Addressing Mode (contd)

A register is used as a pointer to data RAM location. 3 registers involved: FSR0, FSR1, FSR2 Each FSR has low-byte (FSRxL) and high-byte (FSRxH)
i.e: LFSR 0, 0xfff LFSR 1, 0x123 LFSR 2, 0x5d4 ;load FSR0 with fffh ;load FSR1 with 123h ;load FSR2 with 5d4h

Register Indirect Addressing Mode (contd)

Study!
Workout Example 6-2, 6-3, 6-4, 6-5, 6-6, 6-7

Define Byte (DB) & Fixed Data

ORG 500H DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DB D'28' DB B'00110101' DB 0x39 ORG 510H DB 'Y' DB '2','0','0','5 ORG 518H DB "Hello ALI" END ;Even Address ;Number

;Even Address ;ASCII ;Even Address ;ASCII string

Study Example 6-8!

Table Processing
TBLPTR is a 21-bit register used as table pointer. TBLPTR is divided into:
TBLPTRL (low) TBLPTRH (high) TBLPTRU (upper)

TABLAT (TABle LATch) register is used for keeping the byte fetched or to be written.

 There are two operations that allow the processor to move bytes between the program memory space and the data RAM:
Table Read (TBLRD) Table Write (TBLWT)

Table Read Operation

Table Write Operation

DATA MEMORY PROGRAM MEMORY OPERATIONS

Example 6-9
ORG CLRF MOVLW MOVWF MOVLW MOVWF TBLRD* MOVFF INCF TBLRD* MOVFF INCF TBLRD* MOVFF GOTO ORG DB END 0000H TRISB 0x0 TBLPTRL 0x05 TBLPTRH

Lets evaluate through MPLAB!

TABLAT,PORTB TBLPTRL,F
TABLAT,PORTB TBLPTRL,F TABLAT,PORTB HERE 500H "USA"

HERE

MYDATA

Study!!!
Example 6-10, 6-11, 6-12 Example 6-17 to 6-24

Bank Switching in the PIC18

Bank Switching in the PIC18

The use of the BSR allows users to address the entire range of data memory. When a is equal to 1, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address.

When a is 0 however, the instruction is forced to use the Access Bank address map.

Study!
Example 6-25 to 6-28

Checksum
Checksum: to detect any corruption of the contents of ROM Workout Example 6-29

Macros and Modules

MACRO LOCAL INCLUDE Macros vs. Subroutine Modules
EXTERN GLOBAL