EVL 104 VLSI DESIGN LAB-I

Ex.No:1 MODELING OF SEQUENTIAL DIGITAL SYSTEMS USING VHDL Aim: To model sequential digital systems using VHDL. Softwares Required: Xilinx ISE 7.1i 4 bit synchronous Up down Counter: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(Clock, Clear, UP_DOWN : in std_logic; Q : out std_logic_vector(3 downto 0)); end counter; architecture archi of counter is signal temp: std_logic_vector(3 downto 0); begin process (Clock, Clear) begin if (Clear='1' ) then temp <= "0000"; elsif (Clock event and Clock='1') then if (UP_DOWN='1') then temp <= temp + 1; else temp <= temp - 1; end if; end if; end process; Q <= temp; end archi;

Finite state Machines: Moore model: State Diagram of a Moore Machine:

Source code: library IEEE; use IEEE.std_logic_1164.all; entity fsm is port ( clk, reset, x1 : IN std_logic; outp : OUT std_logic); end fsm; architecture beh1 of fsm is type state_type is (s1,s2,s3,s4); signal state: state_type ; begin process (clk,reset) begin if (reset ='1') then state <=s1; outp<='1'; elsif (clk='1' and clk'event) then case state is when s1 => if x1='1' then state <= s2; else state <= s3; end if; outp <= '1'; when s2 => state <= s4; outp <= '1';

when s3 => state <= s4; outp <= '0'; when s4 => state <= s1; outp <= '0'; end case; end if; end process; end beh1; SHIFT REGISTERS: 4 BIT SERIAL IN SERIAL OUT SHIFT REGISTER: library ieee; use ieee.std_logic_1164.all; entity shift is port(CLK, SI, CLEAR : in std_logic; SO : out std_logic); end shift; architecture archi of shift is signal temp: std_logic_vector(4 downto 0); begin process (CLK, CLEAR) begin if (CLEAR='1') then temp <= (others => '0'); elsif (CLK'event and CLK='1') then temp <= temp(3 downto 0) & SI; end if; end process; SO <= temp(4); end archi;

RESULT:

Ex.No:2 MODELING OF SEQUENTIAL DIGITAL SYSTEMS USING VERILOG Aim: To model sequential digital systems using Verilog. Softwares Required: Xilinx ISE 7.1i 4 bit synchronous Up down Counter: Source code: module counter (Clock, Clear, UP_DOWN, Q); input Clock, Clear, UP_DOWN; output [3:0] Q; reg [3:0] temp; always @(posedge Clock or posedge Clear) begin if (Clear) temp = 4'b0000; else if (UP_DOWN) temp = temp + 1'b1; else temp = temp - 1'b1; end assign Q = temp; endmodule

Finite state Machines: Moore model: State Diagram of a Moore Machine:

Source code: module fsm (clk, reset, x1, outp); input clk, reset, x1; output outp; reg outp; reg [1:0] state; parameter s1 = 2'b00; parameter s2 = 2'b01; parameter s3 = 2'b10; parameter s4 = 2'b11; always@(posedge clk or posedge reset) begin if (reset) begin state = s1; outp = 1'b1; end

else begin case (state) s1: begin if (x1==1'b1) state = s2; else state = s3; outp = 1'b1; end s2: begin state = s4; outp = 1'b1; end s3: begin state = s4; outp = 1'b0; end s4: begin state = s1; outp = 1'b0; end endcase end end endmodule SHIFT REGISTERS: 4 BIT SERIAL IN SERIAL OUT SHIFT REGISTER: module shift1 (CLK, CLEAR, SI, SO); input CLK,SI,CLEAR; output SO; reg [4:0] temp; always @(posedge CLK or posedge CLEAR) begin if (CLEAR) tmp = 5'b00000; else begin temp = {temp[3:0], SI}; end end assign SO = temp[4]; endmodule

RESULT:

Ex.No:3 FPGA Aim:

DESIGN AND IMPLEMENTATION OF ALU USING

To design and implement ALU using FPGA.. Softwares Required: Xilinx ISE 7.1i Verilog Source Code: module compar(A, B,sum,sub,mul,,lor,lnot,lshift,rshift); input [7:0] A; input [7:0] B; output output output output output output output output wire wire wire wire wire wire wire wire [16:0] mul; [7:0] sum; [7:0] sub; [7:0] land; [7:0] lor; [7:0] lnot; [7:0] lshift; [7:0] rshift;

[7:0] sum; [7:0] sub; [16:0] mul; [7:0] land; [7:0] lor; [7:0] lnot; [7:0] lshift; [7:0] rshift; sum = A + B; sub = A - B; mul = A * B; land = A & B; lor = A | B; lnot =~ A;

assign assign assign assign assign assign

assign lshift=A<<2; assign rshift=A>>2; endmodule

VHDL Source Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity alu2 is Port ( clk: in std_logic; enable: in std_logic; a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); result : out std_logic_vector(7 downto 0); carry : out std_logic ); end alu2; architecture Behavioral of alu2 is begin process(clk) variable temp : std_logic_vector(8 downto 0):= (others=> '0'); begin if rising_edge(clk) then if( enable ='1') then case sel is when "000" => -- add temp := ('0' & a) + ('0' & b); result <= temp(7 downto 0); carry <= temp(8); when "001" => -- sub

temp :=('0'& a) - ('0' & b); result <= temp(7 downto 0); carry <= temp(8); when "010" => result <= not a; -- complement when "011" => temp(7 downto 0) := a(3 downto 0) * b(7 downto 4); -- Mul result <= temp(7 downto 0); when "100" => result <= a and b ; -- and when "101" => result <= a or b; -- or when "110" => result <= a nand b; -- nand when "111" => result <= a xor b; -- xor when others => result <= "00000000"; carry <= '0'; end case; else result <= "ZZZZZZZZ"; carry <= 'Z'; end if; end if; end process; end Behavioral;

RESULT:

Ex.No:4

TEST BENCH CODE FOR ALU

Aim: To simulate test bench code for ALU using VHDL and Verilog. Softwares Required: Xilinx ISE 7.1i Verilog Test bench Code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY alutb_vhd IS END alutb_vhd; ARCHITECTURE behavior OF alutb_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT alu2 PORT( clk : IN std_logic; enable : IN std_logic; a : IN std_logic_vector(7 downto 0); b : IN std_logic_vector(7 downto 0); sel : IN std_logic_vector(2 downto 0); result : OUT std_logic_vector(7 downto 0); carry : OUT std_logic ); END COMPONENT;

--Inputs SIGNAL clk : std_logic := '0'; SIGNAL enable : std_logic := '0'; SIGNAL a : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL b : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL sel : std_logic_vector(2 downto 0) := (others=>'0'); --Outputs SIGNAL result : std_logic_vector(7 downto 0); SIGNAL carry : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: alu2 PORT MAP( clk => clk, enable => enable, a => a, b => b, sel => sel, result => result, carry => carry ); TB:PROCESS BEGIN clk <= '1'; wait for 5 ns; clk <= '0'; wait for 5 ns; end process; PROCESS BEGIN enable <= '1'; wait for 20 ns; end process; PROCESS BEGIN -- Case "000" a<="00011111"; b<="11001111"; wait for 10 ns; sel <= "001"; wait for 10 ns;

-- clock cycle 10 ns

sel <= "001"; wait for 10 ns; sel <= "010"; wait for 10 ns; sel <= "011"; wait for 10 ns; sel <= "100"; wait for 10 ns; sel <= "101"; wait for 10 ns; sel <= "110"; wait for 10 ns; sel <= "111"; wait for 10 ns; end process; END behavior; ----------------------------------------------------------configuration CFG_TB of alutb_vhd is for behavior end for; end CFG_TB; --------------------------------------------------------------------------------

Verilog Test bench Code: module aluu_v; // Inputs reg [7:0] A; reg [7:0] B; // Outputs

wire wire wire wire wire wire wire wire

[16:0] mul; [7:0] sum; [7:0] sub; [7:0] land; [7:0] lor; [7:0] lnot; [7:0] lshift; [7:0] rshift;

// Instantiate the Unit Under Test (UUT) compar uut ( .A(A), .B(B), .mul(mul), .sum(sum), .sub(sub), .land(land), .lor(lor), .lnot(lnot), .lshift(lshift), .rshift(rshift) ); initial begin // Initialize Inputs A = 8'b00111110; B = 8'b11111110; // Wait 100 ns for global reset to finish #200; A = 8'b11111110; B = 8'b11111111; #200; A = 8'b10001110; B = 8'b00000001; #200; end endmodule.

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Ex.No:5 PSPICE Aim:

SIMULATION OF NMOS,PMOS,CMOS CIRCUITS USING

To simulate NMOS ,PMOS,CMOS circuits using PSPICE Softwares Required: ORCAD 10.3 Capture. CIRCUIT DIAGRAM: NMOS:

V 3 . 3 v

R 1 1 k

0
V 1 V 2 T D T R T F P W P E = = = = = R V 2 . 3 . 5 n n n = 1 00 0 = 0 0 3 0 1 1 M
V

M b r e

1 a k N

PMOS:

V 3 . 3 v

R 1 1 k

0
V 1 V 2 T D T R T F P W P E = = = = = R V 2 . 3 . 5 n n n = 1 00 0 = 0 0 3 0 1 1
V

M M b

2
V

r e

a k

CMOS:

M V 3 . 3 v 1 M b r e

3 a k N

0
M V 1 V 2 T D T R T F P W P E = = = = = R V 2 . 3 . 5 n n n = 1 00 0 = 0 0 3 0 1 1 M b 4 r e a k P

Netlist:

Result:

Ex.No:6 Aim:

DESIGN & IMPLEMENTATION OF STATIC RAM.

To design & implement Static RAM circuit using FPGA.. Softwares Required: Xilinx ISE 7.1i VHDL Souce code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity staticram is port (clk : in std_logic; en : in std_logic; we : in std_logic; a : in std_logic_vector(4 downto 0); di : in std_logic_vector(3 downto 0); do : out std_logic_vector(3 downto 0)); end staticram; architecture syn of staticram is type ram_type is array (31 downto 0) of std_logic_vector (3 downto 0); signal RAM : ram_type;

signal read_a : std_logic_vector(4 downto 0); begin process (clk) begin if (clk'event and clk = '1') then if (en = '1') then if (we = '1') then RAM(conv_integer(a)) <= di; end if; read_a <= a; end if; end if; end process; do <= RAM(conv_integer(read_a)); end syn;

VERILOG Source Code: module staticram1 (clk, en, we, a, di, do); input clk; input en; input we; input [4:0] a; input [3:0] di; output [3:0] do; reg [3:0] ram [31:0]; reg [4:0] read_a; always @(posedge clk) begin if (en) begin if (we) ram[a] <= di; read_a <= a; end end assign do = ram[read_a]; endmodule

RESULT:

Ex.No:7 Aim:

MODELING OF MOSFET USING C

To model NMOS and PMOS using turbo C Language. Softwares Required: Turbo C Language Program:

//N Channel MOSFET modeling//

#include<conio.h> #include<stdio.h> #include<math.h> main( ) { float vds,vgs,vt,ids,w,l,vsb,beta; float vto,kp,gamma,phi,lambda,ld,tox,nsub; clrscr( ); printf(\n N-channel MOSFET Modeling \n); vto=0.7; kp=8*pow(10,-5); gamma=0.4; phi=0.37; lambda=0.01;

ld=0.1*pow(10,-6); tox=2*pow(10,-8); nsub=4*pow(10,16); printf(\n Enter Drain to source voltage vds=); scanf(%f,&vds); printf(\n Enter Gate to source voltage vgs=); scanf(%f,&vgs); printf(\n Enter the width(in um) w=); scanf(%f,&w); printf(\n Enter the length(in um) l= ); scanf(%f,&l); printf(\n Enter the value of source to bulk potential vsb=); scanf(%f,&vsb); printf(\n The following default values are taken \n); printf(\n Threshold voltage vto=0.7v \n); printf(\n Transconductance coefficient kp=8e-5 A/v \n); printf(\n Bulk threshold parameter gamma =0.4 \n); printf(\n surface potential Phi=0.37 \n); printf(Channel length modulation parameter Lambda=0.01 \n); printf(Lateral Diffusion ld=0.1e-6 \n); printf(Oxide thickness tox=2e-8 \n); printf(Enter any key to continue); clrscr(); vt=vto+gamma*(sqrt(2*phi+vsb)-(sqrt(2*phi))); printf(\n\n\n\n Threshold voltage vt is= \n); beta=(500*3.9*8.854*pow(10,-14)*w)/(200*pow(10,-10)*1); if(vgs<vt) { printf(The transistor is in cutoff region \n); ids=0; } elseif(vgs>vt && vds<(vgs-vt)) { printf(The transistor is in linear region \n); ids=(beta/2)*(vgs-vt)*(vgs-vt)*(1+(lambda*vds))*1000; } printf(The Drain source current is %f in mA,ids); getch(); }

//P Channel MOSFET modeling//

#include<conio.h> #include<stdio.h>

#include<math.h> main( ) { float vds,vgs,vtp,ids,w,l,vsb,beta; float vto,kp,gamma,phi,lambda,ld,tox,nsub; clrscr(); printf(\n N-channel MOSFET Modeling \n); vto=0.7; kp=2.5*pow(10,-5); gamma=0.5; phi=0.36; lambda=0.01; ld=0.1*pow(10,-6); tox=2*pow(10,-8); nsub=4*pow(10,16); printf(\n Enter Drain to source voltage vds=); scanf(%f,&vds); printf(\n Enter Gate to source voltage vgs=); scanf(%f,&vgs); printf(\n Enter the width(in um) w=); scanf(%f,&w); printf(\n Enter the length(in um) l= ); scanf(%f,&l); printf(\n Enter the value of source to bulk potential vsb=); scanf(%f,&vsb); printf(\n The following default values are taken \n); printf(\n Threshold voltage vto=0.7v \n); printf(\n Transconductance coefficient kp=8e-5 A/v \n); printf(\n Bulk threshold parameter gamma =0.4 \n); printf(\n surface potential Phi=0.37 \n); printf(Channel length modulation parameter Lambda=0.01 \n); printf(Lateral Diffusion ld=0.1e-6 \n); printf(Oxide thickness tox=2e-8 \n); printf(Enter any key to continue); clrscr(); vtp=vto+gamma*(sqrt(2*phi+vsb)-(sqrt(2*phi))); printf(\n\n\n\n Threshold voltage vt is= \n); beta=(500*3.9*8.854*pow(10,-14)*w)/(200*pow(10,-10)*1); if(vgs>vtp) { printf(The transistor is in cutoff region \n); ids=0; } elseif(vgs<vtp && vds>(vgs-vtp)) { printf(The transistor is in linear region \n);

idsp=(beta/2)*((vgs-vtp)*(vgs-vtp))*(1+(lambda*vds))*1000; } printf(The Drain source current is %f in mA,idsp); getch(); }

RESULT:

Ex.No:8 DESIGN AND IMPLEMENTATION OF FIR AND IIR FILTERS USING VERILOG Aim: To design and implement FIR and IIR filters using verilog. Softwares Required: Xilinx ISE 7.1i Source code: FIR Filter: module FIRlowpass(dataout,datain,clock,reset); parameter order=8; parameter wordsizein=8; parameter wordsizeout=2*wordsizein+2; parameter b0=8'd7; parameter b1=8'd17; parameter b2=8'd32; parameter b3=8'd46; parameter b4=8'd52; parameter b5=8'd46;

parameter b6=8'd32; parameter b7=8'd7; parameter b8=8'd7; output [wordsizeout-1:0] dataout; input [wordsizein-1:0] datain; input clock,reset; reg [wordsizein-1:0] samples[1:order]; integer k; assign dataout=b0*datain+ b1*samples[1]+ b2*samples[2]+ b3*samples[3]+ b4*samples[4]+ b5*samples[5]+ b6*samples[6]+ b7*samples[7]+ b8*samples[8]; always @(posedge clock) if(reset==1) begin for(k=1;k<=order;k=k+1) samples[k]<=0; end else begin samples[1]<=datain; for(k=2;k<=order;k=k+1) samples[k]<=samples[k-1]; end endmodule IIR Filter : Source code: module IIRlowpass(dataout,datain,clock,reset); parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter order=8; wordsizein=8; wordsizeout=2*wordsizein+2; b0=8'd7; b1=0; b2=0; b3=0; b4=0; b5=0; b6=0; b7=0; b8=0;

parameter parameter parameter parameter parameter parameter parameter parameter

a1=8'd46; a2=8'd32; a3=8'd17; a4=8'd0; a5=8'd17; a6=8'd32; a7=8'd46; a8=8'd52;

output [wordsizeout-1:0] dataout; input [wordsizein-1:0] datain; input clock,reset; reg [wordsizein-1:0] samplesin[1:order]; reg [wordsizein-1:0] samplesout[1:order]; wire [wordsizeout-1:0] datafeedforward; wire [wordsizeout-1:0] datafeedback; integer k; assign datafeedforward=b0*datain+ b1*samplesin[1]+ b2*samplesin[2]+ b3*samplesin[3]+ b4*samplesin[4]+ b5*samplesin[5]+ b6*samplesin[6]+ b7*samplesin[7]+ b8*samplesin[8]; assign datafeedback=a1*samplesout[1]+ a2*samplesout[2]+ a3*samplesout[3]+ a4*samplesout[4]+ a5*samplesout[5]+ a6*samplesout[6]+ a7*samplesout[7]+ a8*samplesout[8]; assign dataout=datafeedforward+datafeedback; always @(posedge clock) if(reset==1) for(k=1;k<=order;k=k+1) begin samplesin[k]<=0; samplesout[k]<=0;

end else begin samplesin[1]<=datain; samplesout[1]<=dataout; for(k=2;k<=order;k=k+1) begin samplesin[k]<=samplesin[k-1]; samplesout[k]<=samplesout[k-1]; end end endmodule

RESULT:

Ex.No:9 Aim:

MULTIRATE SIGNAL PROCESSING

To design & implement decimator using Verilog. Softwares Required: Xilinx ISE 7.1i,MATLAB 7.0 Source Code: module decimator(datain, hold, clock, reset, dataout); parameter wordlength=8; input [wordlength-1:0] datain; input hold; input clock;

input reset; output [wordlength-1:0] dataout; reg dataout; always@(posedge clock) if(reset)dataout<=0; else if(hold)dataout<=dataout; else dataout<=datain; endmodule Source Code Using MATLAB: %%Decimation Pocess N=input('Length of input signal='); M=input('Down sampling factor='); f1=input('frequency of first sinusoid='); f2=input('frequency of second sinusoid='); n=0:N-1 x=sin(2*pi*f1*n)+sin(2*pi*f2*n); y=decimate(x,M); subplot(2,1,1) stem(n,x(1:N)); title('Input Sequence'); xlabel('time index n'); ylabel('Amplitude'); subplot(2,1,2); m=0:N/M-1; stem(m,y(1:N/M)); title('output sequence'); xlabel('time index n'); ylabel('Amplitude');

RESULT:

Ex.NO:10 DESIGN AND IMPLEMENTATION OF DSP ALGORITHMS USING SOFTWARE PACKAGE Aim: To design and implement Convolution and FFT algorithms using TMS320C50 DSP processor. Softwares Required: TMS320C50 Processor Kit LINEAR CONVALUTION: .mmregs .text START: LDP #02H LAR AR1,#8100H ; x(n) datas lar ar0,#08200H ;h(n) datas

LAR AR3,#8300H ;y(n) starting LAR AR4,#0007 ;N1+N2-1;to fold the h(n) values ;************************ lar ar0,#8203H ; data mem 8200 to program mem c100(tblw) lacc #0c100h mar *,ar0 rpt #3 tblw *- ;to move 8203- 8200 to c100- c103;padding of zerros for x(n) values ;********************************** lar ar6,#8104h mar *,ar6 lacc #0h rpt #3h sacl *+;convalution operation starts ;****************************** LOP: MAR *,AR1 LACC *+ SACL 050H ;starting of the scope of multiplication LAR AR2,#0153H ; end of the array, to be multiplied with h(n) {150+N1-1} MAR *,AR2 ZAP RPT #03H ;N1-1 times so that N1 times MACD 0C100H,*APAC ;to accmulate the final product sample MAR *,AR3 SACL *+ MAR *,AR4 BANZ LOP,*H: B H

FAST FOURIER TRANSFORM: IN .set 8010H BITREV .set 8020H REAL .set 8040H IMG .set 8050H .MMREGS .TEXT LDP #100H LAR AR1,#IN LAR AR2,#BITREV SPLK #2H,05H LMMR INDX,#8005H

MAR *,AR2 RPT #3H BLDD #IN,*BR0+ LAR AR2,#BITREV LAR AR3,#8030H LAR AR0,#1H FFT1: MAR *,AR2 LACC *+ SACB LT *+ MPY #1H APAC MAR *,AR3 SACL *+ LACB SPAC SACL *+,AR0 BANZ FFT1,*LAR AR3,#8030H LAR AR4,#REAL LAR AR5,#IMG MAR *,AR3 LACC * SACB ADRK #2H LT *MPY #1H APAC MAR *,AR4 SACL * ADRK #2H LACC #0H MAR *,AR5 SACL * ADRK #2H LACB SPAC MAR *,AR4 SACL *LACC #0H MAR *,AR5 SACL *-,AR3 LACC *,AR4 SACL *

ADRK #2H SACL *,AR3 ADRK #2H LT * MPY #0FFFFH MAR *,AR5 SPL *,AR3 LT * MPY #1H MAR *,AR5 ADRK #2H SPL * H: B H

RESULT:

EX.NO:11 UNIT Aim:

DESIGN AND IMPLEMENTATION OF MAC

To design and implement MAC unit using FPGA.. Softwares Required: Xilinx ISE 7.1i VHDL Source Code:

2x2 Multiplier: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multiplier is port(num1, num2: in std_logic_vector(1 downto 0); product: out std_logic_vector(3 downto 0) ); end multiplier; architecture Behavioral of multiplier is begin process(num1, num2) variable num1_reg: std_logic_vector(2 downto 0); variable product_reg: std_logic_vector(5 downto 0); begin num1_reg := '0' & num1; product_reg := "0000" & num2; -- use variables doing computation -- algorithm is to repeat shifting/adding for i in 1 to 3 loop if product_reg(0)='1' then product_reg(5 downto 3) := product_reg(5 downto 3) + num1_reg(2 downto 0); end if; product_reg(5 downto 0) := '0' & product_reg(5 downto 1); end loop; product <= product_reg(3 downto 0); end process; end Behavioral;

Verilog Source Code: Sequential Multiplier: module multiplier1(product, ready, word1, word2, start,clock, reset); parameter lword=4;

output [2*lword-1:0] product; output ready; input input input input [lword-1:0] word1; [lword-1:0] word2; clock,start; reset;

wire m0,loadwords,shift; datapath M1(product,m0,word1, word2,loadwords,shift,add, clock, reset); controller M2(loadwords,shift,add,ready,m0,start, clock, reset); endmodule

module controller(loadwords,shift,add,ready,m0,start, clock, reset); parameter lword=4; parameter lstate=4 output loadwords,shift,add,ready; input reset; input clock,start,m0; reg [lstate-1:0] state,nextstate; parameter sidle=0,s1=1,s2=2; parameter s3=3,s4=4,s5=5,s6=6,s7=7,s8=8; reg loadwords,shift,add; wire ready=((state==sidle)&&!reset)||(state==s8); always @(posedge clock or posedge reset) if(reset)state<=sidle; else state<=nextstate; always@(state or start or m0) begin

loadwords=0; shift=0; add=0; case(state) sidle: if(start) begin loadwords=1; nextstate=s1; end s1: if(m0) begin add=1; nextstate=s2; end else begin shift=1; nextstate=s3; end s2: begin shift=1; nextstate=s3; end s3: if(m0) begin add=1; nextstate=s4; end else begin shift=1; nextstate=s5; end s4: begin shift=1; nextstate=s5; end if(m0)

s5:

begin add=1; nextstate=s6; end else begin shift=1; nextstate=s7; end s6: begin shift=1; nextstate=s7; end if(m0) begin add=1; nextstate=s8; end else begin shift=1; nextstate=s8; end if(start) begin loadwords=1; nextstate=s1; end else nextstate=s8; default:nextstate=sidle; endcase end endmodule module datapath (product,m0,word1, word2,loadwords,shift,add, clock, reset); parameter lword=4; output [2*lword-1:0] product; output m0; input [lword-1:0] word1;

s7:

s8:

input [lword-1:0] word2; input clock,shift,add,loadwords; input reset; reg [2*lword-1:0] product,multiplicand; reg [lword-1:0] multiplier; wire m0=multiplier[0]; always @(posedge clock or posedge reset) if(reset)begin multiplier<=0;multiplicand<=0;product<=0;end else if(loadwords) begin multiplicand<=word1; multiplier<=word2; product<=0; end else if(shift) begin multiplier<=multiplier>>1; multiplicand<=multiplicand<<1; end else if(add)product<=product+multiplicand; endmodule

RESULT: