B Sravani K Tejaswi Sudheer

09B81A0491 09B81A04A6 09B81A0494

Internal Guide
assoc prof Mrs. Ester Rani

To design low power radix-2 FFT processor using MTCMOS technique.

The Fast Fourier Transform (FFT) is a critical block and widely used in digital signal Processing. With the advent of semiconductor processing technology in VLSI system, it has enabled the performance of FFT design to increase steadily and applied in portable application design. However, as semiconductor technologies move toward finer size and geometries FFT design has also faced challenges in power increment in the design.

Low threshold voltages

High device density

Decrease in oxide thickness

Leakage power

Leakage power has become a major concern for the CMOS circuits in deep sub-micron process. This project deals with technique which reduces the leakage power in fft processor. MTCMOS is a very effective technique to reduce the leakage current of circuits in the standby mode. The simple FFT processor is to be designed with MTCMOS to reduce its standby power.

 Low VT gates for speed High VT gates for low leakage

sleep

LOW VT LOGIC

HIGH VT Header and/or Footer

sleep

The leakage power consumptions of the individual blocks in FFT are to be compared with those of using MTCMOS. Comparisons are to be made between leakage power of FFT in fine grain FFT and CMOS FFT. The designing and comparisons are to be done using the 90nm CMOS technology

Real x(0) Img x(0) Real x(1) Img x(1)

Real X(0)

Img X(0)

RADIX 2

RADIX 2 MUL 1 MUL

Real X(2)

Img X(2)

Real x(2) Img x(2) Real x(3) Img x(3)

Real X(1) Img X(1)

RADIX-2
MUL 1

RADIX -2 MUL

Real X(4) Img X(4)

Cadence tools Design and comparisons are to be made using 90nm CMOS technology.

i/p Real x0
ADDER

O/p _x0 real

i/p Img x0
ADDER

o/p_x0 img

i/p Real x1

SUB

o/p real x1

i/p Img x1

SUB

o/p img x1

o/p_Real x1

MUL

o/p_x1 real o/p_Img x1 tiddle factor(W) Real img MUL MUL ADDE R o/p_x1 Img MUL SUB