4

C1147 10pF

D102

C1006 C1007
0.1uF 220pF

C1203
47uF

C1119
0.1uF

21

6V_TX:1

6V:1

22

6V_RX:1

L119

L120

C540
47uF

C541
1uF

C1181
0.1uF

C1183
47uF

C1182
1uF

C1184
0.1uF

C1186
47uF

C1185
1uF

3
AGND_RX:1

Front Panel Power

R101
3_3V:1
C1150

3_3V:1

DVDD_RX:1

L109

R103
8.06K

DVDD_TX:1

L108

F101
SMDXXX

J101

ALT Power

Vunreg:1
L118

F102
SMDXXX

L121

C1170

C1124 C1125
0.1uF 220pF

C1122 C1123 C1126

0.1uF 220pF 47uF

0.47uF
C1176

2
N

C1127 C1128 C1131

0.1uF 220pF 47uF

C1129 C1130
0.1uF 220pF

0.47uF

22uF CER X5R 6.3V

J102

1
1

NONE
R104

6V:1

21

C1004 C1005 C1008

0.1uF 220pF 47uF

24.9K

C1149 0.1uF

470pF

C1148

sync1

C1009 C1010 C1013

0.1uF 220pF 47uF

6V_CLK:1
L107

L122

20

C1011 C1012
0.1uF 220pF

6V:1

6V:1

19

8uH

18

L102

17

AVDD_RX:1

AGND_TX:1

19

16

SS/Track1

15

SHDN

Vout1

17

14

15

IND1

FB1

13

RT/SYNC

12

16

SW1

L101

LT3510A

11

Vc1

B360

18

L101A

PG1

3_3V:1

AVDD_TX:1

L103

PMEG4005ET

GND_EP

40.2K
R102

3_3V:1

6.5uH

Vin1

pg1

BST1

10

20

U14
C1001

Vunreg:1

C1003

4.7uF CER X5R 25V

C1173 0.1uF

0.47uF

3_3V:1

D101

Vunreg:1

C1002

100uF 30V

4.7uF CER X5R 25V

C1169

D103
PMEG4005ET
0.47uF

Vout2

7
14

SS/Track2

12

4K
R105
C1155 0.1uF

GND_EP
21

40.2K
R106

M1
2_5V:1

C1156
R107
8.06K

L112

D106
Vout1

2_5V:1

AGND

AGND

79

AGND

77

AGND

75

74

78

80
71

AGND

AVDD

AVDD

AGND

AGND

70

67

65

63

61

76
AVDD
66

AGND

AVDD
64

AGND

AVDD
AGND
62

43

36

26

18

10

51

AVDD
DGND_EP
81

DVDD
52

DGND

DVDD
44

DGND

DVDD
35

DGND

DVDD
25

DGND

DVDD
DGND
17

DGND

DVDD

CLKGND CLKVDD

D108

1_8V:1

3_3V:1

3
R131
C1208
0.1uF

1_2V:1

U23
1
2
3

190K

V+

OUT1

GND

OUT2

SET

MOD

ps_osc_1

ps_osc_2
R132

0
R133

LTC6908S6X
TSOT23

22uF CER X5R 6.3V

3_3V:1

Removed C1014C1021 b/c they dont fit

C1054C1055
0.1uF 0.1uF

NONE
R134

SSFM Modulation
OFF
1/64
1/32
1/16

C1168

2_5V_FPGA:1

C1053C1050C1051C1024
0.1uF 0.1uF 0.1uF 0.1uF

C1022C1023
0.1uF 0.1uF

NONE
R135
NONE

C1209
1000pF

Removed C1025, C1052, C1056, C1057 b/c they dont fit

2_5V_FPGA:1

1_2V:1

J104

2_5V:1

J105

1_8V:1

J106

J107

1_2V:1

6V:1

XC3SXX00FG456PWR

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCAUX

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

VCCINT

3_3V:1

A6

A17

F1

F22

U1

U22

AB6

G7

G8

G15

G16

H7

H16

R7

R16

T7

T8

T15

T16

C1207
47uF

C1206
47uF

C1205
47uF

AB17

U1

C1204
47uF

J103
GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

USRP2 Power

A1

A22

B2

B21

C9

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

K10

K11

K12

K13

K14

L9

L10

L11

L12

L13

L14

M9

M10

M11

M12

M13

M14

N9

N10

N11

N12

N13

N14

P3

P9

P10

P11

P12

P13

P14

P20

Y9

Y14

AA2

GND

AA21

GND

AB1

GND

AB22

GND

GND

FILE:

power.sch

PAGE
2

10

11

12

13

14

15

16

17

18

$Date$

TITLE

17

C1167 0.1uF

470pF

C1165 10pF

C1166

3_3V:1

LTC2284PWR

AGND_RX:1

1_2V:1

64

8uH

R114
8.06K

AGND_TX:1
pg3

10K

21

R112

GND_EP

GND

Vout2

40.2K
R113

AVdd

12

L115

SS/Track2

65

IND2

14

GND

SW2

PG2

FB2

AVdd

Vin2

LT3510B

10

10

Vc2

31

11

C1059C1058C1061C1060
0.1uF 0.1uF 0.1uF 0.1uF

sync2
1

B360

C1064C1065
0.1uF 0.1uF

C1092C1093 C1090C1091C1088C1089
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

pg1

R137
61.9K

C1164

13
E

R136
61.9K

ps_osc_2

1_8V:1

L115A

C1163
pg4

R139
61.9K

U2

U3

18

R138
61.9K

sync1

6.5uH

4.7uF CER X5R 25V

AVDD_TX:1

50

22uF CER X5R 6.3V

PMEG4005ET
0.47uF

AVDD_RX:1

DGND

C1072C1073C1070C1071 C1068C1069C1066C1067
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

D107

BST2

DVDD_RX:1

GND_EP

R110
8.06K

ps_osc_1

U15

C805
47uF

C1162

C803 C804
0.1uF 220pF

DGND

C1161 0.1uF

NONE
R111

Vunreg:1

C801 C802
0.1uF 220pF

AVdd

19

16.9K

21

40.2K
R109

C1137 C1138 C1141

0.1uF 220pF 47uF

R108

GND_EP

AVdd

SS/Track1

M10

DVdd

SHDN

M9

DVdd

15

17

M8

J108

C1139 C1140
0.1uF 220pF

DVDD_TX:1

FB1

M7

63

RT/SYNC

M6

32

16

LT3510A

M5

49

sync2

M4

IND1

4
8uH

2_5V_RAM:1

L801

Vc1

PG1

18

C1159 10pF

470pF

C1160

SW1

L114

Vin1

B360

pg3

20

BST1

L114A

C1157

2_5V:1

2_5V_SER:1

L111

M3

Power Supplies
6V
Daughterboard Power (<1A)
3.3VAN
LTC2284 (200mA), AD9777 (<500mA)
3.3VCLK
AD9510 (<500mA), CLOCK (88mA)
3.3VDIG
All IO (<2A)
2.5V
FPGA AUX (<100mA), Ethernet Core (<300mA), SERDES (<150mA)
1.8V
Ethernet Core (~500mA)
1.2V
FPGA Core (<2A)

C1132 C1133 C1136

0.1uF 220pF 47uF

U15
4.7uF CER X5R 25V

2_5V:1

C1158

6.5uH

C1134 C1135
0.1uF 220pF

PMEG4005ET

0.47uF

L110

2_5V:1

D105

Vunreg:1

C1142 C1143 C1146

0.1uF 220pF 47uF

M2

2_5V_ETH:1

22uF CER X5R 6.3V

C1144 C1145
0.1uF 220pF

2_5V:1

2_5V_FPGA:1

12

C1175

C1153 10pF

470pF

C1154

FB2

F103
500mA

R130

AD9777PWR

LT3510B

Vunreg:1

C1112 C1113 C1116

0.1uF 220pF 47uF

CLKGND CLKVDD

Vc2

C1114 C1115
0.1uF 220pF

C1179 0.1uF

PG2

13

8uH

4.7uF CER X5R 25V

IND2

FAN Power

L113

4
L113A

SW2

Vin2

pg2
L

BST2

10

DVDD_FPGA:1

L106
1

B360

6.5uH

C1151

D104

11

U14
4.7uF CER X5R 25V

3_3V:1

1_2V:1

C1152

Vunreg:1

19

REVISION:

OF

DRAWN BY:
20

$Revision$
$Author$

21

22

2012 Ettus Research. All rights reserved.

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

U1
XC3SXX00FG456IO7

G2

IO_L27P_7/VREF_7

IO_L17N_7

E4

io_tx_15

SCLK_TX_ADC

H1

IO_L28N_7/400NC

IO_L17P_7

D4

io_tx_14

SDO_TX_ADC

H2

IO_L28P_7/400NC

IO_L19P_7

D2

io_tx_13

SDI_TX_ADC

J4

IO_L29N_7/400NC

IO_L20N_7

F4

io_tx_12

SEN_TX_DAC

H4

IO_L29P_7/400NC

IO_L20P_7

E3

io_tx_11

SCLK_TX_DAC

J5

IO_L31N_7/400NC

IO_L21N_7

E1

io_tx_10

SDI_TX_DAC

J6

IO_L31P_7/400NC

IO_L21P_7

E2

io_tx_09

SDI

J1

IO_L32N_7/400NC

IO_L22N_7

G6

io_tx_08

LTC2284A

SDO

J2

IO_L32P_7/400NC

IO_L22P_7

F5

io_tx_07

SCLK

K5

IO_L33N_7/400NC

IO_L23N_7

F2

io_tx_06

SEN_CLK

K6

IO_L33P_7/400NC

IO_L23P_7

F3

io_tx_05

SEN_DAC

L1

IO_L40N_7/VREF_7

IO_L24N_7

H5

io_tx_04

IO_L24P_7

G5

io_tx_03

IO_L27N_7

G1

io_tx_02

IO_L34N_7

K3

io_tx_01

IO_L34P_7

K4

IO_L35N_7

K1

IO_L35P_7

K2

TX15_A

IO_L38N_7

L5

TX14_A

IO_L38P_7

L6

TX13_A

IO_L39N_7

L3

TX12_A

TX15_A

11

IO_L39P_7

L4

TX11_A

TX14_A

12

TX13_A

13

DB13_P1

TX12_A

14

DB12_P1

TX11_A

15

DB11_P1

TX10_A

16

DB10_P1

TX09_A

19

DB9_P1

TX08_A

20

DB8_P1

TX07_A

21

DB7_P1

TX06_A

22

DB6_P1

TX05_A

23

DB5_P1

TX04_A

24

DB4_P1

TX03_A

27

DB3_P1

TX02_A

28

DB2_P1

TX01_A

29

DB1_P1

TX00_A

30

DB0_P1

VCCO_7

L2

TX10_A

Removed C318, C320 b/c they dont fit

1

DVDD_FPGA:1

DVDD_FPGA:1

RXD

A3

TXD

C7

IO/VREF_0
IO/VREF_0

A10

IO

D9

IO

D10

TX07_A

TX09_A
TX08_A

LED1

IO/VREF_0

LED2

E5

IO/VREF_0/400NC

IO

F6

TX06_A

B7

IO_L19N_0/400NC

IO_L01N_0/VRP_0/DCI

B4

TX05_A

A7

IO_L19P_0/400NC

IO_L01P_0/VRN_0/DCI

A4

TX04_A

E8

IO_L22N_0/400NC

IO_L06N_0

D5

TX03_A

IO_L22P_0/400NC

IO_L06P_0

C5

TX02_A

IO_L31P_0/VREF_0

IO_L09N_0

B5

TX01_A

IO_L09P_0

A5

TX00_A

IO_L10N_0

E6

IO_L10P_0

D6

IO_L15N_0

C6

2.2K

SCL
LED0

R302

SDA

2.2K

C11

K3

slot=2
LED1
slot=2
LED2
R319
1K

LED4

D8

R314
1K

A3

slot=3
LED2

R313
1K
DVDD_FPGA:1

DVDD_FPGA:1

DVDD_FPGA:1

IO_L15P_0

B6

TX15_B

E7

TX14_B

IO_L16P_0

D7

TX13_B

IO_L24N_0

B8

TX12_B

IO_L24P_0

A8

TX11_B

IO_L25N_0

F9

TX10_B

IO_L25P_0

E9

TX09_B

IO_L27N_0

B9

TX08_B

IO_L27P_0

A9

TX07_B

IO_L28N_0

F10

TX06_B

IO_L28P_0

E10

TX05_B

IO_L29N_0

C10

TX04_B

IO_L29P_0

B10

TX03_B

IO_L30N_0

F11

TX02_B

IO_L30P_0

E11

TX01_B

D11

TX00_B

VCCO_0

VCCO_0

VCCO_0
F8

G9

VCCO_0

ADC01_B
ADC02_B

DB15_P1

IOUT1_P

73

DB14_P1

IOUT1_N

72

69

IOUTP_A

TX14_B

32

DB14_P2/ONEPORTCLK IOUT2_N

68

IOUTN_A

TX13_B

33

DB13_P2

TX12_B

34

DB12_P2

TX11_B

37

DB11_P2

TX10_B

38

DB10_P2

TX09_B

39

DB9_P2

TX08_B

40

DB8_P2

TX07_B

41

DB7_P2

TX06_B

42

DB6_P2

TX05_B

45

DB5_P2

TX04_B

46

DB4_P2

TX03_B

47

DB3_P2

TX02_B

48

DB2_P2

TX01_B

49
50

TX00_B

C303

1uF

C301
2.2uF

C306

DB1_P2

1uF C308
0.1uF
C307

DB0_P2

1uF

C305
2.2uF

A18

ADC04_B

F16

IO

IO_L19N_1/400NC

C16

ADC05_B

F17

IO

IO_L19P_1/400NC

D16

ADC06_B

C19

IO_L01N_1/VRP_1/DCI

IO_L22N_1/400NC

A16

ADC07_B

B20

IO_L01P_1/VRN_1/DCI

IO_L22P_1/400NC

B16

ADC08_B

B19

IO_L06P_1

IO_L31N_1/VREF_1

D12

ADC09_B

C18

IO_L09N_1

ADC10_B

D18

IO_L09P_1

ADC11_B

B18

IO_L10P_1

ADC12_B

D17

IO_L15N_1

ADC13_B

E17

IO_L15P_1

ADC_OVF_B

B17

IO_L16N_1

ADC_OE_B_N

C17

IO_L16P_1

ADC_PDN_B

27

ADC03_B

ADC_PDN_B

22

PDWN_B

D4_B

28

ADC04_B

D5_B

29

ADC05_B

D15

IO_L24N_1

D6_B

30

ADC06_B

E15

IO_L24P_1

D7_B

33

ADC07_B

B15

IO_L25N_1

D8_B

34

ADC08_B

A15

IO_L25P_1

D9_B

35

ADC09_B

D14

IO_L27N_1

D10_B

36

ADC10_B

D11_B

37

ADC11_B

D12_B

38

ADC12_B

D13_B

39

ADC13_B

OVF_B

40

ADC_OVF_B

VIN+_A

D0_A

41

ADC00_A

VIN_A

D1_A

42

ADC01_A

CLK_ADC

CLK_A

D2_A

43

ADC02_A

ADC_OE_A_N

58

OEB_A

D3_A

44

ADC03_A

ADC_PDN_A

59

PDWN_A

D4_A

45

ADC04_A

D5_A

46

ADC05_A

D6_A

47

ADC06_A

D7_A

48

ADC07_A

D8_A

51

ADC08_A

REFH_A

SENSE_A

62

REFH_A

SENSE_B

19

REFL_A

MUX

21

REFL_A

MODE

60

13

REFH_B

VCM_A

61

14

REFH_B

VCM_B

20

11

REFL_B

12

REFL_B

IO_L28N_1

ADC01_A

B14

IO_L28P_1

ADC02_A

C13

IO_L29N_1

ADC03_A

D13

IO_L29P_1

ADC04_A

A13

IO_L30N_1

ADC05_A

B13

IO_L30P_1

ADC06_A

E12

IO_L31P_1

Removed C323325 b/c they dont fit

U1

XC3SXX00FG456IO2

D9_A

52

ADC09_A

ADC07_A

C22

IO

IO_L17P_2/VREF_2

D22

SEN_RX_DB

53

ADC10_A

ADC08_A

C20

IO_L01N_2/VRP_2/DCI

IO_L23N_2/VREF_2

F19

SCLK_RX_DB

D11_A

54

ADC11_A

ADC09_A

C21

IO_L01P_2/VRN_2/DCI

IO_L26N_2/400NC

G20

SDO_RX_DB

D12_A

55

ADC12_A

ADC10_A

D20

IO_L16N_2

IO_L26P_2/400NC

H19

SDI_RX_DB

D13_A

56

ADC13_A

ADC11_A

D19

IO_L16P_2

IO_L28N_2/400NC

H18

SEN_RX_ADC

OVF_A

57

ADC12_A

D21

IO_L17N_2

IO_L28P_2/400NC

J17

SCLK_RX_ADC

ADC13_A

E18

IO_L19N_2

IO_L29N_2/400NC

H21

SDO_RX_ADC

ADC_OVF_A

F18

IO_L19P_2

IO_L29P_2/400NC

H22

SDI_RX_ADC

ADC_OE_A_N

E19

IO_L20N_2

IO_L31N_2/400NC

J18

SEN_RX_DAC

ADC_PDN_A

E20

IO_L20P_2

IO_L31P_2/400NC

J19

SCLK_RX_DAC
SDI_RX_DAC

ADC_OVF_A

0
R305
R317
1K

2V Range
0
R304

R306
NONE

R318
2K

MODE ==> 2/3Vdd = 2s Comp, w/DCS

MUX ==> A> A, B > B
SENSE ==> 1 Vpp or 2 Vpp Range

C309
2.2uF

C322C321
0.1uF0.1uF

D10_A

U2

IO_L27P_1

A14

DVDD_FPGA:1

VINN_B

E14

ADC00_A

U2

VINP_B

LTC2284CTRL

1uF C304
0.1uF

IO_L10N_1/VREF_1

D3_B

AVDD_RX:1

C302

IO

D2_B

CLK_B

U3
IOUT2_P

A19

F13

OEB_B

LTC2284A

DB15_P2/IQSEL

ADC03_B

23

IOUTP_B

31

F14

IO_L06N_1/VREF_1

ADC_OE_B_N

IOUTN_B

TX15_B

IO/VREF_1/400NC

IO

26

U3

AD9777CH2

DAC_LOCK

IO_L16N_0

IO_L31N_0

ADC00_B

25

IO

1V Range
R307
NONE

C310
2.2uF

AGND_RX:1

C351 C350
1uF 1uF

E21

IO_L21N_2

IO_L32N_2/400NC

J21

io_rx_15

E22

IO_L21P_2

IO_L32P_2/400NC

J22

io_rx_14

G17

IO_L22N_2

IO_L33N_2/400NC

K17

io_rx_13

G18

IO_L22P_2

IO_L33P_2/400NC

K18

io_rx_12

G19

IO_L23P_2

IO_L34N_2/VREF_2

K19

io_rx_11

F20

IO_L24N_2

IO_L40P_2/VREF_2

L22

io_rx_10

F21

IO_L24P_2

io_rx_09

G21

IO_L27N_2

io_rx_08

G22

IO_L27P_2

io_rx_07

K20

IO_L34P_2

io_rx_06

K21

IO_L35N_2

io_rx_05

K22

IO_L35P_2

io_rx_04

L17

IO_L38N_2

io_rx_03

L18

IO_L38P_2

io_rx_02

L19

IO_L39N_2

io_rx_01

L20

IO_L39P_2

io_rx_00

L21

IO_L40N_2

H17

G10

DVDD_FPGA:1

G11

VCCO_0

24

D1_B

AVDD_RX:1

D0_B

VIN_B

F12

C8

R301

A2

A2

IO

F7

K2

DVDD_FPGA:1

K2

DVDD_FPGA:1

K1

U1
XC3SXX00FG456IO0

LED1
slot=3

K3

LED3

R316

A1

LED2
slot=1

A3

330

1K
R311

C319
0.1uF

R315

330

1K
R312

C317C316
0.1uF0.1uF

VIN+_B

15

PPS_IN

J305

16

VINN_A

io_tx_00

H3

VCCO_7

VCCO_7

J7

IO_L40P_7

H6

DVDD_FPGA:1

K7

L7

VCCO_7

VCCO_7

VINP_A

CLK_ADC

AD9777CH1

U2

E16

ADC02_B

VCCO_1

SEN_TX_ADC

ADC01_B

VCCO_1

clk_en1

G14

clk_en0

D1

G13

C4

IO_L16N_7

E13

DVDD_FPGA:1

VCCO_2

IO_L01P_7/VRN_7/DCI

IO_L26P_7/400NC

P
IO/VREF_1

L16

IO_L26N_7/400NC

G4

IO

VCCO_1

G3

SDI_TX_DB

A12

VCCO_1

SDO_TX_DB

ADC00_B

G12

clk_sel0

VCCO_2

C3

K16

IO_L01N_7/VRP_7/DCI

VCCO_1

IO_L19N_7/VREF_7

F15

D3

C15

SCLK_TX_DB

XC3SXX00FG456IO1

VCCO_2

clk_sel1

VCCO_2

C2

J16

IO

VCCO_2

IO_L16P_7/VREF_7

H20

C1

AGND_RX:1

U1

SEN_TX_DB

AGND_RX:1

Removed C312, C314, C315 b/c they dont fit

C311C313
0.1uF0.1uF

USRP2 FPGA and CODECs

C327C326C328C329C330
0.1uF0.1uF0.1uF0.1uF0.1uF

FILE:

fpga.sch

10

11

12

13

14

15

16

17

18

19

20

$Revision$

REVISION:

PAGE
1

$Date$

TITLE

21

OF

DRAWN BY:
22

$Author$
23

24

2012 Ettus Research. All rights reserved.

10

11

12

13

14

15

16

17

GND

Done/TDO

TDO_PORT
TDI_PORT

GND

Din/TDI

10

11

GND

NC/NC

12

13

GND

INIT/NC

14

R22310

TDO_FPGA

TDO_PORT

TDI_PORT

R224NONE
TDI_FPGA

TDO_FPGA

R225NONE
TDI_CPLD

TCK

1K
R202

U10

POR

42

IO_B1MC8

IO_B3MC9

cpld_detached

43

IO_B1MC9/GCK1

IO_B3MC11

12

cpld_misc

44

IO_B1MC11/GCK2

IO_B3MC14

13

cpld_clk
cpld_start

IO_B1MC17

IO_B3MC17

16

cpld_done

29

IO_B2MC2

IO_B4MC2

19

sd_prot

30

IO_B2MC5

IO_B4MC5

20

sd_cs_25

31

IO_B2MC6

IO_B4MC8

21

sd_din_25

32

IO_B2MC8

IO_B4MC11

22

sd_clk_25

33

IO_B2MC9/GSR

IO_B4MC14

23

34

IO_B2MC11/GTS2

IO_B4MC15

27

36

IO_B2MC14/GTS1

IO_B4MC17

28

37

CD_DAT[3]/NC/nCS

sd_din_33

CMD/CMD/Din

Vss1

DVDD_FPGA:1

Vss2

IO_B2MC15

DAT[0]/DAT[0]/Dout

IO_B2MC17

DAT[1]/NC/NC

DAT[2]/NC/NC

sd_clk_33

TMS

2_5V_FPGA:1
prot_det_com

11

protect

12

detect

10

sd_prot

sd_det

Pin Defs:
SD/MMC/SPI

13

10

TMS

11

TCK

TCK

CLK

R212

U31
SN74AUP1T57

sd_cs_33
sd_din_25

DVDD_FPGA:1

GND

Vcc

U32
SN74AUP1T57

DVDD_FPGA:1

sd_cs_25

sd_cs_33

Slave Serial 2.5V

Bank 4 must be 2.5V

J201
1

Vdd

TDI

38

TDO_CPLD 24 TDO

J204

10K

cpld_mode

R227

18

C202 C204 C205

0.1uF 0.1uF 0.1uF

10K

IO_B3MC16

R228

IO_B1MC15

cpld_clk

C203
0.1uF

17

Y4

AA3

AA14

AB14

ser_rx_en

cpld_start

cpld_mode

cpld_done

ser_enable

cpld_misc

IO_B3MC15

sd_det

U10

25

IO_L01P_5/CS_B

IO_L01N_5/RDWR_B

XC3SXX00FG456CFG

CCLK

DONE

IO_L27P_4/D1

IO_L27N_4/DIN/D0

AB9

AA9

U12

V12

W12

W11

Y12

cpld_detached

IO_B1MC14/GCK3

14

10

ser_prbsen
cpld_din
2_5V_FPGA:1
4.7K

cpld_init_b

ser_loopen

LED1
slot=1

K1

AA22

AB21

M0

IO_L28N_5/D6

IO_L28P_5/D7

IO_L30N_4/D2

IO_L30P_4/D3

IO_L31N_4/INIT_B

IO_L31N_5/D4

V11

IO_L31P_4/DOUT/BUSY

IO_L31P_5/D5

HSWAP_EN

M1

M2

PROG_B

B3

AB2

AA1

A2

AB3

U1

D202

XC9572VQ44PWR

GND

IO_B3MC8

VccINT

IO_B1MC6

R210

DVDD_FPGA:1

15

41

D201

35

CLK_25MHZ_EN

GND

GND

IO_B3MC5

VccINT

IO_B1MC5

C201
NONE

SCL
SDA

VccIO

40

7
6
5

26

CLK_25MHZ

A0
A1
n/c
A2 SCL
SDA

24LC024/SN
DVDD_FPGA:8
GND:4
2_5V_FPGA:1

1K
R214

A1

R213

IO_B3MC2

24Cxx

R211

IO_B1MC2

TDI_CPLD

330

39

POR

2_5V_FPGA:1

1K
R201

XC9572VQ44IO
0

R203
10K

U11
1
2
3

2_5V_FPGA:1

pg1

2_5V_FPGA:1

R226NONE
TDO_PORT

TDO_CPLD

WDI

MAX6749KA+T
2_5V_FPGA:8
GND:4

U1

XC3SXX00FG456JTAG

R234

A21

WDS

U33
SN74AUP1T57
Y

sd_din_33
sd_clk_25

sd_clk_33
B

GND

TCK

TDI

WDI

SRT

Vcc

B1

SWT

CCLK/TCK

TCK

0.1uF

GND

TDI_FPGA

C207

2_5V_FPGA:1

GND

TDO_CPLD

C206

POR

GND

TMS

8200pF

14

TDO

RESETn

DVDD_FPGA:1

PROG/TMS

TDI_FPGA

B22

RSTin/MRn

GND

GND

R22210

TDO_FPGA

Vcc

TDI_CPLD

U24

R233 100K

Vref/Vref

TMS

10K

GND

A20

R232 NONE

NONE

R22110

TDI_PORT

TMS

R206

J203
2_5V_FPGA:1
XILPLATCABLE

NONE

R231 130K

R229

Both JTAG ports are 2.5V

DVDD_FPGA:1

2_5V_FPGA:1

USRP2 Configuration

FILE:

config.sch

PAGE
1

10

11

12

13

$Date$

TITLE

14

REVISION:

OF

DRAWN BY:
15

$Revision$
$Author$
16

17
2012 Ettus Research. All rights reserved.

11

SDA

SCL

10
Ref

GND

CLR

17

C402

L402

SDI_TX_DAC
4

Vdd

16

AGND_TX:1

GND

SDI_TX_ADC

Din

SCLK

Vin0

CS

Vdd

SCLK_TX_ADC
SDO_TX_ADC
SEN_TX_ADC

AVDD_TX:1

AGND_TX:1

15

AD79X2MSOP
Dout 1
5 Vin1

AGND_TX:1

Vref

64

62

60

58

56

54

52

50

48

46

44

36

42

34

40

SEN_TX_DB

clock_tx_n

U6 7

AVDD_TX:1
AGND_TX:1

14

AVDD_TX:1

38

SDI_TX_DB

32

28

26

24

22

20

18

16

14

12

10

30

clock_tx_p

C408

SDO_TX_DB

DVDD_TX:1

0.1uF

AGND_TX:1

U4

13

AVDD_TX:1

AGND_TX:1
SCLK_TX_DB

6V_TX:1

0.1uF

10uF
I2C Address

OUTA

C401

C407

SCLK

AVDD_TX:1

LDAC

12

AGND_TX:1
AVDD_TX:1

0.1uF

10

AD56x3

SEN_TX_DAC

Din

SYNC

OUTB

SCLK_TX_DAC

J401

63

AGND_TX:1

IOUTN_A

IOUTP_A

VINP_A

VINN_A

VINN_B

AVDD_RX:1

61

59

57

55

53

VINP_B

io_rx_00

io_rx_01

io_rx_02

io_rx_03

io_rx_04

io_rx_05

io_rx_06

io_rx_07

io_rx_08

io_rx_09

io_rx_10

io_rx_11

io_rx_12

io_rx_13

AVDD_RX:1

AGND_TX:1
AGND_TX:1

IOUTP_B

IOUTN_B

AVDD_TX:1

51

49

47

AGND_TX:1

AVDD_TX:1

io_tx_00

io_tx_01

io_tx_02

io_tx_03

io_tx_04

io_tx_05

io_tx_06

io_tx_07

io_tx_08

io_tx_09

io_tx_10

io_tx_11

io_tx_12

io_tx_13

io_rx_14

io_rx_15

io_tx_14

io_tx_15

45

43

41

39

37

33

35

31

29

27

25

23

21

19

17

15

13

11

AGND_TX:1

AGND_RX:1 AGND_RX:1 AGND_RX:1

AGND_RX:1 AGND_RX:1
64

61

63

59

62

60

55

57

53

58

56

51

SEN_RX_DB

54

37

SDI_RX_DB

52

38

33

35

SDO_RX_DB

49

36

31

SCLK_RX_DB

50

34

29

47

32

27

48

30

25

45

28

23

46

26

21

43

24

19

44

22

17

41

20

15

39

18

13

42

16

11

40

14

12

10

SDA

SCL

DVDD_RX:1

clock_rx_n

6V_RX:1

clock_rx_p

J402

DVDD_RX:1

Vref

AGND_RX:1 AGND_RX:1

AGND_RX:1

AVDD_RX:1

AVDD_RX:1
AVDD_RX:1

U7

C404

I2C Address

AGND_RX:1

Vdd

Vin0

CS

Vin1

Dout

SDO_RX_ADC

Din

SCLK_RX_ADC

AD79X2MSOP
SDI_RX_ADC

0.1uF

SCLK

SEN_RX_ADC

GND

AVDD_RX:1

C403

C405
10uF

SCLK_RX_DAC

SEN_RX_DAC

SDI_RX_DAC

AGND_RX:1

SCLK

Vdd

OUTA

SYNC

0.1uF

OUTB

0.1uF

Din

10

AVDD_RX:1
C406

LDAC

CLR

Ref

AVDD_RX:1
L401

AD56x3

GND

AGND_RX:1

U5

AGND_RX:1

USRP2 Daughterboad Interface

FILE:

AGND_RX:1
1

AGND_RX:1
10

dboard.sch

PAGE
11

12

13

$Date$

TITLE

14

REVISION:

OF

DRAWN BY:
15

$Revision$
$Author$
16

17
2012 Ettus Research. All rights reserved.

10

11

12

13

6V_CLK:1

DVDD_CLK:1

SEL1

EN0

16

clk_en0

DVDD_CLK:1

clk_sel0

SEL0

EN1

15

clk_en1

R517

IN0_P

OUT0_P

14

IN0_N

OUT0_N

13

clk_exp_in_p

IN1_P

OUT1_P

11

clk_exp_in_n

OUT1_N

10

49.9
R537
R536

4
R527

R529
10K

25

17.4K
DVDD_CLK:1 R525
100

25

5, 2

R503
100

clk_sel1

IN1_N
NC
Vcc

NC

R526
10K

100

R524

0.1uF

1M

REFIN_N

C523
1.2uF

CLK1_P

0.1uF

C532

15

CLK1_N

10

CLK2_P

11

CLK2_N

0.1uF

C526

R504

200

R507

200
DVDD_CLK:1

R509
VCTCXO

DVDD_CLK:1

Vcc

GND

EN

Vin

Vout

C544

C1117 C1118 C1121

0.1uF 220pF 47uF

DVDD_CLK:1

1uF

C542
0.1uF

C524

testclk_n

OUT1_P

54

R542

200
R543
200

R581
R582

OUT

OUT2_P

ENB/TUNE

OUT2_N

34

OUT3_P

29

CLK_DAC_P

OUT3_N

28

CLK_DAC_N

DVDD_FPGA:1

J504

1.3K

825

R515

R514

XC3SXX00FG456CLK

AD9510CTRL

CLK_STATUS
GMII_RX_CLK
ser_rx_clk
CLK_FPGA_P

R530 83

R531

CLK_DAC_P

CLK_P

LPF

127

R532 83

R533

CLK_DAC_N

CLK_N

DATACLK/PLL_LOCK

57

RESET

FSADJ1

60

SDO

53

SDO

FSADJ2

59

SDI

54

SDIO

REFIO

58

18

SDI

19

SDO

20

SDO

SCLK

55

SEN_CLK

21

CSB

SEN_DAC

56

SCLK
SDIO

825

R513

R512

CLK_FUNC
CLK_TO_MAC

C535

127

SCLK

B11

CLK_FPGA_N

R580

U3
AD9777CTRL

DVDD_TX:1

U9

OUT0_N

200

35

DVDD_TX:1

STATUS

testclk_p

57

53

C534
0.1uF

R511

17

58

OUT1_N

1.3K

CLK_STATUS

OUT0_P

DVDD_CLK:1

FUNCTION

C545
0.1uF

U9
AD9510OUTA

TXDboard CMOS/LVDS
RXDboard CMOS/LVDS
ADC CMOS

0.12uF

U8

J503

Outputs to:
DAC PECL
FPGA PECL
Expansion PECL

100

16

R541
10K

C546
0.1uF

33uF

CLK_FUNC

PPS_IN

C580
0.1uF
0.1uF
C581

200

CLK_FPGA_P
CLK_FPGA_N

LP38692MP

NC GND

1K

U22

6V_CLK:1

C525

C527 0.1uF

R508

VccA

390

12K

200

2
14

17
L

3kHz BW, 45 deg Phase margin

with 5 MHz compare freq and 3mA CP current

CP

VccY

DVDD_FPGA:1

C539
100pF

REFIN_P

C531

200

R519

R518

0.1uF

C537

J505

DVDD_CLK:1

1M

AD9510PLL U9
R523
100

R521
49.9

Bias VCXO to 1.65V when no reference

16

DVDD_CLK:1

2345

R535

R505

T501

GND

C533

2345

15

ADG3301

EN

U18
DS90CP22

0.1uF

R522 1K

12

J502

R528

17.4K

J501
K

14

U17

GND

SCLK
CSB

IO_L32N_1/GCLK5

AA12

IO_L32N_4/GCLK1
IO_L32N_5/GCLK3

A11

IO_L32P_0/GCLK6

C12

IO_L32P_1/GCLK4

AB12

IO_L32P_4/GCLK0

Y11

IO_L32P_5/GCLK2

U20
3
4

OUT4_P

47

clkadc_p

OUT4_N

46

clkadc_n
clk_exp_out_p

OUT5_P

43

OUT5_N

42

OUT6_P

39

R520

OUT6_N

38

R506

OUT7_P

25 R570

OUT7_N

24

clk_exp_out_n
25
25

25

DS90LT012AH
5

CLK_ADC

AVDD_RX:1
AGND_RX:2
F

clock_tx_p
clock_tx_n

25

NONE
C536

R571

clock_rx_p
clock_rx_n
E

NONE
DAC_LOCK

AVDD_RX:1

R516
NONE

C543
0.1uF
R510
950 1%

C528
0.1uF

AGND_RX:1

AGND_TX:1

IO_L32N_0/GCLK7

B12

AA11

U9
AD9510OUTB

U1

DVDD_CLK:1

DVDD_CLK:1

13

23

26

30

31

33

36

37

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND_EP

AD9510PWR

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

VS

12

22

27

32

49

50

55

62

65

R502
5.1K 1%

40

41

44

45

48

51

52

56

59

VS

Vcp

VS

63

R501
4.12K 1%

60

61

C521 C522 C519 C520 C513 C514 C511 C512 C509 C510 C507 C508 C505 C506 C503 C504 C501 C502 C517 C518 C515 C516
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF

RSET
CPRSET

64

U9

USRP2 Clocking
A

FILE:

clock.sch

PAGE
1

10

11

12

13

$Date$

TITLE

14

REVISION:

OF

$Rev$

DRAWN BY:
15

$Author$

16

17
2012 Ettus Research. All rights reserved.

3
U1

10

11

12

13

14

15

16

17

XC3SXX00FG456IO5

Y5

IO_L09N_5

IO_L27N_5/VREF_5

W9

ser_r09

ser_t05

W5

IO_L09P_5

IO_L29P_5/VREF_5

W10

ser_r10

ser_t06

AB5

IO_L10N_5/VRP_5/DCI

ser_t07

AA5

IO_L10P_5/VRN_5/DCI

ser_t08

W6

IO_L15N_5

ser_t09

V6

IO_L15P_5

ser_t10

AA6

IO_L16N_5

ser_t11

Y6

IO_L16P_5

ser_t12

W8

IO_L29N_5

ser_r00

AB10

IO_L30N_5

ser_r01

AA10

IO_L30P_5

T9

2_5V_FPGA:1

VCCO_5

Y10

ser_rkmsb

VCCO_5

IO_L27P_5

Y8

IO_L25P_5

V9

VCCO_5

ser_t15

AA8

U8

IO_L25N_5

VCCO_5

IO_L24P_5

AB8

T11

V8

ser_t14

VCCO_5

ser_t13

ser_rklsb
G

IO_L24N_5

C724C723C725C726C727
0.1uF0.1uF0.1uF0.1uF0.1uF
J301

CLK1

debug_31

A3[7]

A1[7]

debug_15

debug_30

A3[6]

A1[6]

10

debug_14

debug_29

11

A3[5]

A1[5]

12

debug_13

debug_28

13

A3[4]

A1[4]

14

debug_12

debug_27

15

A3[3]

A1[3]

16

debug_11

CLK0

debug_clk1

A2[6]

A0[6]

26

debug_06

debug_21

27

A2[5]

A0[5]

28

debug_05

debug_20

29

A2[4]

A0[4]

30

debug_04

debug_19

31

A2[3]

A0[3]

32

debug_03

debug_07
debug_06

ser_rklsb

29

RKLSB/RX_ER/PRBS_PASS

DINRXP

54

ser_rkmsb

30

RKMSB/RX_DV/LOS

TXD0

ser_r00

51

RXD0

63

TXD1

ser_r01

50

RXD1

64

TXD2

ser_r02

49

RXD2

ser_t03

TXD3

ser_r03

47

RXD3

ser_t04

TXD4

ser_r04

46

RXD4

ser_t05

TXD5

ser_r05

45

RXD5

ser_t06

TXD6

ser_r06

44

RXD6

ser_t07

TXD7

ser_r07

42

RXD7

ser_t08

10

TXD8

ser_r08

40

RXD8

ser_t09

11

TXD9

ser_r09

39

RXD9

ser_t10

12

TXD10

ser_r10

37

RXD10

ser_tkmsb

20

TKMSB/TX_EN

ser_t00

62

ser_t01
ser_t02

C709

0.01uF

ser_out_p

debug_29

V5

debug_28

U5

IO_L19P_6

IO_L29P_6/400NC

R1

exp_pps_in_n

V4

IO_L20N_6

IO_L31N_6/400NC

P5

debug_05

exp_pps_in_p

V3

IO_L20P_6

IO_L31P_6/400NC

P4

debug_04

exp_pps_out_n

V2

IO_L21N_6

IO_L32N_6/400NC

P2

debug_03

exp_pps_out_p

V1

IO_L21P_6

IO_L32P_6/400NC

P1

debug_02

debug_27

T6

IO_L22N_6

IO_L33N_6/400NC

N6

debug_01

debug_26

T5

IO_L22P_6

IO_L33P_6/400NC

N5

debug_00

debug_25

U4

IO_L23N_6

IO_L34N_6/VREF_6

N4

debug_24

T4

IO_L23P_6

IO_L40P_6/VREF_6

M1

debug_23

U2

IO_L24P_6

ser_t11

14

TXD11

debug_22

T2

ser_r11

36

IO_L27N_6

RXD11

ser_t12

15

TXD12

debug_21

T1

35

IO_L27P_6

ser_r12

RXD12

ser_t13

16

TXD13

debug_20

N3

34

IO_L34P_6

ser_r13

RXD13

ser_t14

17

TXD14

debug_19

N2

IO_L35N_6

ser_r14

32

RXD14

ser_t15

19

TXD15

debug_18

N1

IO_L35P_6

ser_r15

31

RXD15

debug_17

M6

41

IO_L38N_6

ser_rx_clk

debug_16

M5

IO_L38P_6

debug_15

M4

IO_L39N_6

debug_14

M3

IO_L39P_6

debug_13

M2

IO_L40N_6

2_5V_FPGA:1

debug_clk0
debug_clk1

2_5V_FPGA:1

L707

C711

ser_enable
2_5V_SER_AN:1

ser_loopen
ser_prbsen
200

R713

24
21

LOOPEN

26

PRBSEN

56

Rref

27

TESTEN

ser_in_p
ser_in_n

C730

0.1uF

clk_exp_in_n

exp_pps_in_p
C713C714C715C716C717

R715
100

0.1uF
0.1uF

GND

exp_pps_in_n

TX0_P

B2

ser_out_p

A3

RX0_N

TX0_N

B3

ser_out_n

A4

GND

GND

B4

A5

RX1_P

TX1_P

B5

A6

RX1_N

TX1_N

B6

A7

GND

A8

RX2_P
RX2_N

GND

B7

TX2_P

B8

TX2_N

B9

C731

0.1uF

GND

B10

C734

0.1uF A11
RX3_P

TX3_P

B11

A12

TX3_N

B12

GND

B13

C735

0.1uF

A10

A13

GND

RX3_N
GND

0.1uF

C743

0.1uF

C744

0.1uF

C728
clk_exp_out_p

exp_user_out_p
exp_user_out_n

0.1uF

clk_exp_out_n
C729

0.1uF

C732

0.1uF

C733

R721
100

R730
100

exp_pps_out_p
exp_pps_out_n

R714
100

LVDS

LVDS
B

U13

USRP2 Expansion

CML

13

R717
10K

18

ser_in_p

RX_CLK

RX0_P

10

11

12

13

$Date$
expansion.sch

PAGE
4

0.01uF

B1

FILE:
3

C707

C708
ser_in_n

TITLE

0.01uF

GND

A9

0.01uF
0.01uF
0.01uF
0.01uF
0.01uF

GND

NC

R716
10K

0.01uF

ENABLE

GND

A2

exp_user_in_n
C741
clk_exp_in_p

C712

A1

C742
exp_user_in_p
2_5V_SER:1

0.01uF

R710

J707
IPASSSASX4

2_5V_SER_AN:1
C719C718C720C721C722
0.1uF0.1uF0.1uF0.1uF0.1uF

800

J707

28

NC

R2

53

GND

NC

IO_L29N_6/400NC

60

C710
ser_out_n

DINRXN

33

debug_00

IO_L19N_6

debug_08

DOUTTXP

0.01uF

LCKREFN

GND

38

P6

59

U13
TLK2XX1RX
25

TKLSB/TX_ER

43

A0[0]
NC

IO_L28P_6/400NC

DOUTTXN

R709

ser_rx_en

22

GND

A2[0]

GND

IO_L17N_6

52

37

W2

GTX_CLK

ser_tklsb

GND

debug_16

43

debug_30

58

debug_01

GND

debug_09

GNDA

debug_17

42

R5

61

debug_02

36

GND

IO_L28N_6/400NC

GNDA

34

A0[1]
GND

IO_L16P_6

65

A0[2]

A2[1]

41

W3

GNDA

A2[2]

35

GND

debug_31

GND_EP

33

40

debug_10

debug_08

debug_18

39

ser_r14

ser_tx_clk

TLK2XX1PWR

debug_07

25

debug_11

R4

VDD

A0[7]

debug_22

T3

IO_L26P_6/400NC

U13

A2[7]

24

A3[0]

IO_L26N_6/400NC

debug_23

23

IO_L01P_6/VRN_6/DCI
IO_L16N_6

VDD

A1[0]

22

Y2
W4

VDD

debug_24

21

ser_r13

TLK2XX1TX

23

debug_09

debug_12

VDD

debug_10

20

U3

38

18

A1[1]

IO_L24N_6/VREF_6

VDD

A1[2]

A3[1]

IO_L01N_6/VRP_6/DCI

48

A3[2]

19

Y3

55

17

debug_25

ser_r12

VDDA

debug_26

ser_r15

VDDA

W1

57

debug_clk0

IO_L17P_6/VREF_6

R722
100

MICTOR43LA

IO

GND

ser_t04

ser_r11

GND

ser_r08

37

AA7

GND

IO_L22P_5/400NC

36

IO_L06P_5

GND

AA4

35

ser_t03

XC3SXX00FG456IO6
Y1

GND

ser_r07

34

AB7

GND

IO_L22N_5/400NC

33

IO_L06N_5

GND

AB4

32

ser_t02

200

U1

GND

ser_r06

31

W7

GND

IO_L19P_5/VREF_5/400NC

30

IO

29

V10

IPASSSASX4SHLD

ser_t01

2_5V_SER:1

2_5V_SER_AN:1

VCCO_6

ser_r05

VCCO_6

ser_t00

R6

ser_r04

Y7

R3

AB11

IO_L19N_5/400NC

VCCO_6

IO/VREF_5

IO

VCCO_6

IO

V7

P7

U11

VCCO_6

ser_tkmsb

N7

ser_r03

M7

U6

R708

IO/VREF_5

49.9

IO

R707

U10

49.9

ser_r02

ser_tklsb

R712

U9

49.9

IO/400NC

R711

IO

49.9

U7

ser_tx_clk

T10

14

REVISION:
OF

DRAWN BY:
15

$Revision$
$Author$
16

17
2012 Ettus Research. All rights reserved.

10

11

12

13

14

15

16

17

U1
XC3SXX00FG456IO4

GMII_CRS

U17

IO

IO/VREF_4

Y16

MDIO

GMII_TX_CLK

W13

IO

IO/VREF_4

AB13

PHY_INTn

GMII_TXD0

W14

IO

IO_L05N_4/400NC

AA19

PHY_RESET

GMII_TXD1

AA20

IO_L01N_4/VRP_4/DCI

IO_L05P_4/400NC

AB19

ETH_LED

GMII_TXD2

AB20

IO_L01P_4/VRN_4/DCI

IO_L06N_4/VREF_4

W18

POR

CHASSIS_GND:1

R608 49.9

R607 49.9

R646 NONE

R606 49.9

R605 49.9

R604 49.9

R603 49.9

MDC

J601
BEL 08261X1T23F

GMII_TXD3

Y18

IO_L06P_4

IO_L19N_4/400NC

AA16

GMII_RX_ER

108

11

MDIA_P

GMII_TXD4

AA18

IO_L09N_4

IO_L19P_4/400NC

AB16

GMII_RX_DV

MDIA_N

109

10

MDIA_N

GMII_TXD5

AB18

IO_L09P_4

IO_L22N_4/VREF_4/400NC

V15

MDIB_P

114

MDIB_P

GMII_TXD6

V17

IO_L10N_4

IO_L22P_4/400NC

W15

MDIB_N

115

MDIB_N

GMII_TXD7

W17

IO_L10P_4

MDIC_P

120

MDIC_P

GMII_TX_EN

Y17

IO_L15N_4

MDIC_N

121

MDIC_N

GMII_GTX_CLKAA17 IO_L15P_4

MDID_P

126

MDID_P

GMII_TX_ER

MDID_N

127

0.1uF

C603

C604
R610 330

ACT_LED
ETH_LED

LED Polarities!!!
Section 5.9

R659 0
R660 0
R609 330

SHIELD/GND

SG2

GMII_RXD0

AA15

IO_L24N_4

GMII_RXD1

AB15

IO_L24P_4

GMII_RXD2

U14

IO_L25N_4

MCTB

MCTC

MCTD

GMII_RXD3

V14

IO_L25P_4

13

LED1(Yellow Cath)

GMII_RXD4

U13

IO_L28N_4

14

LED1(Yellow Anode)

15

V13

LED2(Grn Cath/Org An)

GMII_RXD5

IO_L28P_4

16

LED2(Grn An/Org Cath)

GMII_RXD6

Y13

IO_L29N_4

GMII_RXD7

AA13

IO_L29P_4

CHASSIS_GND:1

2_5V_FPGA:1

U12
DP83865JTAG
R611

2K

32

TRST

31

TDI

28

TDO

27

TMS

24

VCCO_4

0.1uF

MCTA

VCCO_4

12

WDI

C361
0.1uF
L603

VCTCXO
4

Vcc

GND

ENB/TUNE

TCK

R615
1_8VA:1

2_5V_ETH_A:1

C605

22uF CER X5R 6.3V

1_8VA:1

C614C615C616C617C618 C636C637C638C639C632C633C634C635C629C630C631C626
0.1uF0.1uF0.1uF0.1uF0.1uF 0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF

1_8V:1

C627C628
0.1uF0.1uF

2_5V_ETH:1

15

21

29

37

42

53

58

69

77

83

90

11

19

25

35

48

63

73

92

101

96

103

105

111

117

123

98

100

2K

R639

R629
R628
R631
R630
R633
R632
R635
R634
R636
R638

76

CRS/RGMII_SEL0

TXD1

75

TX_CLK/RGMII_SEL1

TXD2

72

57

RX_CLK

TXD3

71

56

RXD0

TXD4

68

55

RXD1

TXD5

67

52

RXD2

TXD6

66

51

RXD3

TXD7

65

RXD4

TX_EN/TX_EN\ER

62

47

RXD5

GTX_CLK/TCK

79

46

RXD6

TX_ER

61

45

RXD7

41

RX_ER/RXDV\ER

44

RX_DV/RCK

60

50

R637

10

R671

COL/CLK_MACFREQ

1V8_AVdd1

1V8_AVdd1

1V8_AVdd1

2V5_Avdd2

2V5_Avdd1

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

Core_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

IO_Vdd

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss

Vss
5

12

16

20

22

26

30

36

38

43

49

54

59

64

70

74

78

82

91

93

97

99

2K

104

106

107

110

112

113

116

118

119

122

124

125

128

2K

1V8_AVdd1

Vss

R680

1V8_AVdd1

Vss

R658

1V8_AVdd2

Vss

U12
DP83865MGT

R672

R647

33

R650

33

R649

33

R652

33

R651

33

R654

33

R653

33

R655

33

R657

33

R656

33

GMII_TXD0
GMII_TXD1
GMII_TXD2
I

GMII_TXD3
GMII_TXD4
GMII_TXD5
GMII_TXD6
GMII_TXD7

GMII_TX_EN
GMII_GTX_CLK
GMII_TX_ER

PHY_CLK
2_5V_ETH:1

1K

R662
CLK_25MHZ_EN

NON_IEEE_STRAP

MAN_MDIX_STRAP/TX_TCLK

U12
7

ACT_LED

LINK10_LED/RLED/SPEED1_STRAP

LINK10

2K 14
PHYADDR1_STRAP

LINK100_LED/DUPLEX_STRAP

2K 17
PHYADDR2_STRAP

LINK1000_LED/AN_EN_STRAP

10

R618

2K 18
PHYADDR3_STRAP

DUPLEX_LED/PHYADDR0_STRAP

13

R619

2K 95
PHYADDR4_STRAP

R620

2K 94
MULTI_EN_STRAP/TX_TRIGGER

R621

2K 89
MDIX_EN_STRAP

R622

2K 88
MAC_CLK_EN_STRAP/TX_SYN_CLK
34

LINK100
LINK1G
DUP_LED

2K

R623

2K

R624

2K

R625

2K

R626

2K

R627

VDD_SEL_STRAP

U12
DP83865CLK
PHY_CLK

86

CLK_IN

87

CLK_OUT

MDC

81

MDC

MDIO

80

MDIO

CLK_TO_MAC 85 CLK_TO_MAC

INTERRUPT

PHY_RESET

33

USRP2 Ethernet

RESET

FILE:

ethernet.sch

PAGE
3

10

11

12

13

$Date$

TITLE

33

Everything on 2.5V

PHY_INTn

R648

CLK_25MHZ

2_5V_ETH:1

DP83865PWR

1V8_AVdd3

Vss

Vss

Vss

Vss

Vss

R614

BG_REF
Vss

9.76K

NC

102

NC

NC

33

TXD0

40

C606

23

84

U12

R640

U12

ACTIVITY_LED/SPEED0_STRAP

R616

2_5V_ETH:1
2_5V_ETH:1

22uF CER X5R 6.3V

DP83865MAC

2_5V_ETH:1

L601

2_5V_ETH:1
L602

2_5V_ETH_A:1

R612

33

NONE

18

R613

909

DP83865CFGLED

C622C623C624C625C619C620C621C613
0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF0.1uF

C607

R642

2_5V_ETH:1
2_5V_ETH:1

0.01uF

909

R661

C609C608C610C611C612
0.1uF0.1uF0.1uF0.1uF0.1uF

X2
OUT

R617

10

R643

33 R641
GMII_RX_CLK
33
GMII_RXD0
33
GMII_RXD1
33
GMII_RXD2
33
GMII_RXD3
33
GMII_RXD4
33
GMII_RXD5
33
GMII_RXD6
33
GMII_RXD7
33
GMII_RX_ER
33
GMII_RX_DV
33

C642
0.1uF

1_8V:1

1_8VA:1

909

2_5V_ETH:1

Y15

C601

C602

IO_L16P_4

VCCO_4

0.1uF

SHIELD/GND

W16

VCCO_4

2_5V_ETH:1

SG1

U15

MDID_N

IO_L16N_4

VCCO_4

V16

T14

T13

GMII_TX_CLK

GMII_CRS

reset_fpga

R644

39

GMII_COL

S1

2_5V_FPGA:1

0.1uF

V18

MDIA_P

IO/VREF_4

4.7K

U12
DP83865MDI

R602 49.9

C641
0.1uF

R601 49.9

C640
0.1uF

IO

2_5V_ETH:1

R645 NONE

2_5V_ETH:1

U16

GMII_COL

R236

Add caps at 2.5V near PHY

T12

14

REVISION:

OF

DRAWN BY:
15

$Revision$
$Author$
16

17
2012 Ettus Research. All rights reserved.

10

11

U1

CY7C1356CACRAM

XC3SXX00FG456IO3

RAM_A01

RAM_D09

Y22

IO_L16P_3

IO_L28N_3/400NC

R22

RAM_WEn

V19

IO_L17N_3

IO_L28P_3/400NC

R21

RAM_OEn

RAM_D14

W21

IO_L19N_3

IO_L29N_3/400NC

P19

RAM_A09

RAM_D15

W20

IO_L19P_3

IO_L29P_3/400NC

R19

RAM_LDn

RAM_A16

U19

IO_L20N_3

IO_L31N_3/400NC

P18

RAM_CENn

RAM_A03

V20

IO_L20P_3

IO_L31P_3/400NC

P17

RAM_CLK

V22

IO_L21N_3

IO_L32N_3/400NC

P22

RAM_A11

RAM_A02

V21

IO_L21P_3

IO_L32P_3/400NC

P21

RAM_A15

T17

IO_L22N_3

IO_L33N_3/400NC

N18

RAM_A14

RAM_A18

RAM_D17
U19

35

RAM_A15

RAM_D04

68

DQa

44

RAM_A14

RAM_D05

69

DQa

45

RAM_A13

RAM_D06

72

DQa

46

RAM_A12

RAM_D07

73

DQa

47

RAM_A11

RAM_D08

74

DQPa

48

RAM_A10

RAM_D09

DQb

49

RAM_A09

RAM_D10

DQb

50

RAM_A08

RAM_D11

12

DQb

80

RAM_A07

RAM_D12

13

DQb

81

RAM_A06

RAM_D13

18

DQb

82

RAM_A05

RAM_D14

19

83

RAM_A04

RAM_D15

22

DQb

99

RAM_A03

RAM_D16

23

DQb

100

RAM_A02

RAM_D17

24

DQPb

A1

36

RAM_A01

A0

37

RAM_A00

RAM_A17

U18

IO_L22P_3

IO_L33P_3/400NC

N17

RAM_A13

ZZ

64

RAM_A00

U21

IO_L23N_3

IO_L34P_3/VREF_3

N19

RAM_A12

RAM_A08

R18

IO_L24N_3

IO_L40N_3/VREF_3

M22

RAM_A07

T18

IO_L24P_3

RAM_A06

T22

IO_L27N_3

RAM_A05

T21

IO_L27P_3

RAM_D00

N20

IO_L34N_3

98

31

RAM_D02

N22

IO_L35N_3

RAM_D01

N21

IO_L35P_3

RAM_D04

M18

IO_L38N_3

RAM_D03

M17

IO_L38P_3

M20

IO_L39N_3

10

RAM_D05

M19

IO_L39P_3

20

VDDQ

GND

17

RAM_D07

M21

IO_L40P_3

27

VDDQ

GND

21

54

VDDQ

GND

26

61

VDDQ

GND

40

70

VDDQ

GND

55

77

VDDQ

GND

60

15

VDD

GND

67

41

VDD

GND

71

65

VDD

GND

76

91

VDD

GND

90

2_5V_FPGA:1

CE1

C806 C807
0.1uF 0.1uF

C808
0.1uF

C809
0.1uF

C811
0.1uF

C812
0.1uF

C813
0.1uF

C814
0.1uF

C815
0.1uF

C816
0.1uF

C817
0.1uF

USRP2 RAM

$Date$

TITLE

ram.sch

PAGE
2

C810
0.1uF

C332C331C333C334C335
0.1uF0.1uF0.1uF0.1uF0.1uF

FILE:
1

2_5V_RAM:1

VCCO_3

GND

R20

VDDQ

VCCO_3

11

R17

VCCO_3

GND

RAM_D08

DQb

2_5V_RAM:1

P16

VDDQ

VCCO_3

RAM_D06

VCCO_3

U19
CY7C1356CACPWR

N16

DQa

MODE

2_5V_RAM:1

RAM_A10

63

RAM_CE1n

CY7C1356CACCTRL

M16

RAM_D03

BWb

T19

RAM_A16

94

IO_L26P_3/400NC

BWa

IO_L16N_3

DQa

93

W22

RAM_D02

34

ADV/LD

RAM_D13

RAM_A17

62

RAM_LDn

RAM_A04

33

OE

T20

85

IO_L26N_3/400NC

DQa

86

IO_L01P_3/VRN_3/DCI

59

RAM_OEn

Y19

RAM_D01

WE

RAM_D12

RAM_A18

88

RAM_CE1n

32

RAM_WEn

U20

CLK

IO_L23P_3/VREF_3

DQa

89

IO_L01N_3/VRP_3/DCI

58

RAM_CLK

Y20

RAM_D00

CEN

RAM_D11

RAM_D16

RAM_CENn

W19

CE3

IO_L17P_3/VREF_3

87

IO

CE2

Y21

92

RAM_D10

97

U19

REVISION:

OF

DRAWN BY:
9

$Revision$
$Author$
10

11
2012 Ettus Research. All rights reserved.