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1 2 3 4 5 6 7 8 PCB STACK UP QT6 BLOCK DIAGRAM 01
1
2
3
4
5
6
7
8
PCB STACK UP
QT6 BLOCK DIAGRAM
01
6L
CPU
CPU THERMAL
SENSOR
LAYER 1 : TOP
Penryn
14.318MHz
PAGE 4
A
A
LAYER 2 : SGND
478P (uPGA)/35W
PAGE 3,4
CLK_CPU_BCLK,CLK_CPU_BCLK#
LAYER 3 : IN1
CLOCK GEN
CLK_MCH_BCLK,CLK_MCH_BCLK#
LAYER 4 : IN2
DREFCLK,DREFCLK#
ALPRS355B MLF64PIN
FSB 667/800/1066
DREFSSCLK,DREFSSCLK#
LAYER 5 : VCC
PAGE 2
LAYER 6 : BOT
HDMI CON
PS8101
NORTH BRIDGE
PAGE 20
PAGE 20
DDRII-SODIMM1
DDRII 667/800 MHz
CRT
PAGE 12,13
Cantiga
Cable
VGA
PAGE 20
Docking
RJ-45
DDRII-SODIMM2
DDRII 667/800 MHz
B
CIR/Pwr btn
Dual Link
B
LCD CONN
SPDIF Out
PAGE 12,13
PAGE 5~9
Stereo MIC
PAGE 19
Headphone Jack
32.768KHz
USB Port
DMI LINK
Mini PCI-E Card x2
Express Card x1
Cable Docking x1
NBSRCCLK, NBSRCCLK#
VOL Cntr
PAGE 37
4,7,10,11
SATA0,1 150MB
USB2.0
TWO SATA - HDD
PAGE 33
0,1,8,9
5
3
2
12MHz
6
SYSTEM CHARGER(ISL6251AHAZ-T)
SOUTH BRIDGE
USB2.0 Ports
BlueTooth
Webcam
Fingerprint
PAGE 38
PAGE 30
PAGE 30
PAGE 30
PAGE 30
SATA4 150MB
X4
SATA - CD-ROM
Card Reader
PAGE 33
RTS5158
SYSTEM POWER ISL6237IRZ-T
PAGE 25
ICH-9M
PAGE 39
SATA5 150MB
PCI-E
E-SATA
PAGE 30
X3
X1
X1
DDR II SMDDR_VTERM
C
Azalia
C
1.8V/1.8VSUS(TPS51116REGR)
Accelerometer
SMBUS
PAGE 21,22,23,24
Mini PCI-E
LAN
Express
PAGE 43
PAGE 28
LIS3LV02DL
Card
Card
Realtek
PCIE-LAN
IDT
(NEW CARD)
VCCP +1.5V AND GMCH
(Wireless
RTL8101E/8111C
1.05V(RT8204)
LPC
LAN/ROBSON/TV)
32.768KHz
(10/100/GagaLAN)
92HP61B7X5NLGXA1
PAGE 33
PAGE 40
MDC CONN
PAGE 36
PAGE 27
PAGE 31,32
PAGE 29
CPU CORE ISL6266A
ENE KBC
PAGE 41
Keyboard
25MHz
RJ45
Touch Pad
PAGE 35
KB3926 B1
SPI for
AUDIO
Amplifier
KB3926 C0
HDCP
TPA6017A2
PAGE 31
Capacitive Sense
PAGE 22
PAGE 28
SW
PAGE 34
PAGE 35
D
microphone
Audio Jacks
D
Jack to
(Phone/ MIC)
Speaker
PAGE 27
PAGE 27
PAGE 28
GMT G9931P1U
SPI
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
FAN
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PAGE 35
PAGE 37
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Block Diagram
Block Diagram
Block Diagram
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
1
1
1
of
of
of
44
44
44
1
2
3
4
5
6
7
8
1 2 3 4 5 6 7 8 3,4,6,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44 +3V 3,4,5,6,8,9,21,24,34,40,41
1
2
3
4
5
6
7
8
3,4,6,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44
+3V
3,4,5,6,8,9,21,24,34,40,41
+1.05V
02
+3V
L38
L38
+3V_CK_MAIN
1
2
U21
U21
HCB1608KF-181T15
HCB1608KF-181T15
C513
C513
C562
C562
C511
C511
C509
C509
C541
C541
C508
C508
+3V_CK_MAIN
23
61
VDDPLL3
CPUCLKT0
CLK_CPU_BCLK
3
10U/6.3V_8
10U/6.3V_8
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
16
60
VDD48
CPUCLKC0
CLK_CPU_BCLK#
3
A
SRC8
RP49RP49
3 *4P2R-S-0*4P2R-S-0
A
9
4
VDDPCI
CK505
CK505
CLK_CPU_ITP
3
SRC8#
4
58
2
VDDREF
CPUCLKT1
CLK_MCH_BCLK
5
1 CLK_CPU_ITP#
3
L42
L42
46
57
VDDSRC
CPUCLKC1
CLK_MCH_BCLK#
5
+3V_CK_CPU
+3V_CK_CPU
1
2
62
VDDCPU
HCB1608KF-181T15
HCB1608KF-181T15
SRC8
54
modify for SI Build
CPUT2_ITP/SRCT8
+3V_CK_MAIN2
SRC8#
19
53
VDD96I/O
CPUC2_ITP/SRCC8
C542
C542
C530
C530
27
VDDPLL3I/O
10U/6.3V_8
10U/6.3V_8
.1U/10V_4
.1U/10V_4
SRC0
33
20
VDDSRCI/O
DOTT_96/SRCT0
SRC0#
43
21
int
VDDSRCI/O
DOTC_96/SRCC0
SRC0
RP47RP47
4P2R-S-04P2R-S-0
52
2
1
VDDSRCI/O
DREFCLK
6
SRC1
SRC0#
24
4
3
27MHz_Nonss/SRCCLK1/SE1
DREFCLK#
6
L43
L43
SRC1#
56
25
VDDCPU_IO
27Mhz_ss/SRCCLC1/SE2
+3V_CK_MAIN2
1
2
55
NC
HCB1608KF-181T15
HCB1608KF-181T15
28
int
SRCCLKT2/SATACL
CLK_PCIE_NEW
33
SRC1
RP50RP50
4P2R-S-04P2R-S-0
29
2
1
SRCCLKC2/SATACL
CLK_PCIE_NEW#
33
DREFSSCLK
6
C554
C554
C549
C549
C561
C561
C529
C529
C566
C566
C547
C547
C539
C539
CG_XIN
SRC1#
3
4
3
X1
DREFSSCLK#
6
10U/6.3V_8
10U/6.3V_8
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
CG_XOUT
2
31
X2
SRCCLKT3/CR#_C
32
SRCCLKC3/CR#_D
*100K/F_4*100K/F_4
R317R317
34
SRCCLKT4
CLK_PCIE_3GPLL
6
35
SRCCLKC4
CLK_PCIE_3GPLL#
6
63
45
23
CK_PWG
CK_PWRGD/PD#
PCI_STOP#
PM_STPPCI# 23
+3V
CPU_BSEL1
R312
R312
2.2K_4
2.2K_4
FSB
64
44
FSLB/TEST_MODE
CPU_STOP#
PM_STPCPU# 23
+3V
48
SRCCLKT6
CLK_PCIE_ICH
22
47
SRCCLKC6
CLK_PCIE_ICH#
22
7
51
SCLK
SRCCLKT7/CR#_F
CLK_PCIE_WLAN
36
10,11,28,33,36
CGCLK_SMB
Q15
Q15
R297
R297
R296
R296
6
50
SDATA
SRCCLKC7/CR#_E
CLK_PCIE_WLAN#
36
B
10,11,28,33,36
CGDAT_SMB
R279
R279
10K/F_4
10K/F_4
10K/F_4
10K/F_4
B
10K/F_4
10K/F_4
2N7002
2N7002
37
SRCCLKT9
CLK_PCIE_LAN
31
CGDAT_SMB
3
1
22
38
23
PDAT_SMB
GND
SRCCLKC9
CLK_PCIE_LAN#
31
26
GND
TME
18
41
GND48
SRCCLKT10
CLK_PCIE_SATA
21
59
42
GNDCPU
SRCCLKC10
CLK_PCIE_SATA#
21
15
GNDPCI
+3V
1
40
GNDREF
SRCCLKT11/CR#_H
CLK_PCIE_TVC
36
30
39
GNDSRC
SRCCLKC11/CR#_G
CLK_PCIE_TVC#
36
Q16
Q16
36
GNDSRC
49
GNDSRC
2N7002
2N7002
R_CLK_NEWCARD_OE#
8
R295
R295
475/F_4
475/F_4
PCICLK0/CR#_A
CLK_NEWCARD_OE#
33
CGCLK_SMB
R_CLK_MCH_OE#
R280
R280
475/F_4
475/F_4
3
1
10
23
PCLK_SMB
PCICLK1/CR#_B
CLK_MCH_OE#
6
TME
11
R276
R276
33_4
33_4
PCICLK2/TME
PCLK_DEBUG
36
R_PCLK_KBC
R288
R288
33_4
33_4
12
PCICLK3
PCLK_KBC
35
27M_SEL
13
PCICLK4/27_SELECT
0=overclocking
ITP_EN
R285
R285
33_4
33_4
65
of CPU and
SRC Allowed
Y3
Y3
EPAD
PCLK_ICH
22
CG_XIN
CG_XOUT
R308
R308
22_4
22_4
1
2
14
PCI_F5/ITP_EN
CLK_48M_USB
23
R303
R303
22_4
22_4
CLK_48M_CR
25
1
= overclocking
FSA
R315
R315
2.2K_4
2.2K_4
CPU_BSEL0
17
14.318MHZ
14.318MHZ
USB_48MHZ/FSLA
FSC
R289
R289
10K/F_4
10K/F_4
CPU_BSEL2
of CPU and SRC
C507
C507
C512
C512
FSLC
5
R298
R298
33_4
33_4
FSLC/TST_SL/REF
CLK_14M_ICH
23
not Allowed
30P/50V_4
30P/50V_4
30P/50V_4
30P/50V_4
ICS9LPRS355BKLF MLF64
ICS9LPRS355BKLF MLF64
C
modify for SI Build
C
CK505
QFN64
ICS
ICS9LPRS355BKLF
ALPRS355000
+3V
27M_SEL
PIN20
PIN21
PIN24
PIN25
Silego
SLG8SP513VTR
AL8SP513000
27M_SEL
PIN13
CLK_MCH_OE#
R277
R277
10K/F_4
10K/F_4
2
1
Realtek
RTM875N-606-VD-GR
AL000875000
0=UMA
DOT96T
DOT96C
SRCT1/LCDT_100
SRCT1/LCDT_100
CLK_NEWCARD_OE#
R294
R294
10K/F_4
10K/F_4
2
1
int
R299
R299
10K/F_4
10K/F_4
1 = External
VGA
SRCT0
SRCC0
27Mout-NSS
27Mout-SS
0=UMA
modify for SI Build
1
= External VGA
C501
C501
*33P/50V_4
*33P/50V_4
PCLK_KBC
CPU Clock select
FSC
FSB
FSA
CPU
SRC
PCI
C503
C503
*27P/50V_4
*27P/50V_4
PCLK_ICH
+3V
1
0
1
100
100
33
C495
C495
*33P/50V_4
*33P/50V_4
PCLK_DEBUG
CPU_BSEL0
R321
R321
1K/F_4
1K/F_4
3
CPU_BSEL0
MCH_BSEL0
6
0
0
1
133
100
33
C518
C518
10P/50V_4
10P/50V_4
CLK_48M_USB
0
1
1
166
100
33
C514
C514
10P/50V_4
10P/50V_4
CLK_48M_CR
*10K/F_4
*10K/F_4
R314
R314
1K/F_4
1K/F_4
R291
R291
0
1
0
200
100
33
C506
C506
*33P/50V_4
*33P/50V_4
CLK_14M_ICH
R_PCLK_KBC
CPU_BSEL1
R316
R316
1K/F_4
1K/F_4
3
CPU_BSEL1
MCH_BSEL1
6
D
D
0
0
0
266
100
33
for EMI
ITP_EN
1
0
0
333
100
33
R322
R322
1K/F_4
1K/F_4
+1.05V
R283
R283
1
1
0
400
100
33
10K/F_4
10K/F_4
*10K/F_4
*10K/F_4
CPU_BSEL2
R278
R278
1K/F_4
1K/F_4
3
CPU_BSEL2
MCH_BSEL2
6
R292
R292
1
1
1
RSVD
100
33
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
R281
R281
1K/F_4
1K/F_4
1K to NB only when
XDP is implement.No
XDP can use 0 ohm
+1.05V
Enable ITP CLK
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Clock Generator
Clock Generator
Clock Generator
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
2
2
2
of
of
of
44
44
44
1
2
3
4
5
6
7
8
1
2
1
2
1
2
1
2
1
2
12
2
2
12
5 4 3 2 1 2,4,5,6,8,9,21,24,34,40,41 +1.05V 03 U34A U34A 5 H_A#[35:3] H_A#3 J4 H1
5
4
3
2
1
2,4,5,6,8,9,21,24,34,40,41
+1.05V
03
U34A
U34A
5
H_A#[35:3]
H_A#3
J4
H1
A[3]#
ADS#
H_ADS#
5
5
H_D#[63:0]
H_A#4
U34B
U34B
H_D#[63:0]
L5
E2
A[4]#
BNR#
H_BNR#
5
H_A#5
H_D#0
H_D#32
L4
G5
E22
Y22
A[5]#
BPRI#
H_BPRI#
5
D[0]#
D[32]#
H_A#6
H_D#1
H_D#33
K5
F24
AB24
A[6]#
D[1]#
D[33]#
H_A#7
H_D#2
H_D#34
M3
H5
E26
V24
A[7]#
DEFER#
H_DEFER#
5
D[2]#
D[34]#
H_A#8
H_D#3
H_D#35
N2
F21
G22
V26
A[8]#
DRDY#
H_DRDY#
5
D[3]#
D[35]#
H_A#9
H_D#4
H_D#36
J1
E1
F23
V23
A[9]#
DBSY#
H_DBSY#
5
D[4]#
D[36]#
D
H_A#10
H_D#5
H_D#37
D
N3
G25
T22
DATA GRP 3DATA
DATA GRP 3DATA
GRP 2
GRP 2
A[10]#
D[5]#
D[37]#
H_A#11
H_D#6
H_D#38
P5
F1
E25
U25
A[11]#
BR0#
HBREQ#0
5
D[6]#
D[38]#
H_A#12
H_D#7
H_D#39
P2
E23
U23
A[12]#
D[7]#
D[39]#
H_A#13
H_IERR#
R138
R138
56.2/F_4
56.2/F_4
H_D#8
H_D#40
L2
D20
K24
Y25
DATA GRP 1DATA
DATA GRP 1DATA
GRP 0
GRP 0
+1.05V
A[13]#
IERR#
D[8]#
D[40]#
H_A#14
H_D#9
H_D#41
P4
B3
G24
W22
A[14]#
INIT#
H_INIT#
21
D[9]#
D[41]#
H_A#15
H_D#10
H_D#42
P1
J24
Y23
A[15]#
D[10]#
D[42]#
H_A#16
H_D#11
H_D#43
R1
H4
J23
W24
A[16]#
LOCK#
H_LOCK#
5
D[11]#
D[43]#
H_D#12
H_D#44
M1
H22
W25
5
H_ADSTB#0
ADSTB[0]#
H_CPURST#
5
D[12]#
D[44]#
H_D#13
H_D#45
C1
F26
AA23
5
H_REQ#[4:0]
RESET#
D[13]#
D[45]#
H_REQ#0
H_RS#0
H_D#14
H_D#46
K3
F3
K22
AA24
REQ[0]#
RS[0]#
D[14]#
D[46]#
H_REQ#1
H_RS#1
H_D#15
H_D#47
H2
F4
H23
AB25
REQ[1]#
RS[1]#
D[15]#
D[47]#
H_REQ#2
H_RS#2
K2
G3
J26
Y26
H_RS#[2:0]
5
REQ[2]#
RS[2]#
5
H_DSTBN#0
DSTBN[0]#
DSTBN[2]#
H_DSTBN#2
5
H_REQ#3
J3
G2
H26
AA26
REQ[3]#
TRDY#
H_TRDY#
5
5
H_DSTBP#0
DSTBP[0]#
DSTBP[2]#
H_DSTBP#2
5
H_REQ#4
L1
H25
U22
REQ[4]#
5
H_DINV#0
DINV[0]#
DINV[2]#
H_DINV#2
5
H_A#[35:3]
G6
HIT#
H_HIT#
5
H_A#17
H_D#[63:0]
H_D#[63:0]
Y2
E4
A[17]#
HITM#
H_HITM#
5
H_A#18
H_D#16
H_D#48
U5
N22
AE24
A[18]#
D[16]#
D[48]#
H_A#19
ITP_BPM#0
H_D#17
H_D#49
R3
AD4
K25
AD24
A[19]#
BPM[0]#
D[17]#
D[49]#
H_A#20
ITP_BPM#1
H_D#18
H_D#50
W6
AD3
P26
AA21
A[20]#
BPM[1]#
D[18]#
D[50]#
H_A#21
ITP_BPM#2
H_D#19
H_D#51
U4
AD1
R23
AB22
A[21]#
BPM[2]#
D[19]#
D[51]#
H_A#22
ITP_BPM#3
H_D#20
H_D#52
Y5
AC4
L23
AB21
A[22]#
BPM[3]#
D[20]#
D[52]#
H_A#23
ITP_BPM#4
H_D#21
H_D#53
U1
AC2
M24
AC26
A[23]#
PRDY#
D[21]#
D[53]#
H_A#24
ITP_BPM#5
H_D#22
H_D#54
R4
AC1
L22
AD20
A[24]#
PREQ#
D[22]#
D[54]#
H_A#25
ITP_TCK
H_D#23
H_D#55
T5
AC5
M23
AE22
A[25]#
TCK
D[23]#
D[55]#
H_A#26
ITP_TDI
H_D#24
H_D#56
T3
AA6
P25
AF23
A[26]#
TDI
D[24]#
D[56]#
H_A#27
ITP_TDO
H_D#25
H_D#57
W2
AB3
P23
AC25
A[27]#
TDO
D[25]#
D[57]#
H_A#28
ITP_TMS
H_D#26
H_D#58
W5
AB5
P22
AE21
A[28]#
TMS
D[26]#
D[58]#
H_A#29
ITP_TRST#
H_D#27
H_D#59
Y4
AB6
T24
AD21
A[29]#
TRST#
D[27]#
D[59]#
H_A#30
H_D#28
H_D#60
U2
C20
R24
AC22
A[30]#
DBR#
SYS_RST#
23
D[28]#
D[60]#
H_A#31
H_D#29
H_D#61
V4
L25
AD23
A[31]#
D[29]#
D[61]#
C
H_A#32
+1.05V
H_D#30
H_D#62
C
W3
T25
AF22
A[32]#
H_PROCHOT#
41
D[30]#
D[62]#
H_A#33
THERMAL
THERMAL
H_D#31
H_D#63
AA4
N25
AC23
A[33]#
D[31]#
D[63]#
H_A#34
AB2
L26
AE25
A[34]#
5
H_DSTBN#1
DSTBN[1]#
DSTBN[3]#
H_DSTBN#3
5
H_A#35
AA3
D21
R129
R129
68_4
68_4
R543
R543
M26
AF24
+1.05V
A[35]#
PROCHOT#
5
H_DSTBP#1
DSTBP[1]#
DSTBP[3]#
H_DSTBP#3
5
1K/F_4
1K/F_4
V1
A24
N24
AC20
5
H_ADSTB#1
ADSTB[1]#
THERMDA
H_THERMDA
4
5
H_DINV#1
DINV[1]#
DINV[3]#
H_DINV#3
5
B25
THERMDC
H_THERMDC
4
H_GTLREF
COMP0
A6
AD26
R26
R551
R551
24.9/F_4
24.9/F_4
21
H_A20M#
A20M#
GTLREF
COMP[0]
CPU_TEST1
COMP1
R549
R549
49.9/F_4
49.9/F_4
A5
C7
C23
MISC
MISC
U26
21
H_FERR#
FERR#
THERMTRIP#
PM_THRMTRIP# 6,21
TEST1
COMP[1]
CPU_TEST2
C4
R542
R542
COMP2
D25
AA1
R51
R51
24.9/F_4
24.9/F_4
21
H_IGNNE#
IGNNE#
TEST2
COMP[2]
2K/F_4
2K/F_4
CPU_TEST3
COMP3
R54
R54
49.9/F_4
49.9/F_4
C24
Y1
TP7TP7
TEST3
COMP[3]
H
H
CLK
CLK
CPU_TEST4
D5
AF26
21
H_STPCLK#
STPCLK#
TP61TP61
TEST4
CPU_TEST5
C6
AF1
E5
21
H_INTR
LINT0
TP62TP62
TEST5
DPRSTP#
H_DPRSTP#
6,21,41
CPU_TEST6
B4
A22
A26
B5
21
H_NMI
LINT1
BCLK[0]
CLK_CPU_BCLK
2
TP63TP63
TEST6
DPSLP#
H_DPSLP#
21
CPU_TEST7
A3
A21
C3
D24
21
H_SMI#
SMI#
BCLK[1]
CLK_CPU_BCLK#
2
TP8TP8
TEST7
DPWR#
H_DPWR#
5
B22
D6
2
CPU_BSEL0
BSEL[0]
PWRGOOD
H_PWRGD
21
For QC CPU
Quard Core Only
Quard Core Only
B23
D7
2
CPU_BSEL1
BSEL[1]
SLP#
H_CPUSLP#
5
R174
R174
51/F_4
51/F_4
F6
D2
C21
AE6
+1.05V
TDI_1/RSV
RSVD[06]
2
CPU_BSEL2
BSEL[2]
PSI#
PM_PSI#
41
D3
TDO_2/RSV
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
ITP_BPM1#0
N5
BMP_1#[0]/RSV
ITP_BPM1#1
CPU_TEST2
R141
R141
*1K/F_4
*1K/F_4
M4
BMP_1#[1]/RSV
ITP_BPM1#2
B2
BMP_1#[2]/RSV
ITP_BPM1#3
AE8
BMP_1#[3]/VSS
CPU_TEST1
D8
R151
R151
*1K/F_4
*1K/F_4
TP5TP5
DCLKPH_1/VSS
GTLREF_CTL
For QC Support
+1.05V
F8
ACLKPH_1/VSS
H_GTLREF2
D22
GTLREF_2/RSV
H_THERMDA2
T2
4
H_THERMDA2
THRMDA_1/RSV
H_THERMDC2
R150
R150
V3
4
H_THERMDC2
THRMDC_1/RSV
AA8
Don't install for DC
*1K/F_4
*1K/F_4
TP2TP2
HFPLL_1/VSS
AC8
TP1TP1
SPARE_1[4]/VSS
B
+3V
B
AA7
TP3TP3
BR1#/VCC
H_GTLREF2
CONTROL
CONTROL
XDP/ITP SIGNALS
XDP/ITP SIGNALS
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
ICH
ICH
+1.05V
R185
R185
R154
R154
Populate ITP700Flex for bringup
+1.05V
*2K/F_4
*2K/F_4
*100K/F_4
*100K/F_4
ADDR GROUP 0
ADDR GROUP 0
ADDR GROUP 1
ADDR GROUP 1
R31
R31
54.9/F_4
54.9/F_4
ITP_TCK
R177
R177
2
Q10
Q10
*10K/F_4
*10K/F_4
R32
R32
54.9/F_4
54.9/F_4
ITP_TRST#
*2N7002
*2N7002
R180
R180
Q11
Q11
R170
R170
R30
R30
R23
R23
R20
R20
*10K/F_4
*10K/F_4
*MMBT3904-7-F
*MMBT3904-7-F
BSS138
*51/F_4
*51/F_4
54.9/F_4
54.9/F_4
54.9/F_4
54.9/F_4
GTLREF_CTL
2
*54.9/F_4
*54.9/F_4
JITP1
JITP1
+1.05V
+1.05V
ITP_TDI
1
27
C21
C21
*.1U/10V_4
*.1U/10V_4
TDI
VTT0
ITP_TMS
2
28
TMS
VTT1
ITP_TCK
5
26
C19
C19
*.1U/10V_4
*.1U/10V_4
TCK
VTAP
ITP_TDO
7
TDO
ITP_TRST#
3
TRST#
ITP_BPM1#0
R24
R24
*0_4
*0_4
ITP_BPM#0
R36
R36
R35
R35
R34
R34
R33
R33
ITP_BPM1#1
R25
R25
*0_4
*0_4
ITP_BPM#1
H_CPURST#
R29
R29
*1K/F_4
*1K/F_4
ITP_RST#
SYS_RST#
12
25
*51/F_4
*51/F_4
*51/F_4
*51/F_4
*51/F_4
*51/F_4
*51/F_4
*51/F_4
ITP_BPM1#2
R26
R26
*0_4
*0_4
ITP_BPM#2
RESET#
DBR#
ITP_BPM1#3
R27
R27
*0_4
*0_4
ITP_BPM#3
24
DBA#
ITP_TCK
11
FBO
ITP_BPM1#0
ITP_BPM1#1
8
2
CLK_CPU_ITP#
BCLKN
ITP_BPM#0
ITP_BPM1#2
9
23
2
CLK_CPU_ITP
BCLKP
BPM0#
A
C169
C169
ITP_BPM#1
ITP_BPM1#3
A
21
BPM1#
*100P/50V_4
*100P/50V_4
ITP_BPM#2
19
BPM2#
ITP_BPM#3
10
17
GND0
BPM3#
ITP_BPM#4
14
15
GND1
BPM4#
ITP_BPM#5
16
13
GND2
BPM5#
18
4
GND3
NC0
20
6
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
GND4
NC1
22
29
GND5
GND_0
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
30
GND_1
*ITP700Flex
*ITP700Flex
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Penryn 1/2
Penryn 1/2
Penryn 1/2
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
3
3
3
of
of
of
44
44
44
5
4
3
2
1
1
3
1
3
5 4 3 2 1 2,3,6,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44 +3V 2,3,5,6,8,9,21,24,34,40,41 +1.05V
5
4
3
2
1
2,3,6,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44
+3V
2,3,5,6,8,9,21,24,34,40,41
+1.05V
9,21,22,24,27,29,33,36,40,44
+1.5V
04
+VCORE
+VCORE
41
+VCORE
U34C
U34C
A7
AB20
U34D
U34D
VCC[001]
VCC[068]
A9
AB7
A4
P6
VCC[002]
VCC[069]
VSS[001]
VSS[082]
+VCORE
A10
AC7
A8
P21
VCC[003]
VCC[070]
VSS[002]
VSS[083]
A12
AC9
A11
P24
VCC[004]
VCC[071]
VSS[003]
VSS[084]
A13
AC12
A14
R2
VCC[005]
VCC[072]
VSS[004]
VSS[085]
A15
AC13
A16
R5
VCC[006]
VCC[073]
VSS[005]
VSS[086]
A17
AC15
A19
R22
VCC[007]
VCC[074]
VSS[006]
VSS[087]
C206
C206
C66
C66
C201
C201
C204
C204
A18
AC17
A23
R25
VCC[008]
VCC[075]
VSS[007]
VSS[088]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
A20
AC18
AF2
T1
VCC[009]
VCC[076]
VSS[008]
VSS[089]
D
D
B7
AD7
B6
T4
VCC[010]
VCC[077]
VSS[009]
VSS[090]
B9
AD9
B8
T23
VCC[011]
VCC[078]
VSS[010]
VSS[091]
B10
AD10
B11
T26
VCC[012]
VCC[079]
VSS[011]
VSS[092]
B12
AD12
B13
U3
VCC[013]
VCC[080]
VSS[012]
VSS[093]
C67
C67
C98
C98
C63
C63
C62
C62
B14
AD14
B16
U6
VCC[014]
VCC[081]
VSS[013]
VSS[094]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
B15
AD15
B19
U21
VCC[015]
VCC[082]
VSS[014]
VSS[095]
B17
AD17
B21
U24
VCC[016]
VCC[083]
VSS[015]
VSS[096]
B18
AD18
B24
V2
VCC[017]
VCC[084]
VSS[016]
VSS[097]
B20
AE9
C5
V5
VCC[018]
VCC[085]
VSS[017]
VSS[098]
C9
AE10
C8
V22
VCC[019]
VCC[086]
VSS[018]
VSS[099]
C205
C205
C93
C93
C97
C97
C96
C96
C10
AE12
C11
V25
VCC[020]
VCC[087]
VSS[019]
VSS[100]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
C12
AE13
C14
W1
VCC[021]
VCC[088]
VSS[020]
VSS[101]
C13
AE15
C16
W4
VCC[022]
VCC[089]
VSS[021]
VSS[102]
C15
AE17
C19
W23
VCC[023]
VCC[090]
VSS[022]
VSS[103]
C17
AE18
C2
W26
VCC[024]
VCC[091]
VSS[023]
VSS[104]
C18
AE20
C22
Y3
VCC[025]
VCC[092]
VSS[024]
VSS[105]
C31
C31
C30
C30
C92
C92
C33
C33
D9
AF9
C25
Y6
VCC[026]
VCC[093]
VSS[025]
VSS[106]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
D10
AF10
D1
Y21
VCC[027]
VCC[094]
VSS[026]
VSS[107]
D12
AF12
D4
Y24
VCC[028]
VCC[095]
VSS[027]
VSS[108]
D14
AF14
AA2
VCC[029]
VCC[096]
VSS[109]
D15
AF15
D11
AA5
VCC[030]
VCC[097]
VSS[029]
VSS[110]
D17
AF17
D13
VCC[031]
VCC[098]
VSS[030]
C207
C207
C208
C208
C26
C26
C27
C27
D18
AF18
D16
AA11
VCC[032]
VCC[099]
VSS[031]
VSS[112]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
E7
AF20
+1.05V
D19
AA14
VCC[033]
VCC[100]
VSS[032]
VSS[113]
E9
D23
AA16
VCC[034]
VSS[033]
VSS[114]
E10
G21
D26
AA19
VCC[035]
VCCP[01]
VSS[034]
VSS[115]
E12
V6
E3
AA22
VCC[036]
VCCP[02]
VSS[035]
VSS[116]
E13
J6
E6
AA25
VCC[037]
VCCP[03]
VSS[036]
VSS[117]
C28
C28
C29
C29
C69
C69
C65
C65
E15
K6
E8
AB1
VCC[038]
VCCP[04]
VSS[037]
VSS[118]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
+ +
C107
C107
E17
M6
E11
AB4
VCC[039]
VCCP[05]
VSS[038]
VSS[119]
C
330u_2.5V_7343
330u_2.5V_7343
C
E18
J21
E14
AB8
VCC[040]
VCCP[06]
VSS[039]
VSS[120]
E20
K21
E16
AB11
VCC[041]
VCCP[07]
VSS[040]
VSS[121]
F7
M21
E19
AB13
VCC[042]
VCCP[08]
VSS[041]
VSS[122]
F9
N21
+1.5V
E21
AB16
VCC[043]
VCCP[09]
VSS[042]
VSS[123]
C68
C68
C64
C64
C203
C203
C202
C202
F10
N6
E24
AB19
VCC[044]
VCCP[10]
VSS[043]
VSS[124]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
F12
R21
F5
AB23
VCC[045]
VCCP[11]
VSS[044]
VSS[125]
F14
R6
AB26
VCC[046]
VCCP[12]
VSS[126]
F15
T21
F11
AC3
VCC[047]
VCCP[13]
VSS[046]
VSS[127]
F17
T6
F13
AC6
VCC[048]
VCCP[14]
VSS[047]
VSS[128]
C807
C807
C803
C803
F18
V21
F16
VCC[049]
VCCP[15]
VSS[048]
C99
C99
C95
C95
C32
C32
C94
C94
.01U/16V_4
.01U/16V_4
10U/6.3V_8
10U/6.3V_8
F20
W21
F19
AC11
VCC[050]
VCCP[16]
VSS[049]
VSS[130]
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
22U/6.3V_8
F2
AC14
VSS[050]
VSS[131]
AA9
B26
F22
AC16
VCC[052]
VCCA[01]
VSS[051]
VSS[132]
AA10
C26
F25
AC19
VCC[053]
VCCA[02]
VSS[052]
VSS[133]
AA12
G4
AC21
VCC[054]
VSS[053]
VSS[134]
AA13
AD6
G1
AC24
VCC[055]
VID[0]
CPU_VID0
41
VSS[054]
VSS[135]
+1.05V
AA15
AF5
G23
AD2
VCC[056]
VID[1]
CPU_VID1
41
VSS[055]
VSS[136]
AA17
AE5
G26
AD5
VCC[057]
VID[2]
CPU_VID2
41
VSS[056]
VSS[137]
AA18
AF4
H3
AD8
VCC[058]
VID[3]
CPU_VID3
41
VSS[057]
VSS[138]
AA20
AE3
H6
AD11
VCC[059]
VID[4]
CPU_VID4
41
VSS[058]
VSS[139]
AB9
AF3
H21
AD13
VCC[060]
VID[5]
CPU_VID5
41
VSS[059]
VSS[140]
C72
C72
C70
C70
C39
C39
C61
C61
C75
C75
C45
C45
AC10
AE2
H24
AD16
VCC[061]
VID[6]
CPU_VID6
41
VSS[060]
VSS[141]
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
.1U/10V_4
AB10
J2
AD19
VCC[062]
VSS[061]
VSS[142]
AB12
J5
AD22
VCC[063]
VSS[062]
VSS[143]
AB14
AF7
J22
AD25
VCC[064]
VCCSENSE
VCCSENSE
41
VSS[063]
VSS[144]
AB15
J25
AE1
VCC[065]
VSS[064]
VSS[145]
AB17
K1
AE4
VCC[066]
VSS[065]
VSS[146]
U11U11
*EMC-1403*EMC-1403
AB18
AE7
K4
VCC[067]
VSSSENSE
VSSSENSE
41
VSS[066]
MBCLK2
LM86VCC
10
1
K23
AE11
SCLK
VCC
VSS[067]
VSS[148]
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
R46
R46
R48
R48
K26
AE14
VSS[068]
VSS[149]
B
MBDATA2
H_THERMDA
100/F_4
100/F_4
B
9
2
100/F_4
100/F_4
L3
AE16
SDA
DP1
VSS[069]
VSS[150]
L6
AE19
VSS[070]
VSS[151]
SYS_SHDN-1#
H_THERMDC
8
3
L21
AE23
ALERT#
DN1
VSS[071]
VSS[152]
L24
AE26
VSS[072]
VSS[153]
PM_THRM_R#
7
4
M2
A2
OVERT#
DP2
H_THERMDA2
3
VSS[073]
VSS[154]
C176
C176
M5
AF6
VSS[074]
VSS[155]
+3V
6
5
*100P/50V_4
*100P/50V_4
M22
AF8
GND
DN2
VSS[075]
VSS[156]
+VCORE
M25
AF11
H_THERMDC2
3
VSS[076]
VSS[157]
N1
AF13
VSS[077]
VSS[158]
For QC
N4
AF16
VSS[078]
VSS[159]
N23
AF19
VSS[079]
VSS[160]
R613
R613
N26
AF21
VSS[080]
VSS[161]
R121
R121
*0_4
*0_4
200_4
200_4
P3
A25
SYS_SHDN#
38,39
VSS[081]
VSS[162]
AF25
VSS[163]
25mils
LM86VCC
Penryn Ball-out Rev 1a
Penryn Ball-out Rev 1a
D8
D8
*RB501V-40
*RB501V-40
R132
R132
R131
R131
R161
R161
C811
C811
10K/F_4
10K/F_4
10K/F_4
10K/F_4
10K/F_4
10K/F_4
.1U/10V_4
.1U/10V_4
U9
U9
R120
R120
0_4
0_4
3920_RST# 35,38
MBCLK2
8
1
35
MBCLK2
SCLK
VCC
H_THERMDA
3
MBDATA2
7
2
35
MBDATA2
Q8
Q8
SDA
DXP
C158
C158
D9
D9
100P/50V_4
100P/50V_4
MMBT3904-7-F
MMBT3904-7-F
6
3
ALERT#
DXN
2
2
1
ECPWROK
6,23,35
4
5
OVERT#
GND
H_THERMDC
3
A
A
RB501V-40
RB501V-40
EMC1402-1-ACZL-TR
EMC1402-1-ACZL-TR
ADDRESS: 98H
R118
R118
10K/F_4
10K/F_4
+3V
SYS_SHDN-1#
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
SYS_SHDN-1#
37
PM_THRM_R#
0_6
0_6
R611
R611
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
PM_THRM# 23
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Penryn & TH Monitor 2/2
Penryn & TH Monitor 2/2
Penryn & TH Monitor 2/2
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
4
4
4
of
of
of
44
44
44
5
4
3
2
1
12
1
3
2
1
5 4 3 2 1 05 U40I U40I U40J U40J BG21 AH8 VSS_199 VSS_297 AU48
5
4
3
2
1
05
U40I
U40I
U40J
U40J
BG21
AH8
VSS_199
VSS_297
AU48
AM36
L12
Y8
VSS_1
VSS_100
VSS_200
VSS_298
AR48
AE36
AW21
L8
VSS_2
VSS_101
VSS_201
VSS_299
AL48
P36
AU21
E8
VSS_3
VSS_102
VSS_202
VSS_300
BB47
L36
AP21
B8
VSS_4
VSS_103
VSS_203
VSS_301
AW47
J36
AN21
AY7
VSS_5
VSS_104
VSS_204
VSS_302
AN47
F36
AH21
AU7
U40A
U40A
VSS_6
VSS_105
VSS_205
VSS_303
H_A#[35:3]
3
H_A#3
AJ47
B36
AF21
AN7
A14
VSS_7
VSS_106
VSS_206
VSS_304
3
H_D#[63:0]
H_A#_3
H_D#0
H_A#4
AF47
AH35
AB21
AJ7
F2
C15
VSS_8
VSS_107
VSS_207
VSS_305
H_D#_0
H_A#_4
H_D#1
H_A#5
AD47
AA35
R21
AE7
G8
F16
VSS_9
VSS_108
VSS_208
VSS_306
H_D#_1
H_A#_5
D
H_D#2
H_A#6
D
AB47
Y35
M21
AA7
F8
H13
VSS_10
VSS_109
VSS_209
VSS_307
H_D#_2
H_A#_6
H_D#3
H_A#7
Y47
U35
J21
N7
E6
C18
VSS_11
VSS_110
VSS_210
VSS_308
H_D#_3
H_A#_7
H_D#4
H_A#8
T47
T35
G21
J7
G2
M16
VSS_12
VSS_111
VSS_211
VSS_309
H_D#_4
H_A#_8
H_D#5
H_A#9
N47
BF34
BC20
BG6
H6
J13
VSS_13
VSS_112
VSS_212
VSS_310
H_D#_5
H_A#_9
H_D#6
H_A#10
L47
AM34
BA20
BD6
H2
P16
VSS_14
VSS_113
VSS_213
VSS_311
H_D#_6
H_A#_10
H_D#7
H_A#11
G47
AJ34
AW20
AV6
F6
R16
VSS_15
VSS_114
VSS_214
VSS_312
H_D#_7
H_A#_11
H_D#8
H_A#12
BD46
AF34
AT20
AT6
D4
N17
VSS_16
VSS_115
VSS_215
VSS_313
H_D#_8
H_A#_12
H_D#9
H_A#13
BA46
AE34
AJ20
AM6
H3
M13
VSS_17
VSS_116
VSS_216
VSS_314
H_D#_9
H_A#_13
H_D#10
H_A#14
AY46
W34
AG20
M6
M9
E17
VSS_18
VSS_117
VSS_217
VSS_315
H_D#_10
H_A#_14
H_D#11
H_A#15
AV46
B34
Y20
C6
M11
P17
VSS_19
VSS_118
VSS_218
VSS_316
H_D#_11
H_A#_15
H_D#12
H_A#16
AR46
A34
N20
BA5
J1
F17
VSS_20
VSS_119
VSS_219
VSS_317
H_D#_12
H_A#_16
H_D#13
H_A#17
AM46
BG33
K20
AH5
J2
G20
VSS_21
VSS_120
VSS_220
VSS_318
H_D#_13
H_A#_17
H_D#14
H_A#18
V46
BC33
F20
AD5
N12
B19
VSS_22
VSS_121
VSS_221
VSS_319
H_D#_14
H_A#_18
H_D#15
H_A#19
R46
BA33
C20
Y5
J6
J16
VSS_23
VSS_122
VSS_222
VSS_320
H_D#_15
H_A#_19
H_D#16
H_A#20
P46
AV33
A20
L5
P2
E20
VSS_24
VSS_123
VSS_223
VSS_321
H_D#_16
H_A#_20
H_D#17
H_A#21
H46
AR33
BG19
J5
L2
H16
VSS_25
VSS_124
VSS_224
VSS_322
H_D#_17
H_A#_21
H_D#18
H_A#22
F46
AL33
A18
H5
R2
J20
VSS_26
VSS_125
VSS_225
VSS_323
H_D#_18
H_A#_22
H_D#19
H_A#23
BF44
AH33
BG17
F5
N9
L17
VSS_27
VSS_126
VSS_226
VSS_324
H_D#_19
H_A#_23
H_D#20
H_A#24
AH44
AB33
BC17
BE4
L6
A17
VSS_28
VSS_127
VSS_227
VSS_325
H_D#_20
H_A#_24
H_D#21
H_A#25
AD44
P33
AW17
M5
B17
VSS_29
VSS_128
VSS_228
H_D#_21
H_A#_25
H_D#22
H_A#26
AA44
L33
AT17
BC3
J3
L16
VSS_30
VSS_129
VSS_229
VSS
VSS
VSS_327
H_D#_22
H_A#_26
H_D#23
H_A#27
Y44
H33
R17
AV3
N2
C21
VSS_31
VSS_130
VSS_230
VSS_328
H_D#_23
H_A#_27
+1.05V
H_D#24
H_A#28
U44
N32
M17
AL3
R1
J17
VSS_32
VSS_131
VSS_231
VSS_329
H_D#_24
H_A#_28
H_D#25
H_A#29
T44
K32
H17
R3
N5
H20
VSS_33
VSS_132
VSS_232
VSS_330
H_D#_25
H_A#_29
H_D#26
H_A#30
M44
F32
C17
P3
N6
B18
VSS_34
VSS_133
VSS_233
VSS_331
H_D#_26
H_A#_30
H_D#27
H_A#31
F44
C32
F3
P13
K17
VSS_35
VSS_134
VSS_332
H_D#_27
H_A#_31
H_D#28
H_A#32
BC43
A31
BA16
BA2
N8
B20
VSS_36
VSS_135
VSS_235
VSS_333
H_D#_28
H_A#_32
H_D#29
H_A#33
AV43
AN29
AW2
L7
F21
VSS_37
VSS_136
VSS_334
H_D#_29
H_A#_33
H_D#30
H_A#34
AU43
T29
AU16
AU2
R621
R621
N10
K21
VSS_38
VSS_137
VSS_237
VSS_335
H_D#_30
H_A#_34
221/F_4
221/F_4
H_D#31
H_A#35
AM43
N29
AN16
AR2
M3
L20
VSS_39
VSS_138
VSS_238
VSS_336
H_D#_31
H_A#_35
C
H_D#32
C
J43
K29
N16
AP2
Y3
VSS_40
VSS_139
VSS_239
VSS_337
H_D#_32
H_SWING
H_D#33
C43
H29
K16
AJ2
AD14
H12
VSS_41
VSS_140
VSS_240
VSS_338
H_D#_33
H_ADS#
H_ADS#
3
H_D#34
BG42
F29
G16
AH2
Y6
B16
VSS_42
VSS_141
VSS_241
VSS_339
H_D#_34
H_ADSTB#_0
H_ADSTB#0
3
H_D#35
AY42
A29
E16
AF2
Y10
G17
VSS_43
VSS_142
VSS_242
VSS_340
H_D#_35
H_ADSTB#_1
H_ADSTB#1
3
H_D#36
AT42
BG28
BG15
AE2
Y12
A9
VSS_44
VSS_143
VSS_243
VSS_341
H_D#_36
H_BNR#
H_BNR#
3
R622
R622
C837
C837
H_D#37
AN42
BD28
AC15
AD2
Y14
F11
VSS_45
VSS_144
VSS_244
VSS_342
H_D#_37
H_BPRI#
H_BPRI#
3
AJ42
BA28
W15
AC2
100/F_4
100/F_4
.1U/10V_4
.1U/10V_4
H_D#38
Y7
G12
VSS_46
VSS_145
VSS_245
VSS_343
H_D#_38
H_BREQ#
HBREQ#0
3
H_D#39
AE42
AV28
A15
Y2
W2
E9
VSS_47
VSS_146
VSS_246
VSS_344
H_D#_39
H_DEFER#
H_DEFER#
3
H_D#40
N42
AT28
BG14
M2
AA8
B10
VSS_48
VSS_147
VSS_247
VSS_345
H_D#_40
H_DBSY#
H_DBSY#
3
H_D#41
L42
AR28
AA14
K2
Y9
AH7
VSS_49
VSS_148
VSS_248
VSS_346
H_D#_41
HPLL_CLK
CLK_MCH_BCLK
2
H_D#42
BD41
AJ28
C14
AM1
AA13
AH6
VSS_50
VSS_149
VSS_249
VSS_347
H_D#_42
HPLL_CLK#
CLK_MCH_BCLK#
2
H_RCOMP
H_D#43
AU41
AG28
BG13
AA1
AA9
J11
VSS_51
VSS_150
VSS_250
VSS_348
H_D#_43
H_DPWR#
H_DPWR#
3
H_D#44
AM41
AE28
BC13
P1
AA11
F9
VSS_52
VSS_151
VSS_251
VSS_349
H_D#_44
H_DRDY#
H_DRDY#
3
H_D#45
AH41
AB28
BA13
H1
AD11
H9
VSS_53
VSS_152
VSS_252
VSS_350
H_D#_45
H_HIT#
H_HIT#
3
H_D#46
AD41
Y28
AD10
E12
VSS_54
VSS_153
H_D#_46
H_HITM#
H_HITM#
3
R196
R196
H_D#47
AA41
P28
U24
AD13
H11
VSS_55
VSS_154
VSS_351
H_D#_47
H_LOCK#
H_LOCK#
3
H_D#48
Y41
K28
AN13
U28
24.9/F_4
24.9/F_4
AE12
C9
VSS_56
VSS_155
VSS_255
VSS_352
H_D#_48
H_TRDY#
H_TRDY#
3
H_D#49
U41
H28
AJ13
U25
AE9
VSS_57
VSS_156
VSS_256
VSS_353
H_D#_49
H_D#50
T41
F28
AE13
U29
AA2
VSS_58
VSS_157
VSS_257
VSS_354
H_D#_50
H_D#51
M41
C28
N13
AD8
VSS_59
VSS_158
VSS_258
H_D#_51
H_D#52
G41
BF26
L13
AA3
VSS_60
VSS_159
VSS_259
H_D#_52
H_D#53
B41
AH26
G13
AF32
AD3
J8
VSS_61
VSS_160
VSS_260
VSS_NCTF_1
H_D#_53
H_DINV#_0
H_DINV#0
3
H_D#54
BG40
AF26
E13
AB32
AD7
L3
VSS_62
VSS_161
VSS_261
VSS_NCTF_2
H_D#_54
H_DINV#_1
H_DINV#1
3
H_D#55
BB40
AB26
BF12
V32
AE14
Y13
VSS_63
VSS_162
VSS_262
VSS_NCTF_3
H_D#_55
H_DINV#_2
H_DINV#2
3
H_D#56
AV40
AA26
AV12
AJ30
AF3
Y1
VSS_64
VSS_163
VSS_263
VSS_NCTF_4
H_D#_56
H_DINV#_3
H_DINV#3
3
H_D#57
AN40
C26
AT12
AM29
AC1
VSS_65
VSS_164
VSS_264
VSS_NCTF_5
H_D#_57
H_D#58
H40
B26
AM12
AF29
AE3
L10
VSS_66
VSS_165
VSS_265
VSS_NCTF_6
H_D#_58
H_DSTBN#_0
H_DSTBN#0
3
H_D#59
E40
BH25
AA12
AB29
AC3
M7
VSS_67
VSS_166
VSS_266
VSS_NCTF_7
H_D#_59
H_DSTBN#_1
H_DSTBN#1
3
H_D#60
AT39
BD25
J12
U26
AE11
AA5
VSS_68
VSS_167
VSS_267
VSS_NCTF_8
H_D#_60
H_DSTBN#_2
H_DSTBN#2
3
H_D#61
AM39
BB25
A12
U23
AE8
AE6
VSS_69
VSS_168
VSS_268
VSS_NCTF_9
H_D#_61
H_DSTBN#_3
H_DSTBN#3
3
H_D#62
B
B AJ39
AV25
BD11
AL20
AG2
VSS_70
VSS_169
VSS_269
VSS_NCTF_10
H_D#_62
H_D#63
AE39
AR25
BB11
V20
AD6
L9
VSS_71
VSS_170
VSS_270
VSS_NCTF_11
H_D#_63
H_DSTBP#_0
H_DSTBP#0
3
N39
AJ25
AY11
AC19
M8
VSS_72
VSS_171
VSS_271
VSS_NCTF_12
H_DSTBP#_1
H_DSTBP#1
3
L39
AC25
AN11
AL17
AA6
VSS_73
VSS_172
VSS_272
VSS_NCTF_13
H_DSTBP#_2
H_DSTBP#2
3
H_SWING
B39
Y25
AH11
AJ17
C5
AE5
VSS_74
VSS_173
VSS_273
VSS_NCTF_14
H_SWING
H_DSTBP#_3
H_DSTBP#3
3
H_RCOMP
BH38
N25
AA17
E3
VSS_75
VSS_174
VSS_NCTF_15
H_RCOMP
H_REQ#[4:0]
3
H_REQ#0
BC38
L25
Y11
U17
B15
VSS_76
VSS_175
VSS_275
VSS_NCTF_16
H_REQ#_0
H_REQ#1
BA38
J25
N11
K13
VSS_77
VSS_176
VSS_276
H_REQ#_1
H_REQ#2
AU38
G25
G11
F13
VSS_78
VSS_177
VSS_277
H_REQ#_2
+1.05V
H_REQ#3
AH38
E25
C11
BH48
B13
VSS_79
VSS_178
VSS_278
VSS_SCB_1
H_REQ#_3
H_REQ#4
AD38
BF24
BG10
BH1
C12
B14
VSS_80
VSS_179
VSS_279
VSS_SCB_2
3
H_CPURST#
H_CPURST#
H_REQ#_4
AA38
AD12
AV10
A48
E11
VSS_81
VSS_180
VSS_280
VSS_SCB_3
3
H_CPUSLP#
H_CPUSLP#
H_RS#[2:0]
3
R199
R199
H_RS#0
Y38
AY24
AT10
C1
B6
VSS_82
VSS_181
VSS_281
VSS_SCB_4
H_RS#_0
U38
AT24
AJ10
A3
1K/F_4
1K/F_4
H_RS#1
F12
VSS_83
VSS_182
VSS_282
VSS_SCB_5
H_RS#_1
H_RS#2
T38
AJ24
AE10
C8
VSS_84
VSS_183
VSS_283
H_RS#_2
H_AVREF
J38
AH24
AA10
E1
A11
VSS_85
VSS_184
VSS_284
NC_26
H_AVREF
F38
AF24
M10
D2
B11
VSS_86
VSS_185
VSS_285
NC_27
H_DVREF
R198
R198
C38
AB24
BF9
C3
VSS_87
VSS_186
VSS_286
NC_28
BF37
R24
BC9
B4
2K/F_4
2K/F_4
C844
C844
CANTIGA_GM
CANTIGA_GM
VSS_88
VSS_187
VSS_287
NC_29
.1U/10V_4
.1U/10V_4
BB37
L24
AN9
A5
VSS_89
VSS_188
VSS_288
NC_30
AW37
K24
AM9
A6
VSS_90
VSS_189
VSS_289
NC_31
AT37
J24
AD9
A43
VSS_91
VSS_190
VSS_290
NC_32
AN37
G24
G9
A44
VSS_92
VSS_191
VSS_291
NC_33
H_AVREF
AJ37
F24
B9
B45
VSS_93
VSS_192
VSS_292
NC_34
H37
E24
BH8
C46
VSS_94
VSS_193
VSS_293
NC_35
C37
BH23
BB8
D47
VSS_95
VSS_194
VSS_294
NC_36
BG36
AG23
AV8
B47
VSS_96
VSS_195
VSS_295
NC_37
BD36
Y23
AT8
A46
VSS_97
VSS_196
VSS_296
NC_38
AK15
B23
F48
VSS_98
VSS_197
NC_39
AU36
A23
E48
A VSS_99
VSS_198
NC_40
A
AJ6
C48
VSS_199
NC_41
B48
NC_42
2,3,4,6,8,9,21,24,34,40,41
+1.05V
CANTIGA_GM
CANTIGA_GM
CANTIGA_GM
CANTIGA_GM
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Cantiga Host & VSS 1/5
Cantiga Host & VSS 1/5
Cantiga Host & VSS 1/5
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
5
5
5
of
of
of
44
44
44
5
4
3
2
1
VSS
VSS
VSS SCB
VSS SCB
NC
NC
VSS NCTF
VSS NCTF
HOST
HOST
5 4 3 2 1 2,3,4,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44 +3V 8,9,10,34,40,43 +1.8VSUS LVDS
5
4
3
2
1
2,3,4,9,10,11,19,20,21,22,23,24,27,28,29,30,31,33,35,36,37,41,44
+3V
8,9,10,34,40,43
+1.8VSUS
LVDS
LVDS
TV
TV
2,3,4,5,8,9,21,24,34,40,41
+1.05V
06
VGA
VGA
MCH_CFG_5
DMIx2 selection
9
+1.05V_PEG
Low: DMIx2
High: DMIx4 (Default)
MCH_CFG_16
FSB Dynamic ODT
U40C
U40C
U40B
U40B
+1.05V_PEG
Low: Dynamic ODT disabled
High: Dynamic ODT enabled (Default)
M36
RSVD1
N36
AP24
L32
RSVD2
SA_CK_0
M_A_CLK0
10
19
DPST_PWM
L_BKLT_CTRL
MCH_CFG_9
PCI Express Graphic Lane
R33
AT21
G32
T37
PEG_COMP
R241
R241
49.9/F_4
49.9/F_4
RSVD3
SA_CK_1
M_A_CLK1
10
19
LVDS_BLON
L_BKLT_EN
PEG_COMPI
T33
AV24
R229
R229
10K/F_4
10K/F_4
L_CTRL_CLK
M32
T36
RSVD4
SB_CK_0
M_B_CLK0
10
L_CTRL_CLK
PEG_COMPO
AH9
AU20
Low: Reverse Lane
10
+3V
RSVD5
SB_CK_1
M_B_CLK1
AH10
R236
R236
10K/F_4
10K/F_4
L_CTRL_DATA
D
M33
D
High: Normal operation(Default)
RSVD6
L_CTRL_DATA
AH12
AR24
K33
H44
RSVD7
SA_CK#_0
M_A_CLK0#
10
19
EDIDCLK
L_DDC_CLK
PEG_RX#_0
MCH_CFG_19
DMI Lane Reversal
AH13
AR21
J33
J46
RSVD8
SA_CK#_1
M_A_CLK1#
10
19
EDIDDATA
L_DDC_DATA
PEG_RX#_1
K12
AU24
L44
RSVD9
SB_CK#_0
M_B_CLK0#
10
PEG_RX#_2
AV20
L40
Low: Normal (Default)
High: Lane Reserved
SB_CK#_1
M_B_CLK1#
10
PEG_RX#_3
M29
N41
19
DISP_ON
L_VDD_EN
PEG_RX#_4
BC28
R646
R646
2.37K/F_4 LVDS_IBG
2.37K/F_4
C44
P48
SA_CKE_0
M_A_CKE0
10,11
LVDS_IBG
PEG_RX#_5
MCH_CFG_6
iTPM Host Interface
AY28
LVDS_VBG
B43
N44
SA_CKE_1
M_A_CKE1
10,11
TP70TP70
LVDS_VBG
PEG_RX#_6
T24
AY36
E37
T43
RSVD14
SB_CKE_0
M_B_CKE0
10,11
LVDS_VREFH
PEG_RX#_7
BB36
E38
U43
Low: iTPM Host Interface enabled
High: iTPM Host Interface disabled (Default)
SB_CKE_1
M_B_CKE1
10,11
LVDS_VREFL
PEG_RX#_8
B31
C41
Y43
RSVD15
19
LA_CLK#
LVDSA_CLK#
PEG_RX#_9
B2
BA17
C40
Y48
RSVD16
SA_CS#_0
M_A_CS#0
10,11
19
LA_CLK
LVDSA_CLK
PEG_RX#_10
MCH_CFG_7
Intel (R) Management Engine Crypto
M1
AY16
B37
Y36
RSVD17
SA_CS#_1
M_A_CS#1
10,11
19
LB_CLK#
LVDSB_CLK#
PEG_RX#_11
AV16
A37
AA43
SB_CS#_0
M_B_CS#0
10,11
19
LB_CLK
LVDSB_CLK
PEG_RX#_12
AR13
AD37
Low: Intel (R) Management Engine Crypto
TLS cipher suite with no confidentiality
High: Intel (R) Management Engine Crypto
TLS cipher suite with no confidentiality (Default)
SB_CS#_1
M_B_CS#1
10,11
PEG_RX#_13
AY21
H47
AC47
RSVD20
19
LA_DATAN0
LVDSA_DATA#_0
PEG_RX#_14
BD17
E46
AD39
SA_ODT_0
M_A_ODT0
10,11
19
LA_DATAN1
LVDSA_DATA#_1
PEG_RX#_15
AY17
G40
SA_ODT_1
M_A_ODT1
10,11
19
LA_DATAN2
LVDSA_DATA#_2
BF15
LA_DATAN3
A40
H43
int
SB_ODT_0
M_B_ODT0
10,11
TP69TP69
LVDSA_DATA#_3
PEG_RX_0
BG23
AY13
+1.8VSUS
J44
RSVD22
SB_ODT_1
M_B_ODT1
10,11
PEG_RX_1
MCH_CFG_10
PCIe Lookback Enable
BF23
H48
L43
RSVD23
19
LA_DATAP0
LVDSA_DATA_0
PEG_RX_2
BH18
BG22
SM_RCOMP
R219
R219
80.6/F_4
80.6/F_4
D45
L41
PEG_RX3
HDMI_HPD#
RSVD24
SM_RCOMP
19
LA_DATAP1
LVDSA_DATA_1
PEG_RX_3
BF18
BH21
SM_RCOMP#
R209
R209
80.6/F_4
80.6/F_4
F40
N40
Low: Enabled
High: Disabled (Default)
RSVD25
SM_RCOMP#
19
LA_DATAP2
LVDSA_DATA_2
PEG_RX_4
LA_DATAP3
B40
P47
TP68TP68
LVDSA_DATA_3
PEG_RX_5
BF28
SM_RCOMP_VOH
N43
SM_RCOMP_VOH
PEG_RX_6
MCH_CFG_12/13
XOR/ALLZ/CLOCK Un-gating
BH28
SM_RCOMP_VOL
A41
T42
SM_RCOMP_VOL
19
LB_DATAN0
LVDSB_DATA#_0
PEG_RX_7
H38
U42
19
LB_DATAN1
LVDSB_DATA#_1
PEG_RX_8
MCH_CFG_13 MCH_CFG_12
Configuration
AV42
+0.9VSMVREF_MCH
G37
Y42
SM_VREF
19
LB_DATAN2
LVDSB_DATA#_2
PEG_RX_9
AR36
SW_PWROK_NB
R237
R237
10K/F_4
10K/F_4
LB_DATAN3
J37
W47
SM_PWROK
TP35TP35
LVDSB_DATA#_3
PEG_RX_10
0
0
Reserved
BF17
SM_REXT
R207
R207
499/F_4
499/F_4
Y37
SM_REXT
PEG_RX_11
BC36
TP_SM_DRAMRST#
B42
AA42
TP34TP34
SM_DRAMRST#
19
LB_DATAP0
LVDSB_DATA_0
PEG_RX_12
1
0
XOR Mode enabled
G38
AD36
19
LB_DATAP1
LVDSB_DATA_1
PEG_RX_13
B38
F37
AC48
DPLL_REF_CLK
DREFCLK
2
19
LB_DATAP2
LVDSB_DATA_2
PEG_RX_14
0
1
All-Z Mode enabled
A38
LB_DATAP3
K37
AD40
DPLL_REF_CLK#
DREFCLK#
2
TP37TP37
LVDSB_DATA_3
PEG_RX_15
E41
C
DPLL_REF_SSCLK
DREFSSCLK
2
C
1
1
Normal operation (Default)
F41
J41
C_PEG_TX#0
C416
C416
.1U/10V_4
.1U/10V_4
PEG_TX#0
DPLL_REF_SSCLK#
DREFSSCLK#
2
PEG_TX#_0
TP36TP36
AL34
M46
C_PEG_TX#1
C423
C423
.1U/10V_4
.1U/10V_4
PEG_TX#1
ME_JTAG_TCK
PEG_TX#_1
F43
R211
R211
75/F_4
75/F_4
F25
M47
C_PEG_TX#2
C440
C440
.1U/10V_4
.1U/10V_4
PEG_TX#2
PEG_CLK
CLK_PCIE_3GPLL
2
TVA_DAC
PEG_TX#_2
TP32TP32
AK34
E43
R213
R213
75/F_4
75/F_4
H25
M40
C_PEG_TX#3
C431
C431
.1U/10V_4
.1U/10V_4
PEG_TX#3
ME_JTAG_TDI
PEG_CLK#
CLK_PCIE_3GPLL#
2
TVB_DAC
PEG_TX#_3
R212
R212
75/F_4
75/F_4
K25
M42
TVC_DAC
PEG_TX#_4
TP29TP29
AN35
R48
ME_JTAG_TDO
PEG_TX#_5
H24
N38
DMI_TXN[3:0]
22
TV_RTN
PEG_TX#_6
TP28TP28
AM35
AE41
DMI_TXN0
modify for SI Build
T40
ME_JTAG_TMS
DMI_RXN_0
PEG_TX#_7
AE37
DMI_TXN1
U37
DMI_RXN_1
PEG_TX#_8
AE47
DMI_TXN2
U40
DMI_RXN_2
PEG_TX#_9
AH39
DMI_TXN3
R626
R626
*2.2K_4
*2.2K_4
TV_DCONSEL0
C31
Y40
+3V
DMI_RXN_3
TV_DCONSEL_0
PEG_TX#_10
R628
R628
*2.2K_4
*2.2K_4
TV_DCONSEL1
E32
AA46
DMI_TXP[3:0]
22
TV_DCONSEL_1
PEG_TX#_11
AE40
DMI_TXP0
AA37
2
MCH_BSEL0
DMI_RXP_0
PEG_TX#_12
T25
AE38
DMI_TXP1
AA40
2
MCH_BSEL1
CFG_0
DMI_RXP_1
PEG_TX#_13
R25
AE48
DMI_TXP2
AD43
2
MCH_BSEL2
CFG_1
DMI_RXP_2
PEG_TX#_14
P25
AH40
DMI_TXP3
AC46
CFG_2
DMI_RXP_3
PEG_TX#_15
MCH_CFG_3
P20
TP9TP9
CFG_3
DMI_RXN[3:0]
22
MCH_CFG_4
P24
AE35
DMI_RXN0
E28
J42
C_PEG_TX0
C419
C419
.1U/10V_4
.1U/10V_4
PEG_TX0
TP23TP23
CFG_4
DMI_TXN_0
20
CRT_B
CRT_BLUE
PEG_TX_0
MCH_CFG_5
C25
AE43
DMI_RXN1
R215
R215
150/F_4
150/F_4
L46
C_PEG_TX1
C418
C418
.1U/10V_4
.1U/10V_4
PEG_TX1
CFG_5
DMI_TXN_1
PEG_TX_1
TP64TP64
MCH_CFG_6
N24
AE46
DMI_RXN2
G28
M48
C_PEG_TX2
C430
C430
.1U/10V_4
.1U/10V_4
PEG_TX2
CFG_6
DMI_TXN_2
20
CRT_G
CRT_GREEN
PEG_TX_2
TP20TP20
MCH_CFG_7
M24
AH42
DMI_RXN3
R221
R221
150/F_4
150/F_4
M39
C_PEG_TX3
C424
C424
.1U/10V_4
.1U/10V_4
PEG_TX3
CFG_7
DMI_TXN_3
PEG_TX_3
MCH_CFG_8
E21
J28
M43
TP22TP22 TP14TP14
CFG_8
DMI_RXP[3:0]
22
20
CRT_R
CRT_RED
PEG_TX_4
MCH_CFG_9
C23
AD35
DMI_RXP0
R217
R217
150/F_4
150/F_4
R47
CFG_9
DMI_TXP_0
PEG_TX_5
TP12TP12
MCH_CFG_10
C24
AE44
DMI_RXP1
G29
N37
CFG_10
DMI_TXP_1
CRT_IRTN
PEG_TX_6
TP19TP19
TP16TP16
MCH_CFG_11
N21
AF46
DMI_RXP2
T39
CFG_11
DMI_TXP_2
PEG_TX_7
MCH_CFG_12
P21
AH43
DMI_RXP3
H32
U36
CFG_12
DMI_TXP_3
20
DDCCLK
CRT_DDC_CLK
PEG_TX_8
TP18TP18
MCH_CFG_13
T21
J32
U39
CFG_13
20
DDCDATA
CRT_DDC_DATA
PEG_TX_9
MCH_CFG_14
R20
R216
R216
33_4
33_4
HSYNC_INT
J29
Y39
TP13TP13 TP11TP11
CFG_14
20
HSYNC_COM
CRT_HSYNC
PEG_TX_10
MCH_CFG_15
M20
R630
R630
1.02K/F_4
1.02K/F_4
CRTIREF
E29
Y46
TP10TP10
CFG_15
CRT_TVO_IREF
PEG_TX_11
MCH_CFG_16
L21
R220
R220
33_4
33_4
VSYNC_INT
L29
AA36
CFG_16
20
VSYNC_COM
CRT_VSYNC
PEG_TX_12
MCH_CFG_17
H21
AA39
TP15TP15 TP17TP17
CFG_17
PEG_TX_13
MCH_CFG_18
P29
AD42
TP25TP25
CFG_18
PEG_TX_14
MCH_CFG_19
R28
AD46
CFG_19
PEG_TX_15
TP21TP21
MCH_CFG_20
T28
B33
GFXVR_VID_0
CFG_20
GFX_VID_0
TP66TP66
TP24TP24
B32
GFXVR_VID_1
B
B
GFX_VID_1
TP65TP65
G33
GFXVR_VID_2
CANTIGA_GM
CANTIGA_GM
GFX_VID_2
TP33TP33
F33
GFXVR_VID_3
GFX_VID_3
TP31TP31
R29
E33
GFXVR_VID_4
23
PM_SYNC#
PM_SYNC#
GFX_VID_4
TP30TP30
+1.8VSUS
B7
For UMA HDMI Function
3,21,41
H_DPRSTP#
PM_DPRSTP#
PM_EXTTS#0
N33
ME JTAG
ME JTAG
10,11
PM_EXTTS#0
PM_EXT_TS#_0
PM
PM
PM_EXTTS#1
P32
PEG_TX0
PEG_TX0
11
PM_EXTTS#1
PM_EXT_TS#_1
IN_D2
20
CFGRSVD
CFGRSVD
NC
NC
AT40
C34
GFXVR_EN
PEG_TX#0
PEG_TX#0
23,41
DELAY_VR_PWRGOOD
PWROK
GFX_VR_EN
TP67TP67
IN_D2#
20
R201
R201
100/F_4
100/F_4
RST_IN#_MCH
AT11
R225
R225
22
PLT_RST-R#
RSTIN#
T20
PEG_TX1
PEG_TX1
3,21
PM_THRMTRIP#
THERMTRIP#
IN_D1
20
+1.05V
R32
1K/F_4
1K/F_4
PEG_TX#1
PEG_TX#1
23,41
DPRSLPVR
DPRSLPVR
IN_D1#
20
AH37
SM_RCOMP_VOH
PEG_TX2
PEG_TX2
CL_CLK
CL_CLK0
23
IN_D0
20
AH36
R257
R257
PEG_TX#2
PEG_TX#2
CL_DATA
CL_DATA0
23
IN_D0#
20
BG48
AN36
0.35 V
1K/F_4
1K/F_4
C363
C363
NC_1
CL_PWROK
ECPWROK
4,23,35
BF48
AJ35
C356
C356
PEG_TX3
PEG_TX3
NC_2
CL_RST#
CL_RST#0
23
IN_CLK
20
+3V
BD48
AH34
MCH_CLVREF
.01U/16V_4
.01U/16V_4
2.2U/6.3V_6
2.2U/6.3V_6
R222
R222
PEG_TX#3
PEG_TX#3
NC_3
CL_VREF
IN_CLK#
20
BC48
3.01K/F_4
3.01K/F_4
NC_4
BH47
NC_5
BG47
C451
C451
R258
R258
NC_6
R235
R235
10K/F_4
10K/F_4
PM_EXTTS#0
BE47
N28
DDPC_CTRLCLK
.1U/10V_4
.1U/10V_4
499/F_4
499/F_4
SM_RCOMP_VOL
NC_7
DDPC_CTRLCLK
TP27TP27
BH46
M28
DDPPC_CTRLDATA
Level: 0.9V
NC_8
DDPC_CTRLDATA
TP26TP26
R230
R230
10K/F_4
10K/F_4
PM_EXTTS#1
BF46
G36
C386
C386
R552
R552
20K/F_4
20K/F_4
HDMI_HPD#
+3V
NC_9
SDVO_CTRLCLK
SDVO_CLK
20
BG45
E36
C373
C373
R218
R218
NC_10
SDVO_CTRLDATA
SDVO_DATA
20
BH44
K36
.01U/16V_4
.01U/16V_4
2.2U/6.3V_6
2.2U/6.3V_6
NC_11
CLKREQ#
CLK_MCH_OE#
2
BH43
H36
1K/F_4
1K/F_4
NC_12
ICH_SYNC#
MCH_ICH_SYNC#
23
+1.05V
BH6
NC_13
BH5
NC_14
BG4
B12
MCH_TSATN
R200
R200
56.2/F_4
56.2/F_4
NC_15
TSATN#
ACZ_BITCLK_MCH
BH3
2
Q31
Q31
NC_16
20
HDMI_HPD_CON
BF3
R550
R550
NC_17
2N7002
2N7002
BH2
7.5K/F_4
7.5K/F_4
NC_18
BG2
B28
NC_19
HDA_BCLK
ACZ_BITCLK_MCH
21
+1.8VSUS
BE2
B30
R558
R558
NC_20
HDA_RST#
ACZ_RST#_MCH
21
R634
R634
BG1
B29
ACZ_SDIN3_MCH
R638
R638
0_4
0_4
100K/F_4
100K/F_4
NC_21
HDA_SDI
ACZ_SDIN3
21
A
A
*33_4
*33_4
BF1
C29
NC_22
HDA_SDO
ACZ_SDOUT_MCH
21
BD1
A28
NC_23
HDA_SYNC
ACZ_SYNC_MCH
21
BC1
R253
R253
NC_24
F1
NC_25
C874
C874
A47
*1K/F_4
*1K/F_4
HPD# Inverting Level Shifting Circuit
NC_26
*33P/50V_4
*33P/50V_4
CANTIGA_GM
CANTIGA_GM
+0.9VSMVREF_MCH
R254
R254
0_4
0_4
+0.9VSMVREF
10,43
PROJECT : QT6
PROJECT : QT6
PROJECT : QT6
C426
C426
C425
C425
.1U/10V_4
.1U/10V_4
470P/50V_4
470P/50V_4
R251
R251
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
*1K/F_4
*1K/F_4
HP SVTP TEST
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
Custom
Custom
Custom
Cantiga DMI/DISP 2/5
Cantiga DMI/DISP 2/5
Cantiga DMI/DISP 2/5
2A
2A
2A
NB5
NB5
NB5
Date:
Date:
Date:
Monday, October 29, 2007
Monday, October 29, 2007
Monday, October 29, 2007
Sheet
Sheet
Sheet
6
6
6
of
of
of
44
44
44
5
4
3
2
1
MISC
MISC
CLK DDR CLK/ CONTROL/COMPENSATION
CLK DDR CLK/ CONTROL/COMPENSATION
MEHDA
MEHDA
GRAPHICS VID
GRAPHICS VID
DMI
DMI
12
PCI-EXPRESS GRAPHICS
PCI-EXPRESS GRAPHICS
1
3

D

 

5

D   5 C 10 M_A_DQ[63:0]   B A     5

C

10 M_A_DQ[63:0]

 
B

B

A

 
 

5

4

3

2

1

M_B_BS#0 10,11

M_B_BS#1 10,11

M_B_BS#2 10,11

M_B_RAS# 10,11

M_B_CAS# 10,11

M_B_WE# 10,11

M_B_DM[7:0]

10

M_B_DQS[7:0]

M_B_DQS#[7:0]

10

10

M_B_A[14:0]

10,11

07

D

C

10 M_B_DQS[7:0] M_B_DQS#[7:0] 10 10 M_B_A[14:0] 10,11 07 D C B A U40D U40D 10 M_B_DQ[63:0]

B

A

U40D U40D 10 M_B_DQ[63:0] M_A_DQ0 U40E U40E AJ38 BD21 SA_DQ_0 SA_BS_0 M_A_BS#0 10,11 M_A_DQ1 M_B_DQ0
U40D
U40D
10 M_B_DQ[63:0]
M_A_DQ0
U40E
U40E
AJ38
BD21
SA_DQ_0
SA_BS_0
M_A_BS#0 10,11
M_A_DQ1
M_B_DQ0
AJ41
BG18
AK47
BC16
SA_DQ_1
SA_BS_1
M_A_BS#1 10,11
SB_DQ_0
SB_BS_0
M_A_DQ2
M_B_DQ1
AN38
AT25
AH46
BB17
SA_DQ_2
SA_BS_2
M_A_BS#2 10,11
SB_DQ_1
SB_BS_1
M_A_DQ3
M_B_DQ2
AM38
AP47
BB33
SA_DQ_3
SB_DQ_2
SB_BS_2
M_A_DQ4
M_B_DQ3
AJ36
BB20
AP46
SA_DQ_4
SA_RAS#
M_A_RAS# 10,11
SB_DQ_3
M_A_DQ5
M_B_DQ4
AJ40
BD20
AJ46
SA_DQ_5
SA_CAS#
M_A_CAS# 10,11
SB_DQ_4
M_A_DQ6
M_B_DQ5
AM44
AY20
AJ48
AU17
SA_DQ_6
SA_WE#
M_A_WE# 10,11
SB_DQ_5
SB_RAS#
M_A_DQ7
M_B_DQ6
AM42
AM48
BG16
SA_DQ_7
SB_DQ_6
SB_CAS#
M_A_DQ8
M_B_DQ7
AN43
AP48
BF14
SA_DQ_8
SB_DQ_7
SB_WE#
M_A_DQ9
M_B_DQ8
AN44
AU47
SA_DQ_9
SB_DQ_8
M_A_DQ10
M_B_DQ9
AU40
AU46
SA_DQ_10
M_A_DM[7:0]
10
SB_DQ_9
M_A_DQ11
M_A_DM0
M_B_DQ10
AT38
AM37
BA48
SA_DQ_11
SA_DM_0
SB_DQ_10
M_A_DQ12
M_A_DM1
M_B_DQ11
AN41
AT41
AY48
SA_DQ_12
SA_DM_1
SB_DQ_11
M_A_DQ13
M_A_DM2
M_B_DQ12
M_B_DM0
AN39
AY41
AT47
AM47
SA_DQ_13
SA_DM_2
SB_DQ_12
SB_DM_0
M_A_DQ14
M_A_DM3
M_B_DQ13
M_B_DM1
AU44
AU39
AR47
AY47
SA_DQ_14
SA_DM_3
SB_DQ_13
SB_DM_1
M_A_DQ15
M_A_DM4
M_B_DQ14
M_B_DM2
AU42
BB12
BA47
BD40
SA_DQ_15
SA_DM_4
SB_DQ_14
SB_DM_2
M_A_DQ16
M_A_DM5
M_B_DQ15
M_B_DM3
AV39
AY6
BC47
BF35
SA_DQ_16
SA_DM_5
SB_DQ_15
SB_DM_3
M_A_DQ17
M_A_DM6
M_B_DQ16
M_B_DM4
AY44
AT7
BC46
BG11
SA_DQ_17
SA_DM_6
SB_DQ_16
SB_DM_4
M_A_DQ18
M_A_DM7
M_B_DQ17
M_B_DM5
BA40
AJ5
BC44
BA3
SA_DQ_18
SA_DM_7
SB_DQ_17
SB_DM_5
M_A_DQ19
M_B_DQ18
M_B_DM6
BD43
BG43
AP1
SA_DQ_19
M_A_DQS[7:0]
10
SB_DQ_18
SB_DM_6
M_A_DQ20
M_A_DQS0
M_B_DQ19
M_B_DM7
AV41
AJ44
BF43
AK2
SA_DQ_20
SA_DQS_0
SB_DQ_19
SB_DM_7
M_A_DQ21
M_A_DQS1
M_B_DQ20
AY43
AT44
BE45
SA_DQ_21
SA_DQS_1
SB_DQ_20
M_A_DQ22
M_A_DQS2
M_B_DQ21
M_B_DQS0
BB41
BA43
BC41
AL47
SA_DQ_22
SA_DQS_2
SB_DQ_21
SB_DQS_0
M_A_DQ23
M_A_DQS3
M_B_DQ22
M_B_DQS1
BC40
BC37
BF40
AV48
SA_DQ_23
SA_DQS_3
SB_DQ_22
SB_DQS_1
M_A_DQ24
M_A_DQS4
M_B_DQ23
M_B_DQS2
AY37
AW12
BF41
BG41
SA_DQ_24
SA_DQS_4
SB_DQ_23
SB_DQS_2
M_A_DQ25
M_A_DQS5
M_B_DQ24
M_B_DQS3
BD38
BC8
BG38
BG37
SA_DQ_25
SA_DQS_5
SB_DQ_24
SB_DQS_3
M_A_DQ26
M_A_DQS6
M_B_DQ25
M_B_DQS4
AV37
AU8
BF38
BH9
SA_DQ_26
SA_DQS_6
SB_DQ_25
SB_DQS_4
M_A_DQ27
M_A_DQS7
M_B_DQ26
M_B_DQS5
AT36
AM7
BH35
BB2
SA_DQ_27
SA_DQS_7
M_A_DQS#[7:0]
10
SB_DQ_26
SB_DQS_5
M_A_DQ28
M_A_DQS#0
M_B_DQ27
M_B_DQS6
AY38
AJ43
BG35
AU1
SA_DQ_28
SA_DQS#_0
SB_DQ_27
SB_DQS_6
M_A_DQ29
M_A_DQS#1
M_B_DQ28
M_B_DQS7
BB38
AT43
BH40
AN6
SA_DQ_29
SA_DQS#_1
SB_DQ_28
SB_DQS_7
M_A_DQ30
M_A_DQS#2
M_B_DQ29
M_B_DQS#0
AV36
BA44
BG39
AL46
SA_DQ_30
SA_DQS#_2
SB_DQ_29
SB_DQS#_0
M_A_DQ31
M_A_DQS#3
M_B_DQ30
M_B_DQS#1
AW36
BD37
BG34
AV47
SA_DQ_31
SA_DQS#_3
SB_DQ_30
SB_DQS#_1
M_A_DQ32
M_A_DQS#4
M_B_DQ31
M_B_DQS#2
BD13
AY12
BH34
BH41
SA_DQ_32
SA_DQS#_4
SB_DQ_31
SB_DQS#_2
M_A_DQ33
M_A_DQS#5
M_B_DQ32
M_B_DQS#3
AU11
BD8
BH14
BH37
SA_DQ_33
SA_DQS#_5
SB_DQ_32
SB_DQS#_3
M_A_DQ34
M_A_DQS#6
M_B_DQ33
M_B_DQS#4
BC11
AU9
BG12
BG9
SA_DQ_34
SA_DQS#_6
SB_DQ_33
SB_DQS#_4
M_A_DQ35
M_A_DQS#7
M_B_DQ34
M_B_DQS#5
BA12
AM8
BH11
BC2
SA_DQ_35
SA_DQS#_7
SB_DQ_34
SB_DQS#_5
M_A_DQ36
M_B_DQ35
M_B_DQS#6
AU13
BG8
AT2
SA_DQ_36
M_A_A[14:0]
10,11
SB_DQ_35
SB_DQS#_6
M_A_DQ37
M_A_A0
M_B_DQ36
M_B_DQS#7
AV13
BA21
BH12
AN5
SA_DQ_37
SA_MA_0
SB_DQ_36
SB_DQS#_7
M_A_DQ38
M_A_A1
M_B_DQ37
BD12
BC24
BF11
SA_DQ_38
SA_MA_1
SB_DQ_37
M_A_DQ39
M_A_A2
M_B_DQ38
M_B_A0
BC12
BG24
BF8
AV17
SA_DQ_39
SA_MA_2
SB_DQ_38
SB_MA_0
M_A_DQ40
M_A_A3
M_B_DQ39
M_B_A1
BB9
BH24
BG7
BA25
SA_DQ_40
SA_MA_3
SB_DQ_39
SB_MA_1
M_A_DQ41
M_A_A4
M_B_DQ40
M_B_A2
BA9
BG25
BC5
BC25
SA_DQ_41
SA_MA_4
SB_DQ_40
SB_MA_2
M_A_DQ42
M_A_A5
M_B_DQ41
M_B_A3
AU10
BA24
BC6
AU25
SA_DQ_42
SA_MA_5
SB_DQ_41
SB_MA_3
M_A_DQ43
M_A_A6
M_B_DQ42
M_B_A4
AV9
BD24
AY3
AW25
SA_DQ_43
SA_MA_6
SB_DQ_42
SB_MA_4
M_A_DQ44
M_A_A7
M_B_DQ43
M_B_A5
BA11
BG27
AY1
BB28
SA_DQ_44
SA_MA_7
SB_DQ_43
SB_MA_5
M_A_DQ45
M_A_A8
M_B_DQ44
M_B_A6
BD9
BF25
BF6
AU28
SA_DQ_45
SA_MA_8
SB_DQ_44
SB_MA_6
M_A_DQ46
M_A_A9
M_B_DQ45
M_B_A7
AY8
AW24
BF5
AW28
SA_DQ_46
SA_MA_9
SB_DQ_45
SB_MA_7
M_A_DQ47
M_A_A10
M_B_DQ46
M_B_A8
BA6
BC21
BA1
AT33
SA_DQ_47
SA_MA_10
SB_DQ_46
SB_MA_8
M_A_DQ48
M_A_A11
M_B_DQ47
M_B_A9
AV5
BG26
BD3
BD33
SA_DQ_48
SA_MA_11
SB_DQ_47
SB_MA_9
M_A_DQ49
M_A_A12
M_B_DQ48
M_B_A10
AV7
BH26
AV2
BB16
SA_DQ_49
SA_MA_12
SB_DQ_48
SB_MA_10
M_A_DQ50
M_A_A13
M_B_DQ49
M_B_A11
AT9
BH17
AU3
AW33
SA_DQ_50
SA_MA_13
SB_DQ_49
SB_MA_11
M_A_DQ51
M_A_A14
M_B_DQ50
M_B_A12
AN8
AY25
AR3
AY33
SA_DQ_51
SA_MA_14
SB_DQ_50
SB_MA_12
M_A_DQ52
M_B_DQ51
M_B_A13
AU5
AN2
BH15
SA_DQ_52
SB_DQ_51
SB_MA_13
M_A_DQ53
M_B_DQ52
M_B_A14
AU6
AY2
AU33
SA_DQ_53
SB_DQ_52
SB_MA_14
M_A_DQ54
M_B_DQ53
AT5
AV1
SA_DQ_54
SB_DQ_53
M_A_DQ55
M_B_DQ54
AN10
AP3
SA_DQ_55
SB_DQ_54
M_A_DQ56
M_B_DQ55
AM11
AR1
SA_DQ_56
SB_DQ_55
M_A_DQ57
M_B_DQ56
AM5
AL1
SA_DQ_57
SB_DQ_56
M_A_DQ58
M_B_DQ57
AJ9
AL2
SA_DQ_58
SB_DQ_57
M_A_DQ59
M_B_DQ58
AJ8
AJ1
SA_DQ_59
SB_DQ_58
M_A_DQ60
M_B_DQ59
AN12
AH1
SA_DQ_60
SB_DQ_59
M_A_DQ61
M_B_DQ60
AM13
AM2
SA_DQ_61
SB_DQ_60
M_A_DQ62
M_B_DQ61
AJ11
AM3
SA_DQ_62
SB_DQ_61
M_A_DQ63
M_B_DQ62
AJ12
AH3
SA_DQ_63
SB_DQ_62
M_B_DQ63
AJ3
SB_DQ_63
CANTIGA_GM
CANTIGA_GM
CANTIGA_GM
CANTIGA_GM
DDR SYSTEM MEMORY
DDR SYSTEM MEMORY
A
A
DDR SYSTEM MEMORY
DDR SYSTEM MEMORY
B
B
MEMORY A A DDR SYSTEM MEMORY DDR SYSTEM MEMORY B B NB5 NB5 NB5 PROJECT :

NB5

NB5

NB5

PROJECT : QT6

PROJECT : QT6

PROJECT : QT6

Quanta Computer Inc.

Quanta Computer Inc.

Quanta Computer Inc.

Size

Size

Size

Document Number

Document Number

Document Number

Custom

Custom

Custom

Rev

Rev

Rev

2A

2A

2A

Cantiga DDR2 3/5

Cantiga DDR2 3/5

Cantiga DDR2 3/5

Date:

Date:

Date:

Monday, October 29, 2007

Monday, October 29, 2007

Monday, October 29, 2007

Sheet

Sheet

Sheet

7 7

7

of

of

of

44

44

44

4

3

2

1

5 4 3 2 1 U40G U40G +1.8VSUS +1.05V 08 AP33 W28 VCC_SM_1 VCC_AXG_NCTF_1 AN33
5
4
3
2
1
U40G
U40G
+1.8VSUS
+1.05V
08
AP33
W28
VCC_SM_1
VCC_AXG_NCTF_1
AN33
V28
VCC_SM_2
VCC_AXG_NCTF_2
BH32
W26
VCC_SM_3
VCC_AXG_NCTF_3
BG32
V26
VCC_SM_4
VCC_AXG_NCTF_4
BF32
W25