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Solutions Manual to accompany the text Introduction to VLSI Circuits and Systems by John P. Uyemura Preliminary Draft June, 2001 Note: This is the first draft ofthe Solutions Manual that was transcribed from tha author's hhand-scratched notes. It has not been proofread, nor have the solutions been checked for completeness or accuracy. While most of them are reasonably accurate, errors will be found. The final version of the Solutions Manual will be available in the near fre, JOHN WILEY & SONS, INC. NEW YORK + CHICHESTER « WEINHEIM + BRISBANE « SINGAPORE « TORONTO. Chapter 1 ‘There are no problems in Chapter 1. Chapter 2 [2.1] The nFET can pass any voltage in the range [0.Vmax) Where Vina (Vg ~ Vim) with Vg the voltage on the gate. With the stated values, Vina= 5-0.7=4.3 V. If Viq> Vmax then Vout 8 restricted t0 Vinge However, the nFET passes any voltage Vin < Vmax - This gives the following answers. (2) Vin= 2 V. Vou = 2 Vi (0) Vin= 4-5 V. Vout (©) Vin= 8.5 V. Vout = 8.5 Vi (@) Vin= 0.7 V. Voue= 0.7 V. ‘The main idea is to show the effect of the threshold loss through an nFET. 3 V is limited: [2.2] For Vi, < Vmax» then the input voltage fs transmitted through the chain. If Vi, > Vmax then a threshold drop occurs in the first transistor (only) and Vmax makes it to the output. With the stated values, Vma= 8.3-0.55=2.75 V This gives the following answers. (8) Vin= 2.9 V, Vous = 2.75 V (limited): (0) Vin= 8.0 V, Vous 2.75 V (limited); (0) Viq= 1-4 V. Vout= 1.4 Vi (@) Vin= 8.1 V, Vous 2.75 V (mited). [2.3] The output of the upper FET M1 (with V, applied) is used to control the gate voltage Vo of the lower transistor M2 (with V, applied). Both are susceptible to threshold voltage Problem (2.3) 2 drops so that max(Vg) = (Vpp -Vmn) and max{Vour) = (Ve -Vm ). Using max{Vg) = (3.3-0.6 } = 2.7 V gives the following results. (@) Va= 8.3 V, Vp= 3.3 V: Vq= 2.7 V 50 Voy.= 2.7 - 0.6 = 2.1 V. 5 V, Vp= 3 V: Vg= 0.5 V so M2"is in cutoff. This makes Voy an unknown value since the transistor is an open circuit. V, Vp= 2.5 V:Vg= 2 V 80 Vout = 2 - 0. .8-V, Vp= 1.8 V: Vg= 2.7 V 50 Vout L4v. BV. [2.4] NANDS gate using an 8:1 MUX is shown in drawing below with Prob. [2.5] solution. [2.5] NORS gate using an 8:1 MUX is shown in drawing below with Prob. [2.4] solution. a Ta] pS | celery 2 | 26f$ 2off “ylo ° =o abe i abe 2 Output 2 Ourpur +3 3 i i ads 5 pele s ws 7 Problem (24) NAND3 Problem [25] NOR3 [2.6] The drawings below illustrate the XOR2 and XNOR2 MUX-based designs. To imple- ment the full-adder sum expression, we use s= (abc

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