Вы находитесь на странице: 1из 54
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Table of Contents
Page. 1
D
Page. 3
COVER
OPERATION BLOCK DIAGRAM
POWER DIAGRAM
POWER SEQUENCE
POWER RAIL
CLOCK DISTRIBUTION
D
Page. 2
Page. 4
DIAGRAM
Page. 5
Page. 6
TORINO 2
Page. 7
BOARD INFORMATION
Page. 8
CLOCK GENERATOR (CK-505)
Page. 9~10
MEROM
PCB Thinckness:1mm
Page. 11
THERMAL MONITOR
Page. 12~16
CRESTLINE (965GM)
Page. 17
DDR2 SODIMM (TOP)
CPU
: INTEL MEROM
Page. 18
DDR2 SODIMM (BOTTOM)
Page. 19
DDR2 TERMINATION
Chip Set : INTEL 965GM & ICH8-M
C
Page. 20~23
DISCRETE GFX (NB8M-SE & GDDR3)
C
Page. 24~27
ICH8-M
Remarks
: w/o INTEL AMT
Page. 28
LCD(LVDS) CONN.
2 SODIMMs
Page. 29
CRT CONN.
Page. 30
HDD & ODD CONNECTOR
Page. 31
MICOM
Page. 32
LAN CONTROLLER (10/100M)
Model Name : TORINO 2
Page. 33
ROBSON
www.kythuatvitinh.com
Page. 34
USB PORT, MDC CONN. & BLUETOOTH
PBA Name
: MAIN
Page. 35
MINI CARD SOCKET (WLAN/HSDPA/WIBRO)
Page. 36
CARDBUS CONTROLLER(1) & 4IN1
PCB Code
: BA41-00727A / 728A
Page. 37
CARDBUS CONTROLLER(2) & 1394(4P)
Page. 38
PCMCIA SOCKET
Dev. Step
: MP
Page. 39
AUDIO CODEC
Page. 40
AUDIO AMP
B
B
Revision
: 1.1
Page. 41
AUDIO JACK
Page. 42
CHARGER
T.R. Date : 2007.04.10
Page. 43
P3.3V_AUX & P5V_AUX
Page. 44
DDR2 POWER
Page. 45
CPU VRM POWER
Page. 46
P1.25V & P1.05V POWER
Page. 47
GFX CORE & P1.5V POWER
DRAW
CHECK
APPROVAL
Page. 48
SWITCHED POWER
Page. 49
POWER S/W, DMB, DEBUG & KEYBOARD CONN.
Page. 50
Page. 51
-
-
-
Page. 52
Page. 53
LEDS & TOUCHPAD
MOUNT HOLE
TEST POINTS
REVISION HISTORY
A
A
DRAW
DATE
TITLE
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
CHECK
DEV. STEP
ELECTRONICS
GUO LEI
MP
COVER
APPROVAL
REV
PART NO.
CONTENTS
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
1
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
OPERATION BLOCK DIAGRAM
mPGA479M Socket-M
FAN CONTROL
THERMAL
D
CLOCK
D
CPU
MONITOR
Page 11
GENERATOR
CPU2_THERMDA/DC
MAX6695
MEROM-4M
CK-505
Page 11
Page 9,10
Page 8
TFT_LCD
12.1" WIDE
800MHz FSB
(CeleronM:667MHz)
1280 X 800
SODIMM0 (TOP)
MAX 2 GB
1299 uFCBGA Type
CHANNEL A
Page 17
LVDS
Page 28
GMCH
667/533 MHz
CRT
VGA
965GM/PM
Discrete Gfx.
Page 29
CHANNEL B
CRESTLINE
nVidia G3-64 Family
GDDR3 128MB
64bit
667/533 MHz
SODIMM1 (BOTTOM)
MAX 2 GB
NB8M-SE
Page 12~16
K4J52324QC-BC14
PCI-E X16
Page 18
Page 27
C
C
DMI X4
C-Link0
LOM
MDC
10/100M
676 FCBGA Type
AZALIA
PCI-E
Module
PCI-E Lane2
LAN Transformer
Marvell
88E8039
Page 35
Page 34
ICH
Page 32,33
EXTERNAL MIC
PCI
3722-001822
3301-001629
ICH8 - M
AUDIO CODEC
HEADPHONE
IEEE1394
1394
82801 HBM
IDE
4pin
www.kythuatvitinh.com
CardBus
ALC262
MS / SD / MMC / xD
SATA
Page 38
Page 38
Controller
Internal MIC
Page 40
USB2.0
Page 23~26
RICOH R5C847
MultiMedia Crad
PCMCIA
Audio AMP
6in1 B’d
Page 37,38
LPC
SPI
D-Class
Page 37
RTC
MAX9715
2P
Batt.
Page 41
Page 18
B
SPI EEPROM
B
Intel ROBSON
PCI-E Lane4
AT25080
PCMCIA
Page 33
Page 24
Page 39
PCI-E Lane1
Page 30
Page 30
KBC
USB PORT 3
On TOP B’D
H8S - 2110B
HDD
ODD
MASTER
Power S/W Sub-B’D
Page 31
with MIO, LID S/W
PCI-E Lane3
GOLAN / Kerdon
HSDPA
2.5inch
802.11abg/abgn
/Wibro
USB PORT 5
SATA only
USB PORT 6
Page 36
Page 36
Space bar
KEYBOARD
A
A
DMB Module
BLUETOOTH
CAMERA
PS/2
SYNAPTICS
TOUCHPAD
DRAW
DATE
TITLE
PORT 0
PORT 1
PORT 2
PORT 4
PORT 7
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
CHECK
DEV. STEP
USB (Right)
USB (Back)
ELECTRONICS
GUO LEI
MP
MAIN
Page 35
Page 35
Page 48
Page 35
APPROVAL
REV
PART NO.
BLOCK DIAGRAM
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
2
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
RJ45
R
L
RJ11
JACK
SPEAKER
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER DIAGRAM
D
D
ALWAYS ON
KBC3_SUSPWR
KBC3_PWRON
KBC3_VRON
P3.3V_AUX
P3.3V
Clock Gen.
P3.3V_AUX
LOM
3.3V Core
0.8V CPU IO
LDO
3.3V
CTRL_18
FET
1.8V
CTRL12_25
FET
2.5V
P5.0V_AUX
P5.0V
CPU_CORE
DDR2 Power VRM
ICH8-M
USB
CPU
P1.05V
ICH8-M
CRT
Touchpad
Vcc_CORE
P5.0V
MICOM
FAN
VCCP
HDD / ODD
P1.5V
PCMCIA
HDD
VCCA
5V
AC Adapter
P3.3V
3.3V
19V
VDC
P1.05V
P3.3V_AUX
P3.3V
Crestline GM/PM
P3.3V_AUX
1.05V MCHCore
SPI
Battery DC
ICH8M
965GM
Thermal Sensor
P1.25V
1.05V FSB, PEG
3.3V VCC
MDC
ICH8-M
R5C843
11.1V
1.05V DDRHSIO, DDRDLL
MINICARD
CK505
BlueTooth
P1.5V
1.05V ME
LOM
MICOM
LEDs
P3.3V_AUX
0.7V~1.25V Vgfx
Thermal Sensor
SODIMM
LCD
P1.8V_AUX
1.25V DPLL, DMI
3.3V VCC
HDD
MINICARD
1.25V MLINK, HPLL
P12.0V_ALW
SPI
1.5V VCCDTV/CRT
P5.0V
SWITCHED POWER
1.8V DDRIO
FAN
P3.3V
1.8V LVDSIO
5V VCC
P2.5V
3.3V TV/CRT IO, PXPBG
G7xM
P3.3V
P3.3V
LCD
P5.0V_ALW
DDR2
C
P1.8V_AUX
VDC
MAX1999
3.3V SPD
3.3V VDD
12V Inverter VDC
C
P1.5V
1.8V VDDQ
P0.9V
MEROM
0.9V Vref, Vtt
P5.0V
965GM
CRT
ICH8-M
5V VCC
P3.3V_MICOM
GFX_CORE
Discrete GFX
MICOM
1.0V~1.1V VDD Core
P1.8V_AUX
P0.9V
P1.2V
P3.3V_MICOM
1.2V PEX Core, IO, PLL
MICOM
SODIMM (DDR II)
DDR II-Termination
1.2V FBA PLL
3.3V VCC
RTC Battery
P2.5V
P5.0V
965GM
1.2V Core Clock PLL Digital
5V VccB
3V
2.5V Core Clock PLL Analog
P1.8V
ICH8-M
2.5V VID PLL
P1.8V
P3.3V_AUX
1.8V FBVDDQ
MDC
P3.3V
NB8M-SE
1.8V LVDSIO
3.3V VCC
GDDR3
3.3V VDD3_3
www.kythuatvitinh.com
P5.0V
3.3V DAC VDD
AUDIO
3.3V MIO VDDQ
5V AVDD
P3.3V
3.3V DVDD
P1.25V
P1.8V
965GM
GDDR3
P3.3V
ICH8-M
1.8V VDDQ
Bluetooth
0.9V VREF
3.3V VCC
P1.2V
NB8M-SE
P5.0V
USB (2 Ports)
PRTC
RTC
5V VCC
ICH8-M Base
VccRTC
P1.05V
B
P3.3V
P5.0V
MEROM
LAN
DMB
B
965GM
VccLAN3_3
5V
1.05V AUX LDO
LAN100_SLP
P3.3V
ICH8-M
VccLAN1_05
3.3V
VccGLAN3_3
P3.3V
VccGLAN1_5
GFX_CORE
P1.5V
MINI CARD
P1.5V
NB8M-SE
CL
3.3V
VccCL3_3
1.5V
1.05V EP LDO
P3.3V_AUX
VccCL1_05
3.3V AUX
VccCL1_5
1.5V EP LDO
INTVRMEN
CPU_CORE
P5.0V_AUX
P3.3V
MEROM
Resume
CARDBUS
V5REF_Sus
3.3V
P3.3V_AUX
VccSus3_3
1.8V (Internal VR)
1.05V Sus LDO
VccSus1_05
P3.3V
VccSus1_5
1.5V Sus LDO
P3.3V
S5 / S4
S3
S0
DIAMOND
LEDS
P5.0V
P3.3V_AUX
Core
VDD
3.3V SCL, NUM, CAP
P1.5V
V5REF
AVDD
3.3V WLAN
P1.05V
P3.3V_MICOM
Vcc3_3
3.3V POWERON
Vcc1_05
3.3V ACIN
P1.25V
P3.3V
Vcc1_5
NAND FLASH
VccDMI
1.8V VCC
Rail
+V*Always
+V*AUX
+V
SUSPWR PWRON
VRON
State
Full On
ON
ON
ON
H
H
H
A
A
S3
ON
ON
OFF
H
L
L
S4
ON
OFF
OFF
H
L
L
DRAW
DATE
TITLE
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
S5
ON
OFF
OFF
L
L
L
CHECK
DEV. STEP
ELECTRONICS
GUO LEI
MP
MAIN
APPROVAL
REV
PART NO.
POWER DIAGRAM
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
3
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER SEQUENCE
Rev. 0.1
D
D
3) P12V_ALWS
2) VDC
ALWAYS
3) P5V_ALWS
PRTC
POWER
3) MICOM_P3V
7) P3.3V_AUX
INTVRMEN
7) P1.05V_AUX
PRTC
4) KBC3_RST*
RST Circuit
RES#
7) P5V_AUX
7) P1.5V_AUX
EN
7) P1.5V_CL
5) KBC3_CHKPWRSW*
POWER S/W
LAN100_SLP
ONTOP B’D
7) P1.05V_CL
1-1) PRTC_BAT
6) KBC3_SUSPWRON
* KBC3_LANRST# assert 100ms after LAN Power stable
EN
RTC
7) P1.05V_LAN
1-2) CHP3_RTCRST*
Battery
RTCRST#
8) SUSPWRGD
9) KBC3_RSMRST*
RSMRST#
10-1) CHP3_SLPS4*/S5*
SLP_M#
18) CLK3_PWRGD*
CLOCK
19) Clock Running
11) KBC3_PWRON
SLP_S3#
CK_PWRGD
10-2) CHP3_SLPS3*
SLP_S4#
CK505
C
S4_STATE#
C
13) VCCP_PWRGD
99ms Delay
17) VRM3_CPU_PWRGD
SLP_S5#
VRMPWRGD
21) CPU1_PWRGDCPU
CPUPWRGD
20) KBC3_PWRGD
PWROK
PWRGOOD
CLPWROK
CL_RST#
CPU
20) KBC3_PWRGDMCH
SUS_STAT#
PLTRST#
16) VCC_CORE
PCIRST#
RESET#
ICH8-M
15) KBC3_VRON
MICOM
22) PLT3_RST*
7) P3.3V_AUX
23) CPU1_CPURST*
www.kythuatvitinh.com
P5V_AUX & P3V_AUX
7) P5V_AUX
MAX 1999
CPURST#
PWROK
CLPWROK
7) P1.8V_AUX
22) CL3_RST*
DDR2 POWER
IMVP6
16) VCC_CORE
CL_RST#
12) P0.9V
SC486
SC452
RSTIN#
GMCH
12) P1.25V
P1.25V / P1.05V
B
B
ISL6227
12) P1.05V
Discrete
GFX.
GFX_CORE
12) GFX_CORE
SC470
P1.5V
12) P1.5V
SC486
12) P5V
Switched
12) P3.3V
Power
12) P2.5V
14) P1.8V
Switched
14) P1.2V
A
Power
A
DRAW
DATE
TITLE
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
CHECK
DEV. STEP
ELECTRONICS
GUO LEI
MP
MAIN
APPROVAL
REV
PART NO.
POWER SEQUENCE
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
4
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Timing Diagram, no ME
Rev. 0.2 Phil 2006-9-21
G3
S5
S5
S3
S3
S0
S0
S0
S3
S3
S4 / S5
D
D
VDC
VDC
Px.xV_ALW
Px.xV_ALW
P3.3V_MICOM
P3.3V_MICOM
ADT3_SEL
ADT3_SEL
>= 20ms
KBC3_RST*
KBC3_RST*
>= 16ms, ICH internal debounce
KBC3_CHKPWRSW#
KBC3_CHKPWRSW#
KBC3_SUSPWRON
KBC3_SUSPWRON
Px.xV_AUX
Px.xV_AUX
SUSPWRGD
SUSPWRGD
KBC3_LANLOWPWR#
Due to Pull-up
to P3.3V_AUX
KBC3_LANLOWPWR#
>= 5ms
KBC3_RSMRST*
KBC3_RSMRST*
Due to enabled wake event, such as PWRBTN#
1 ~ 2 RTCCLK
CHP3_SLPS5*
CHP3_SLPS5*
1 ~ 2 RTCCLK, Refer to D31:F0:A4h bits 5:3
1 ~ 2 RTCCLK
CHP3_SLPS4*
CHP3_SLPS4*
Raise at the same time as SLPS4#
CHP3_S4STATE*
CHP3_S4STATE*
1 ~ 2 RTCCLK
1 ~ 2 RTCCLK
C
C
CHP3_SLPS3*
CHP3_SLPS3*
Raise at the same time as SLPS3#
CHP3_SLPM*
CHP3_SLPM*
KBC3_PWRON
KBC3_PWRON
P5.0V / P3.3V / P1.5V
P5.0V / P3.3V / P1.5V
P1.25V / P2.5V
P1.25V / P2.5V
P0.9V
P0.9V
P1.05V
P1.05V
VCCP_PWRGD
VCCP_PWRGD
www.kythuatvitinh.com
P1.8V / P1.2V
P1.8V / P1.2V
KBC3_VRON
KBC3_VRON
VCC_CORE
VCC_CORE
>= 0
VRM3_CPU_PWRGD
VRM3_CPU_PWRGD
0 ~ 100ns
CLK3_PWRGD
CLK3_PWRGD
>= 3ms
KBC3_PWRGD
KBC3_PWRGD
>= 99ms
B
KBC3_PWRGDMCH
KBC3_PWRGDMCH
B
CPU1_CPUPWRGD
CPU1_CPUPWRGD
>= 0s
CL3_RST0*
CL3_RST0*
32 ~ 38 RTCCLK
2 ~ 4 RTCCLK
CHP3_SUSSTAT*
CHP3_SUSSTAT*
2 ~ 3 RTCCLK
5 ~ 7 RTCCLK
PLT3_RST*
PLT3_RST*
PCI3_RST*
PCI3_RST*
>= 1ms
CPU1_CPURST*
CPU1_CPURST*
>= 1ms
<= 100us
SPI Signals
soft strap read
BIOS Boot
SPI Signals
CL0 (MCH-ICH)
MCH soft straps
Prepare for ME off
CL0 (MCH-ICH)
DMI
CPU_RST_DONE/ACK
BIOS Boot
SMM SLP_EN Write
Sx Entry Req
Sx Entry Ack
L2 / L3
DMI
BSEL[2:0]
Valid
Toggling (Valid)
BSEL[2:0]
0 ~
100ns after VRM3_PWRGD Low
CHP3_CPUSTP*
CHP3_CPUSTP*
2 ~ 10 RTCCLK
CHP3_PCISTP*
CHP3_PCISTP*
0 ~ 1ms
CLK0_HOST_CPU
Toggling (Valid)
CLK0_HOST_CPU
A
A
CLK0_HOST_GMCH
Toggling (Valid)
CLK0_HOST_GMCH
DRAW
DATE
TITLE
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
CHECK
DEV. STEP
ELECTRONICS
GUO LEI
MP
MAIN
APPROVAL
REV
PART NO.
TIMING DIAGRAM
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
5
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CLOCK DISTRIBUTION
Rev. 0.1
BSEL(2:0)
D
CLK0_HOST_CPU/CPU#
D
200
MHz
MEROM
CPU
BSEL
CK505
CLK3_PWRGD
FSB
667/533 MHz
CLK0_HOST_GMCH/GMCH#
CPU_STP#
Main PLL
200
MHz
HPLL
333/266 MHz
CLK1_MCLK0/0#
SSC
MPLL
GMCH3_CLKREQ#
965GM / PM
ON B’D MEM
333/266 MHz
CLK1_MCLK1/1#
100
MHz
CLK1_MCH3GPLL/3GPLL#
3GPLL
Crestline
333/266 MHz
CLK1_MCLK2/2#
CLK1_DREFCLK/CLK#
96
MHz
GMCH
48/96MHz
DPLLA
SODIMM #0
NO SSC
333/266 MHz
CLK1_MCLK3/3#
100
MHz
CLK1_DREFSSC/SSC#
DPLLB
CLK1_27M
CLK1_27M_SS
C
C
PCIE Ext. GFX.
100
MHz CLK1_PCIEGFX/GFX#
X16 PEG
X4 DMI
MDC3_BCLK
CLK1_PCIEICH/ICH#
MDC
100
MHz
PCIEPLL
GMCH3_CLKREQ#
AUD3_BCLK
HD 24 MHz
100MHz
HD Audio
100
MHz
CLK1_MCH3GPLL/3GPLL#
/33MHz
SATAPLL
SEL_LCDCLK#
SSC
CLK3_USB48
SPI3_CLK
PCI_STP#
48
MHz
SPI
USBPLL
17.86 / 31.25 MHz
www.kythuatvitinh.com
ICH8-M
CLK3_ICH14
14.318 MHz
RTC Clock
CLK3_PCLKICH
33
MHz
32.768 KHz
32.768 KHz
OSC
2801-003856
MINIPCIE3_CLKREQ1 / 2#
MINI CARD (WLAN)
100
MHz
CLK1_MINIPCIE1 / 1#
B
B
MINI CARD (HSDPA)
100
MHz
CLK1_MINIPCIE2 / 2#
OPTION
LAN3_CLKREQ#
25 MHz
100
MHz
CLK1_PCIELOM/PCIELOM#
LAN PHY
2801-003892
ITP_EN
ROBSON
100
MHz
CLK1_PEXNAND/FEXNAND#
OPTION
33
MHz
CLK3_PCLKMICOM
MICOM
10 MHz
14 MHz
1394 Clock
A
OSC
A
33
MHz
CLK3_PCLKCB
CARDBUS
24.576 MHz
DRAW
DATE
TITLE
14.318 MHz
2801-003898
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
2801-003730
CHECK
DEV. STEP
ELECTRONICS
33
MHz
CLK3_DBGLPC
GUO LEI
MP
MAIN
DEBUG PORT
APPROVAL
REV
PART NO.
CLOCK DISTRIBUTION
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
6
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
 

4

 

3

 

2

 

1

   

SAMSUNG PROPRIETARY

   

THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG ELECTRONICS CO’S PROPERTY. DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS EXCEPT AS AUTHORIZED BY SAMSUNG.

 

BOARD INFORMATION

 

D

 

SCHEMATIC ANNOTATIONS AND BOARD INFORMATION

 

D

 

PCI Devices

Crystal / Oscillator

 

Devices

IDSEL#

REQ/GNT#

Interrupts

TYPE

FREQUENCY

DEVICE

 

USAGE

 

Cardbus

AD25

0

E,F,G

Crystal

32.768KHz

ICH8-M

 

Real Time Clock

 
 

Crystal

10MHz

 

MICOM

H8S/2110BV

Crystal

14.318MHz

CLOCK-Generator

CK-505

 

Crystal

24.576MHz

Cardbus Controller

1394

 

Crystal

25MHz

 

LAN

 

LAN

 
   

Voltage Rails

   
 

VDC

   

CPU_CORE

P1.05V

Primary DC system power supply (7 to 21V) Core voltage for Processor (1.308~1.068V) Processor System Bus(PSB) Termination (1.05V)

 

CPU Core Voltage Table

 

IMVP-6

 
 

GMCH & ICH8 Core Voltage

 

GFX_CORE

P1.8V_AUX

P0.9V

Core voltage for NB8M-SE (1.0 ~ 1.1V) 1.8V power rail for DDR2 (off in S4-S5) 0.9V switched power rail (off in S3-S5)

         

Active Mode

 

Active/Deeper Sleep

   

Deeper Sleep/Extended Deeper Sleep Dual Mode Region

 

C

P1.8V

1.8V power rail for GDDR3 (off in S3-S5)

Dual Mode Region

C

P1.2V

P1.5V

1.2V switched power rail (off in S3-S5) 1.5V switched power rail (off in S3-S5)

   
     

P2.5V

VID(6:0)

Voltage

VID(6:0)

Voltage

 

VID(6:0)

Voltage

P3.3V

P5.0V

P3.3V_AUX

P5V_AUX

PRTC_BAT

P3.3V_MICOM

P5.0V_ALW

P12.0V_ALW

2.5V switched power rail (off in S3-S5) 3.3V switched power rail (off in S3-S5) 5.0V switched power rail (off in S3-S5) 3.3V power rail (off in S4-S5) 5.0V power rail (off in S4-S5)

3.0V power rail (ALWAYS ON)

3.3V always on power rail for MICOM

5V power rail (Always On)

12V power rail (Always On)

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

1

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1 0

1 0

1 0

1 0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

1

1

0

1 0

0

0

0

1

1

1

1

0

1 1

1

1

1

1

0

1

0

1

1

0

0

1 1

1 0

0

0

0

0

0

0

0

1

1

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

0 V

1.0000

1 V

0

1

0

1

0

1 1

0

1

0

1

0

1

0

1

0

1

V

V

V

V

V

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

0.8375

0.8250

0.8125

0.8000

0.7875

V

V

V

V

V

V

V

V

V

V

V

1 0

1 0

1 0

1 0

0

0

0

1

1

1

1

1

1

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1

1

1

1 1

0

0

0

1 0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

1 1

0

1 0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

1

V

1 V

0.4875

0.4750

0.4625

0.4500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

V

V

V

1 V

V

0

V

1

V

0

V

1

V

V

1

V

1

V

0

V

1

V

1

V

0

V

0

 
   

www.kythuatvitinh.com

Address

Hex

Bus

I C / SMB Address

Devices

2

 
 

0

0

1

0

0

1

0

1.2750

V

0

1

1

1

0

1

0

0.7750

V

 

1

1

0

0

0

1

1

0.2625

V

 
 

ICH8

Master

-

SMBUS Master

0

0

1

0

0

1

1

1.2625

V

0

1

1

1

0

1

1

0.7625

V

1

1

0

0

1

0

0

0.2500

V

   

0

0

1

0

1

0

0

1.2500

V

0

1

1

1

1

0

0

0.7500

V

1

1

0

0

1

0

1

0.2375

V

 

SODIMM0

1010 000X

A0h

-

     

SODIMM1

CK-505 (Clock Generator)

1010

1101

010X

001x

A4h

D2h

-

Clock, Unused Clock Output Disable

 

0

0

0

0

0

0

1

1

1 1

0

0

0

1

1

1

0

1

1

1

1

0

1

1

1.2375

1.2250

1.2125

V

V

V

0

0

0

1

1

1

1

1

1 1

1

1

1

1

1

1

0

1

1

1

1

0

1 1

0.7375

0.7250

0.7125

V

V

V

 

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

0

1

1

0

0

1

1 0

0.2250

0.2125

0.2000

V

V

V

B

 

MICOM

Master

-

SMBUS Master

0

0

1

1

0

0

0

1.2000

V

1

0

0

0

0

0

0

0.7000

V

1

1

0

1

0

0

1

0.1875

V

B

 

BATTERY

0001

011X

16h

0

0

1

1

0

0

1

1.1875

V

1

0

0

0

0

0

1

0.6875

V

1

1

0

1

0

1

0

0.1750

V

-

     

EMC2102(Thermal Sensor)

0111

101X

7Ah

Thermal Sensor

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

1

0

1

1.1750

1.1625

1.1500

1.1375

V

V

V

V

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1 0

1 0

0

0

0 0.6750

1 0.6625

0 0.6500

1 0.6375

V

V

V

V

 

1

1

1

1

1

1

1

1

0

0

0

0

0.1625

1

1

1 0.1500

0

V

0

V

1 V

1

1

0

0

1 0.1375

1

1 V

1 0.1250

0

1

 
 

0

0

1

1

1

1

0

1.1250

V

1

0

0

0

1

1

0

0.6250

V

1

1

0

1

1

1

1

0.1125

V

0

0

1

1

1

1

1

1.1125

V

1

0

0

0

1

1

1

0.6125

V

1

1

1

0

0

0

0

0.1000

V

 

USB PORT Assign

 

0

1

0

0

0

0

0

1.1000

V

1

0

0

1

0

0

0

0.6000

V

1

1

1

0

0

1

0 0.0875

V

 

0

1

0

0

0

0

1

1.0875

V

1

0

0

1

0

0

1

0.5875

V

1

1

1

0

0

0

1 0.0750

V

PORT NUMBER

ASSIGNED TO

0

0

1

1

0

0

0

0

0

0

1

1

0

1

1.0750

1.0625

V

V

1

1

1 1

0

0

0

0

1

1

0

0

0 1

0.5750

0.5625

V

V

V

1

1

1

1

1

1

0

0

0 0.0625

1 0.0500

1

1

0

0

V

V

V

0

1

SYSTEM PORT A

SYSTEM PORT B

0

0

0

1

1

1

0

0

0

0

0

0

1

1

1

0

0

1

0

1

0

1.0500

1.0375

1.0250

V

V

V

1

1 0

0

0

1 0

1 0

1 1

0

0

0

1

1

1 1

1 0

0

0.5500

0.5375

0.5250

V

V

1

1

1

1

1

1

1

1

1

0

0

0

1

0.0375

1 0.0250

0

1

1

0

1

1 0.0125

1

V

V

 

2

3

4

DMB CARD

MINIPCI-E

BLUETOOTH

0

1 1

0

0

1 1

1

1

1

1.0125

V

1 1

0

1 0 1

0

0

0

1

1 1

0

0

1

1

0

0

1

0

0.5125

0.5000

V

V

1

1

1

1 1

1

1

1

1

1

1

1

1

0

0

0

1 0

0

1

0

1

0

0.0000

0.0000

0.0000

V

V

V

 

5

WIBRO SIM CARD

 

Deeper Slp

1

1

1

1

0

1

1

0.0000

V

6

HSDPA

 

Active

1

1

1

1

1

0

0

0.0000

V

7

CAMERA

DPRSLPVR

0

DPRSLPVR

1

1

1

1

1

1

0

1

0.0000

V

 

DPRSTP*

1

 

DPRSTP*

0

1

1

1

1

1

1

0

0.0000

V

 

1

1

1

1

1

1

1

0.0000

V

 
 

System Power States

 

PSI2*

0 or 1

PSI2*

0 or 1

*"1111111" : 0V power good asserted.

A

CHP3_SLPS1*

S1, Powered-On-Suspend(POS) : In this state, all clocks(except the 32.768KHz clock) are stopped.

 

A

 

The system context is maintained in system DRAM. Power is maintained to PCI, the CPU, memory controller, memory, and all other criticial subsystems. Note that this state does not preclude power being removed from non-essential devices, such as disk drives. During this state, CPU can be selected for either Deep Sleep or Deeper Sleep.

 

DRAW

ZHOU JUN

DATE

4/10/2007

TITLE

TORINO 2

SAMSUNG

 

CHP3_SLPS3*

In Deeper Sleep, CPU voltage reduced in this state to reduce the leakage power. S3, Suspend-To-RAM(STR) : The system context is maintained in system DRAM, but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks stop except RTC clock.

 

CHECK

GUO LEI

DEV. STEP

MP

MAIN

 

ELECTRONICS

CHP3_SLP4S* S4, Suspend-To-Disk(STD) : The Context of the system is maintained on the disk. All power is then shut off to the system except for the logic required to resume. Externally appears same as S5, but may have different wake events.

 

APPROVAL

KEVIN LEE

REV

1.1

BOARD INFORMATION

 

PART NO.

BA41-00727/8A

CHP3_SLPS5*

S5, Soft Off(SOFF) : System context is not maintained. All power is shut off except for the logic required to restart. A full boot is required when waking.

     
 

MODULE CODE

LAST EDIT

March 28, 2007 3:33:29 PM

PAGE

7

OF

54

 

4

 

3

 

2

 

1

4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
P3.3V
TP15281
MMZ1608S121AT
C744
C774
B524
C772
C743
C742
C768
C766
C769
C773
C771
C767
C770
10000nF
10000nF
U20
10nF
10nF
100nF
100nF
100nF
100nF
10000nF
100nF
100nF
100nF
6.3V
6.3V
SLG8SP513
6.3V
19
4
VDD_IO
VDD_REF
33
16
VDD_SRC_IO1
VDD_48
43
9
VDD_SRC_IO2
VDD_PCI
52
23
VDD_SRC_IO3
VDD_PLL3
56
VDD_CPU_IO
27
46
VDD_PLL3_IO
VDD_SRC
EXT_GFX
62
VDD_CPU
37-B2
R189
33
5%
55
CLK3_FM48
NC
25-A2
R188
33
5%
61
10-D4
CLK3_USB48
CPU0
CLK0_HOST_CPU
TP15280
R190
2.2K 5%
17
60
10-D4
CPU1_BSEL0
USB_FS_A
CPU0#
CLK0_HOST_CPU#
10-C4
13-A3
64
CPU1_BSEL1
FSB_TESTMODE
TP15279
10-C4
13-A3
R199
10K
1%
5
58
12-B2
CPU1_BSEL2
REF_FS_C_TEST_SEL
CPU1_MCH
CLK0_HOST_GMCH
10-C4
13-A3
R200
33
5%
57
12-B2
CLK3_ICH14
CPU1_MCH#
CLK0_HOST_GMCH#
25-A2
44
CHP3_CPUSTP#
CPUSTOP#
25-D2
45
40
R214
0
5%
CHP3_PCISTP#
PCISTOP#
SRC11_CLKREQH#
CLK1_MINIPCIE2
25-D2
39
R213
0
5%
35-C2
SRC11#_CLKREQG#
CLK1_MINIPCIE2#
TP15278
R201
100
63
35-C2
C
CLK3_PWRGD
CLKPWRGD_PWRDN#
C
25-B2
41
SRC10
CLK1_PCIEICH
TP15277
R192
33
5%
14
42
25-C1
CLK3_PCLKICH
PCIF_5_ITP_EN
SRC10#
CLK1_PCIEICH#
25-C3
25-C1
TP15282
R194
33
5%
13
37
R210
0
CLK3_PCLKMICOM
PCI_4_SEL_LCDCLK#
SRC9
CLK1_PEXNAND
31-B4
38
R211
0
33-B4
TP15275
SRC9#
CLK1_PEXNAND#
R196
33
5%
12
33-B4
CLK3_PCLKCB
PCI_3
36-A4
54
TP15276
SRC8_ITP
CLK1_PCIELOM
R197
33
5%
11
53
32-D4
CLK3_DBGLPC
PCI_2
SRC8#_ITP#
CLK1_PCIELOM#
49-B4
32-D4
TP15272
TP16368
NO_STUFF
13-B4
10
51
R569
0
32-C4
GMCH3_CLKREQ#
PCI_1_CLKREQ_B#
SRC7_CLKREQF#
LAN3_CLKREQ#
50
35-C4
SRC7#_CLKREQE#
MINIPCIE3_CLKREQ1#
25-B2
8
CHP3_SATACLKREQ#
PCI_0_CLKREQ_A#
48
SRC6
CLK1_MINIPCIE1
7
47
35-C4
CLK3_SMBCLK
SCL
SRC6#
CLK1_MINIPCIE1#
8-A2
8-A2
17-B4
17-C4
18-C4
18-B4
6
35-C4
CLK3_SMBDATA
SDA
www.kythuatvitinh.com
34
SRC4
CLK1_MCH3GPLL
TP15268
3
35
13-C1
TP15269
XTAL_IN
SRC4#
CLK1_MCH3GPLL#
2
13-C1
XTAL_OUT
31
SRC3_CLKREQC#
18
32
VSS_48
SRC3#_CLKREQD#
Y500
59
VSS_CPU
22
28
14.31818MHz
VSS_IO
SRC2
CLK1_SATA
15
29
24-B4
VSS_PCI
SRC2#
CLK1_SATA#
1
2
26
24-B4
SEL_LCDCLK#
Pin20
Pin21
Pin24
Pin25
VSS_PLL3
1
24
INT_GFX
INT_GFX
R208
0
VSS_REF
LCDCLK_27M
CLK1_DREFSSCLK
30
25
R209
0
13-C1
0 DOT96
DOT96#
LCDCLK
LCDCLK#
2801-004518
VSS_SRC1
LCDCLK#_27M_SS
CLK1_DREFSSCLK#
36
13-C1
1 SRC0
SRC0#
27MHz
27MHz_SS
VSS_SRC2
49
20
R751
301
1%
VSS_SRC3
SRC0_DOT96
CLK3_27M
B
21
EXT_GFX
EXT_GFX
R752
301
1%
20-B1
B
INT_GFX
3.3V to 1.2V Translation for G72M
SRC0#_DOT96#
CLK3_27M_SS
C273
C274
20-B1
0.033nF
0.033nF
INT_GFX
INT_GFX
R206
0
CLK1_DREFCLK
1205-003156
R207
0
13-C1
CLK1_DREFCLK#
SMBUS Address "D2h"
13-C1
EXT_GFX
EXT_GFX
R750
0
CLK1_PCIEGFX
R749
0
20-A4
CLK1_PCIEGFX#
20-A4
P1.05V
PCI2 is multiple used as TME on IDTCV179
R89
0
Place 14.318MHz within
IDTCV179 P/N: 1205-003159
R88
1K
500mils of Clock chip
R21
0
R93
1K
P3.3V
P3.3V
EXT_GFX
EXT_GFX
EXT_GFX
EXT_GFX
R711
CLK REQ
Mapping
Device
FSA
FSB
FSC
10K
HOST CLK
R754
R753
A#
SRC_2
SATA
TP1065
CPU
BSEL0
BSEL1
BSEL2
10K
10K
B#
SRC_4
GMCH
RHU002N06
1
G
0
0
0
266
MHz
Q506
E#
SRC_6
MiniCard(WLAN)
0
0
1
333
MHz
D
S
SMB3_CLK
CLK3_SMBCLK
25-D2
27-C3
35-C1
35-C3
3
2
18-C4
17-C4
8-C4
0
1
0
200
MHz
F#
SRC_8
GbE LAN (100M: N/A)
1
G
0
1
1
400
MHz
A
A
S
25-D2
27-C3
35-C1
35-C3
D
1
0
0
133
MHz
SMB3_DATA
CLK3_SMBDATA
3
2
18-B4
17-B4
8-B4
1
0
1
100
MHz
DRAW
DATE
TITLE
RHU002N06
C932
C933
ZHOU JUN
4/10/2007
SAMSUNG
1
1
0
166
MHz
Q507
TORINO 2
0.33nF
0.33nF
CHECK
DEV. STEP
1
1
1
RSVD
ELECTRONICS
GUO LEI
MP
MAIN
APPROVAL
REV
PART NO.
CLOCK GENERATOR
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
8
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
NO_STUFF
NO_STUFF
10K 1%R917
1%10KR918
10KR191
1%
1%10KR193
1%R195
10K
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
CPU SOCKET : MEROM
P1.05V
CPU500-2
R37
CPU500-1
MEROM-SOCKET
56
MEROM-SOCKET
2 / 4
CPU1_D#(15:0)
CPU1_D#(47:32)
1 / 4
12-D4
0 E22
Y22
32
12-D4
CPU1_A#(16:3)
D0*
D32*
12-D1
3 J4
H1
12-C2
1 F24
AB24
33
A3*
ADS*
CPU1_ADS#
D1*
D33*
4 L5
E2
2 E26
V24
34
A4*
BNR*
CPU1_BNR#
D2*
D34*
5 L4
G5
12-C2
12-C2
3 G22
V26
35
A5*
BPRI*
CPU1_BPRI#
D3*
D35*
6 K5
4 F23
V23
36
A6*
D4*
D36*
7 M3
F1
5 G25
T22
37
A7*
BR0*
CPU1_BREQ#
D5*
D37*
8 N2
12-C2
6 E25
U25
38
C
A8*
D6*
D38*
C
9 J1
H5
12-B2
7 E23
U23
39
A9*
DEFER*
CPU1_DEFER#
D7*
D39*
10 N3
F21
8 K24
Y25
40
A10*
DRDY*
CPU1_DRDY#
D8*
D40*
11 P5
E1
12-B2
9 G24
W22
41
A11*
DBSY*
CPU1_DBSY#
D9*
D41*
12 P2
12-B2
10 J24
Y23
42
A12*
D10*
D42*
TP15292
13 L2
D20
11 J23
W24
43
A13*
IERR*
D11*
D43*
14 P4
B3
24-C2
12 H22
W25
44
A14*
INIT*
CPU1_INIT#
D12*
D44*
15 P1
13 F26
AA23
45
A15*
D13*
D45*
R1
H4
K22
AA24
46
16 A16*
LOCK*
CPU1_LOCK#
14 D14*
D46*
M1
12-B2
15
H23
AB25
47
CPU1_ADSTB0#
ADSTB0*
D15*
D47*
12-C2
C1
12-B2
J26
Y26
12-B2
RESET*
CPU1_CPURST#
CPU1_DSTBN0#
DSTBN0*
DSTBN2*
CPU1_DSTBN2#
F3
12-A2
12-B4
12-B2
H26
AA26
12-B2
RS0*
CPU1_RS0#
CPU1_DSTBP0#
DSTBP0*
DSTBP2*
CPU1_DSTBP2#
F4
12-A2
12-B2
H25
U22
12-B2
CPU1_A#(35:17)
RS1*
CPU1_RS1#
CPU1_DBI0#
DINV0*
DINV2*
CPU1_DBI2#
12-D1
17
Y2
G3
12-A2
A17*
RS2*
CPU1_RS2#
CPU1_D#(31:16)
CPU1_D#(63:48)
18
U5
G2
12-B2
12-D4
16
N22
AE24
48
12-D4
A18*
TRDY*
CPU1_TRDY#
D16*
D48*
19
R3
17
K25
AD24
49
A19*
D17*
D49*
www.kythuatvitinh.com
20
W6
G6
18
P26
AA21
50
A20*
HIT*
CPU1_HIT#
D18*
D50*
21
U4
E4
12-B2
19
R23
AB22
51
A21*
HITM*
CPU1_HITM#
D19*
D51*
22
Y5
12-B2
20
L23
AB21
52
A22*
D20*
D52*
23
U1
A6
24-C2
21
M24
AC26
53
A23*
A20M*
CPU1_A20M#
D21*
D53*
24
R4
A5
22
L22
AD20
54
A24*
FERR*
CPU1_FERR#
D22*
D54*
25
T5
C4
24-C2
24-C2
23
M23
AE22
55
26 A25*
IGNNE*
CPU1_IGNNE#
24 D23*
D55*
T3
P25
AF23
56
A26*
D24*
D56*
27 W2
D5
24-C2
25 P23
AC25
57
A27*
STPCLK*
CPU1_STPCLK#
D25*
D57*
28 W5
C6
24-C2
26 P22
AE21
58
A28*
LINT0
CPU1_INTR
D26*
D58*
29 Y4
B4
24-C2
27 T24
AD21
59
A29*
LINT1
CPU1_NMI
D27*
D59*
30 U2
A3
28 R24
AC22
60
A30*
SMI*
CPU1_SMI#
D28*
D60*
31 V4
24-C2
29 L25
AD23
61
A31*
CPU1_REQ#(4:0)
D29*
D61*
32 W3
K3
0
12-A2
30 T25
AF22
62
A32*
REQ0*
D30*
D62*
B
33 AA4
H2
1
31 N25
AC23
63
B
A33*
REQ1*
D31*
D63*
34 AB2
K2
2
12-B2
L26
AE25
12-B2
A34*
REQ2*
CPU1_DSTBN1#
DSTBN1*
DSTBN3*
CPU1_DSTBN3#
35 AA3
J3
3
12-B2
M26
AF24
12-B2
A35*
REQ3*
CPU1_DSTBP1#
DSTBP1*
DSTBP3*
CPU1_DSTBP3#
V1
L1
4
12-B2
N24
AC20
12-B2
CPU1_ADSTB1#
ADSTB1*
REQ4*
CPU1_DBI1#
DINV1*
DINV3*
CPU1_DBI3#
12-C2
A
A
DRAW
DATE
TITLE
ZHOU JUN
4/10/2007
SAMSUNG
TORINO 2
CHECK
DEV. STEP
ELECTRONICS
GUO LEI
MP
MAIN
APPROVAL
REV
PART NO.
MEROM(1)
KEVIN LEE
1.1
BA41-00727/8A
MODULE CODE
LAST EDIT
9
54
March 28, 2007 3:33:29 PM
PAGE
OF
4
3
2
1
0
ADDR GROUP 1
ADDR GROUP
ICH
CONTROL
DATA GRP 1
DATA GRP 0
DATA GRP 3
DATA GRP 2
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CPU SOCKET : MEROM
D
D
CPU500-3
CPU_CORE
CPU_CORE
P1.5V
MEROM-SOCKET
A22
B26
CLK0_HOST_CPU
BCLK0
VCCA_1
8-C1
A21
C26
CLK0_HOST_CPU#
BCLK1
VCCA_2
C4
C5
8-C1
10nF
10000nF
D7
K6
A11
K1
CPU1_SLP#
SLP*
VCCP_1
25V
6.3V
VSS_1
VSS_120
12-B4
B5
J6
A14
J5
CPU1_DPSLP#
DPSLP*
VCCP_2
VSS_2
VSS_119
24-C2
E5
M6
A16
J25
CPU1_DPRSTP#
DPRSTP*
VCCP_3
VSS_3
VSS_118
Placed as close as possible to
13-B1
24-C2
D24
N6
A19
J22
CPU1_DPWR#
DPWR*
VCCP_4
VSS_4
VSS_117
each of the four VCCA pins.
12-B2
D6
T6
A2
A10
AE9
J2
CPU1_PWRGDCPU
PWRGOOD
VCCP_5
VSS_5
VCC_1
VCC_51
VSS_116
24-C2
AE6
R6
A23
A12
AF10
H6
CPU1_PSI#
PSI*
VCCP_6
VSS_6
VCC_2
VCC_52
VSS_115
45-B4
K21
A25
A13
AF12
H3
CPU1_VID(6:0)
VCCP_7
VSS_7
VCC_3
VCC_53
VSS_114
P1.05V
45-B4
6
AE2
J21
A4
A15
AF14
H24
VID_6
VCCP_8
VSS_8
VCC_4
VCC_54
VSS_113
5
AF3
M21
A8
A17
AF15
H21
VID_5
VCCP_9
VSS_9
VCC_5
VCC_55
VSS_112
P1.05V
4
AE3
N21
AA11
A18
AF17
G4
VID_4
VCCP_10
VSS_10
VCC_6
VCC_56
VSS_111
3
AF4
T21
EC5
AA14
A20
AF18
G26
VID_3
VCCP_11
VSS_11
VCC_7
VCC_57
VSS_110
2
AE5
R21
330uF
AA16
A7
AF20
G23
VID_2
VCCP_12
VSS_12
VCC_8
VCC_58
VSS_109
1
AF5
V21
2.5V
AA19
A9
AF9
G1
R36
IF PROCHOT* USED, 56ohm -> 68ohm
VID_1
VCCP_13
VSS_13
VCC_9
CPU500-4
VCC_59
VSS_108
AD6
W21
AL
0
AA2
AA10
B10
F8
56
VID_0
3 / 4
VCCP_14
VSS_14
VCC_10
VCC_60
VSS_107
1%
V6
AA22
AA12
B12
F5
VCCP_15
VSS_15
VCC_11
MEROM-SOCKET
VCC_61
VSS_106
TP16322
D21
G21
AA25
AA13
B14
F25
CPU1_PROCHOT#
PROCHOT*
VCCP_16
VSS_16
VCC_12
VCC_62
VSS_105
A24
AA5
AA15
B15
F22
CPU2_THERMDA
THRMDA
VSS_17
VCC_13
VCC_63
VSS_104
11-C2
B25
AC1
AA8
AA17
B17
F2
CPU2_THERMDC
THRMDC
PREQ*
VSS_18
VCC_14
4 / 4
VCC_64
VSS_103
P1.05V
11-C2
C7
AC2
AB1
AA18
B18
F19
C
CPU1_THRMTRIP#
THERMTRIP*
PRDY*
VSS_19
VCC_15
VCC_65
VSS_102
C
11-B3
13-B1
24-C2
AC4
AB11
AA20
B20
F16
BPM3*
VSS_20
VCC_16
VCC_66
VSS_101
C21
AD1
AB13
AA7
B7
F13
CPU1_BSEL2
BSEL2
BPM2*
VSS_21
VCC_17
VCC_67
VSS_100
P1.05V
8-C4
13-A3
B23
AD3
AB16
AA9
B9
F11
R148
CPU1_BSEL1
BSEL1
BPM1*
VSS_22
VCC_18
VCC_68
VSS_99
8-C4
13-A3
B22
AD4
AB19
AB10
C10
E8
1K
CPU1_BSEL0
BSEL0
BPM0*
VSS_23
VCC_19
VCC_69
VSS_98
1%
8-C4
13-A3
AB26
AB12
C12
E6
TP15067 AD26
TP15068
VSS_24
VCC_20
VCC_70
VSS_97
AC5
R151
27.4 1%
AB4
AB14
C13
E3
GTLREF
TCK
VSS_25
VCC_21
VCC_71
VSS_96
AA6
R134
150
1%
AB8
AB15
C15
E24
54.9 1% TP15063
TDI
VSS_26
VCC_22
VCC_72
VSS_95
R136
Y1
AB3
AC11
AB17
C17
E21
R147
COMP3
TDO
VSS_27
VCC_23
VCC_73
VSS_94
TP15064
R137
27.4
1%
AA1
AB5
R135
40.2
5%
AC14
AB18
C18
E19
2K
COMP2
TMS
VSS_28
VCC_24
VCC_74
VSS_93
TP15065
1%
R132
54.9
1%
U26
AB6
R133
475
1%
AC16
AB20
C9
E16
TP15066
COMP1
TRST*
TP15072
VSS_29
VCC_25
VCC_75
VSS_92
R131
27.4
1%
R26
C20
R38
0
AC19
AB7
D10
E14
COMP0
DBR*
ITP3_SYSRST#
VSS_30
VCC_26
VCC_76
VSS_91
25-D2
AC21
AB9
D12
E11
VSS_31
VCC_27
VCC_77
VSS_90
AF7
D2
AC24
AC10
D14
D8
CPU1_VCCSENSE
VCCSENSE
RSVD_1
VSS_32
VCC_28
VCC_78
VSS_89
10-A3
45-B4
AE7
F6
AC3
AC12
D15
D4
CPU1_VSSSENSE
VSSSENSE
RSVD_2
VSS_33
VCC_29
VCC_79
VSS_88
10-A3
45-B4
D3
AC6
AC13
D17
D26
RSVD_3
VSS_34
VCC_30
VCC_80
VSS_87
www.kythuatvitinh.com
NO_STUFF
NO_STUFF
D22
AC8
AC15
D18
D23
RSVD_4
VSS_35
VCC_31
VCC_81
VSS_86
TP15073
COMP0,2(COMP1,3) should be
R7
1K
C23
M4
AD11
AC17
D9
D19
TP15062
TEST1
RSVD_5
VSS_36
VCC_32
VCC_82
VSS_85
R8
1K
D25
N5
AD13
AC18
E10
D16
connected with Zo=27.4ohm(55ohm)
TEST2
RSVD_6
VSS_37
VCC_33
VCC_83
VSS_84
1%
C24
T2
AD16
AC7
E12
D13
trace shorter than 1/2" to their
TEST3
RSVD_7
VSS_38
VCC_34
VCC_84
VSS_83
AF26
V3
AD19
AC9
E13
D11
TEST4
RSVD_8
VSS_39
VCC_35
VCC_85
VSS_82
respective Banias socket pins.
AF1
B2
AD2
AD10
E15
D1
TEST5
RSVD_9
VSS_40
VCC_36
VCC_86
VSS_81
A26
C3
AD22
AD12
E17
C8
TEST6
RSVD_10
VSS_41
VCC_37
VCC_87
VSS_80
AB23
AD14
E18
C5
VSS_42
VCC_38
VCC_88
VSS_79
GTLREF : Keep the Voltage divider within 0.5"
of the First GTLREF0 with Z0= 55 ohm trace
Minimize coupling of any switching signals to this net
AD25
AD15
E20
C25
VSS_43
VCC_39
VCC_89
VSS_78
AD5
AD17
E7