Dr.

NGP IT, CBE-48

Department of EEE

8085 ARCHITECTURE

INTR INTA

RST 5.5

RST 6.5

RST 7.5

Trap

SID

SOD

Interrupt Control

Serial I/O

8 bit Internal Bus

Accumulator

Temp. Register

Flag Reg

Instr. Register B Reg. Instruction Decoder and Machine Cycle Encoding D Reg. H Reg. C Reg. E Reg. L Reg.

ALU

+ 5v GND X1 X2 CLK GEN CLK OUT Timing and Control Control RD WR ALE Status S0 S1 IO/M DMA Reset

Stack Pointer Program Counter Address Buffer Data Address Buffer Incrementer and Decrementer Address Bus Latch Reset In Address/Data Bus A15- A8 AD7- AD0

Ready

HLD HLDA

Reset Out

Sub Code: CS2259 1

Lab Name: Microprocessors Laboratory

Prepared by: M.Dhivya,AP/EEE

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