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THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
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EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
BONN-L
CPU
: Intel Penryn
Chip Set : Intel Cantiga & ICH9M
Remarks : Montevina Platform
C
C
Model Name : R519
PBA
Name
PCB Code
: MAIN
: GCE :
NAN :
HAN :
Dev. Step
: PR
B
B
Revision
: 1.2
T.R. Date
:
2009.06.03
Design
CHECK
APPROVAL
A
A
DRAW
DATE
TITLE
SY.KIM
10/10/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
Owner : SEC Mobile R & D
Signature :
X
COVER
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
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4
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CPU
Smart
FAN
Charging
Mobile Processor
DC/DC
Battery
DC/DC
Clocking
PG 8
Circuit
Module
IMVP-6
CK-505
D
Penryn-6M
D
PG 12
CPU
FSB 1067
Thermistor
EMC2112
ON BOARD
478pin
PG 8
PG 9-11
L2 Cache : 6/3MB
Termination
VCCP / DC-DC
FSB
PG 18,19
PG 48
800/1067 MT/S
DDR II
PG 18
Channel A (Standard)
DDR II 667/800
GMCH-M
SODIMM 0
DDR II Power
Dual channel
Cantiga-GM
DDR II
PG 19
LCD
PG 47
LCD
Channel B (Reverse)
DDR II 667/800
SODIMM 1
GL40
PG 26
CRT
1329 FCBGA
CRT
PG 27
PG 13-17
C
Direct Media Interface
CLINK
C
x4, 1.5V
USB 0,2,6
PG 42, 52
USB 0,2,6
PCIE x1
Lane 4
RTL103EL
RJ45
PG 34
ANT
PG 34
USB 5
52P
PG 43
Bluetooth
PCIE x1
Lane 1
ANT
ICH9-M
Mini Card 1
PG 37
USB 1
OPTION
USB 8
(WLAN)
Camera
PG 43
676 BGA
High Definition Audio
PG 20 - 24
PG 31
Aud.
Audio
HD Audio
AMP
ALC269
PCIE x1
Lane 3
Express Card
USB 7
PG 30
PG 35
B
B
PG 33
USB 4
2 IN 1
SD
PG 36
SPI
SPI ROM
HP
PG 25
GENESIS
MMC
PG 36
MIC-IN
PG 36
SATA 0
SATA
HDD
PG 38
2P
2P
PG 31
12P
SATA 1
SATA
ODD
PG 40
PG 53
Touch
MICOM
Touchpad
Sub board
PAD
LED
3.3V LPC, 33MHz
SPKR
R
PG 38
MEC1308
PG 40
TMKBC (TBD)
KBD
PG 40
PG 39
SPKR
L
A
80 Port
A
LED
DRAW
DATE
TITLE
PG 25
PG 41
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
BLOCK DIAGRAM
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
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4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
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PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
BOARD INFORMATION
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
D
D
PCI Devices
Crystal / Oscillator
Devices
IDSEL#
REQ/GNT#
Interrupts
TYPE
FREQUENCY
DEVICE
USAGE
Cardbus
AD25
3
A,B,C
Crystal
32.768KHz
ICH9-M
Real Time Clock
Crystal
10MHz
MICOM
HD64F2169/2160
Crystal
14.318MHz
CLOCK-Generator
CK-505
USB
AD29(internal)
-
USB2.0 #0 (USB0) : A
Crystal
25MHz
LAN
RealTek 88E8057
USB2.0 #1 (USB1) : D
USB2.0 #2 (USB4) : C
USB2.0 #3 (USB5) : E
USB2.0 #4 (EHCI) : H
Hub to PCI
LPC bridge/IDE/AC97/SMBUS
AD30(internal)
-
-
AD31(internal)
-
B
Internal MAC
AD24(internal)
-
E
AC Link
-
-
B
GLAN
-
-
F
LCD Pannel Detect
(TBD)
C
Devices
Resolution
PANNEL_DETECT_0
C
Voltage Rails
2
I C / SMB Address
VDC
VCC_CORE
P1.05V (VCCP)
Primary DC system power supply (9 to 20V)
Core Voltage for CPU
VTT for CPU, Crestline & ICH9-M
Devices
Address
Hex
Bus
P3.3V_MICOM
P1.5V
3.3V always power rail (for Micom)
1.5V switched power rail (off in S3-S5)
ICH9-M
Master
-
SMBUS Master
P1.8V
1.8V switched power rail (off in S3-S5)
CPU Thermal Sensor
0111
101x
7Ah
Thermal Sensor
P1.8V_AUX
SODIMM0
1010
000x
A0h
-
P0.9V
1.8V power rail for DDR (off in S4-S5)
0.9V power rail for DDR (off in S3-S5)
SODIMM1
1010
010x
A4h
-
P3.3V
3.3V switched power rail (off in S3-S5)
Thermal Sensor on SODIMM0
0011
000x
30h
-
P3.3V_AUX
3.3V switched on power rail (off in S4-S5)
Thermal Sensor on SODIMM1
0011
010x
34h
-
P5.0V
5.0V switched power rail (off in S3-S5)
CK-505M (Clock Generator)
1101
001x
D2h
Clock, Unused Clock Output Disable
P5.0V_AUX
P5.0V_ALW
5.0V switched on power rail (off in S4-S5)
5.0V always power rail
B
B
USB PORT Assign
PCI Express Assign
PORT #
ASSIGNED TO
PORT #
ASSIGNED TO
0
SYSTEM PORT 0
0 NC
REVISION HISTORY
1
SYSTEM PORT 1
1 Mini Card 1 (WLAN)
2
SYSTEM PORT 2
2 NC
3
NC
3 LOM
4
NC
4 Mini Card 2 (ROBSON or DVB-T)
5
Bluetooth
5 NC
6
Mini PCI Express 2
7
8
Camera
NC
See rev notes for more information.
9
NC
A
A
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
BOARD INFO
H.J.KIM
1.2
BA41-
MODULE CODE
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4
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PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER DIAGRAM
Rev 0.1
KBC3_SUSPWR
KBC3_PWRON
D
D
(CHP3_S4_STATE*)
(CHP3_SLPS3*)
KBC3_VRON
AC Adapter
P1.05V_AUX
P1.05V
MEROM
VCC_CORE
MEROM
CRESTLINE
(VCCP)
ICH8-M
P1.5V_AUX
VDC
Battery DC
ICH9-M
PEG
P1.5V_AUX
P1.8V
SODIMM (DDR III)
GDDR-3 for PEG
Cantiga
DDR II-Termination
DDR III-Termination
P0.9V
P0.9V
OPTION FOR ME
C
C
ICH8-M
PCMCIA
HDD
It should be updated
FDD
USB
M_PCI
P3.3V_MICOM
P5.0V
CRT
HEATSINK
FAN CIRCUIT
P5V_AUX
MICOM
MDC
AUX DISPLAY
PEG
MICOM
IGFX_CORE
CRESTLINE
CRESTLINE
P1.5V
ICH8-M
P3.3V_ALW
P3.3V_AUX
EGFX_CORE
nVidia (TBD)
ICH8-M
LAN
MDC
BT
CRESTLINE
Thermal Sensor
MICOM
ICH8-M
SODIMM
B
P5.0V_ALW
P3.3V
SPI
PCMCIA
B
M_PCI
PEG
LEDs
MDC
LCD
CRESTLINE
ICH8-M
P1.25V
P1.2V_LAN
P12.0V_ALW
LAN
PEG
P1.8V_LAN
P1.2V
P2.5V_LAN
Power On/Off Table by S-state
LAN
Rail
S0
S3
S4
S5
State
S5-S4
S3
S0
+V*A(LWS)
ON
ON
ON
ON
+V*LAN
A
A
+1.8V_AUX
ON
ON
+0.9V
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
+V*AUX
ON
ON
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
+V
ON
APPROVAL
REV
PART NO.
POWER DIAGRAM
H.J.KIM
1.2
BA41-
+V* (CORE)
ON
MODULE CODE
LAST EDIT
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4
3
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SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER RAILS ANALYSIS
Rev. 0.6 (060920)
220V
D
D
Adapter
Battery
MICOM 3V ( TBD A )
1.8V ( TBD A )
1.05V
0.1
A (TBD)
ITP
CPU CORE
MICOM 3V
CPU CORE ( TBD A )
1.05V ( TBD A )
1.5V ( TBD A )
1.25V ( TBD A )
3.3V ( TBD A )
5.0V ( TBD A )
1.8V_AUX ( TBD A )
0.9V( TBD A )
41 A (TBD)
Penryn-6M
Thermal
0.08
A (TBD)
KBC
1.05V (VCCP)
3.3V
0.75
A (TBD)
0.08
A (TBD)
4.5
A (TBD)
3.3V
Sensor
1.5V
( 35 W )
0.13
A (TBD)
MICOM 3V
PWR LED
0.1
A (TBD)
1.05V (MCH CORE)
7.7
A (TBD)
1.05V (VCCP)
4.48
A (TBD)
Cantiga
1.5V
1.8V
C
0.125
A (TBD)
C
1.25V
GMCH
2.43A (TBD)
3.3V
CLOCK
3.3V
0.25
A (TBD)
3.3V
0.33
A (TBD)
1.8V_AUX
(8 - 8.5 W )
3.79
A (TBD)
3.3V
KeyBoard
0.2
A (TBD)
3.3V_AUX
LAN
0.6
A (TBD)
1.05V
1.13
A (TBD)
1.5V
2.4A
(TBD)
ICH9-M
3.3V
3.3V
KBD LED
0.01
A (TBD)
0.374
A (TBD)
3.3V_AUX
3.3V_AUX
0.1
A (TBD)
SD Card
0.209
A (TBD)
5V
0.001
A (TBD)
5V_AUX
0.001
A (TBD)
( ~ 2.0 W )
RTC_Battery
SPI
3.3V
0.015 A (TBD)
0.006
A (TBD)
3.3V
5V
1.0V-1.1V (EGFX CORE)
3.3V
17.75
A (TBD)
0.06 A (TBD)
HD Audio
3.3V
5V
1.5
A (TBD)
0.07 A (TBD)
1.8V
0.5
A (TBD)
Mini Card
6.53
A (TBD)
PEG
3.3V_AUX
1.5V
0.75A (TBD)
1.2V (PEX IO)
1.75
A (TBD)
5V
1.5
A (TBD)
ODD
SATA
3.3V
0.67
A (TBD)
3.3V_AUX
B
MDC
B
0.5
A (TBD)
1.8V_AUX
3.1
A (TBD)
DDR-2
5V
SATA HDD
0.9V
0.22
A (TBD)
1 A (TBD)
(Dual slots)
( ~ 5.0 W )
1.8V
GDDR
5V
FAN
3.1
A (TBD)
0.16
A (TBD)
3.3V (LCD 3V)
0.67
A (TBD)
LCD
Audio AMP
1.5
A (TBD)
19V (VDC INV)
5V
0.5
A (TBD)
P3.3V_AUX
5V
USB (x 3)
0.08
A (TBD)
2 A (TBD)
P1.2V_LAN
LAN (RTL103EL)
0.29
A (TBD)
P1.8V/2.5V_LAN
0.15
A (TBD)
5V
Touch Pad
0.2
A (TBD)
A
A
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
Value by Datasheet/Application notes
(Value by measurement)
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
POWER RAILS
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
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3.3V_AUX ( TBD A )
5.0V_AUX ( TBD A )
VDC INV ( TBD A )
PEX IO (TBD A)
VGA CORE (TBD A)
RTC_Battery
http://mycomp.su/x/
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
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PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Host Boot / ME Off
1
POWER SEQUENCE
(SLPS4* = S4_STATE*) > (SLPM* = SLPS3*)
RTC
PRTC_BAT
Rev. 0.7
M-1) KBC3_DDR_PWRON (TBD) = 8) KBC3_SUSPWR
Battery
CHP3_RTCRST#
M-2) KBC3_ME_PWRON = 15) KBC3_PWRON
Host / ME Boot
15) VRM3_CPU_PWRGD
(SLPS4* = S4_STATE*) > SLPM* > SLPS3*
PRTC
PRTC
15
D
16
D
Host S5 / ME Boot
(SLPS4* = SLPM*) > S4_STATE* > SLPS3*
CK-505
16-1) Clock Running
POWER
8
16) CLK3_PWRGD
10-1) ICH_CORE (P1.05V)
Sheet 8
S/W
8) CHP3_SLPS5#/4#/3#
7) KBC3_RSMRST#
7) P1.05V_AUX
7
CPU
7) P1.5V_AUX
12)GCORE3_PWRGD (PM-model)
4
VRM
KBC
15)VRM3_CPU_PWRGD
13) KBC3_VRON (Back-up)
VRMPWRGD
DC/DC B’d
17
17) KBC3_PWRGD
18
17) KBC3_PWRGD
(Test Option)
PWROK
18) CPU1_PWRGDCPU
14) VCC_CORE
110ms Delay
15)VRM3_CPU_PWRGD
CPU
19) PLT3_RST*
14
ICH8-M
19
5) KBC3_SUSPWR
19) PCI3_RST*
5
10-1) P1.5V
9) KBC3_PWRON
9
17) KBC3_PWRGD
CL_PWROK
Sheet 22-25
13) KBC3_VRON
C
10-1) P1.05V
20
C
Sheet 10-12
13
3
6) P1.8V_AUX
10) P5.0V
DDR2 POWER
20) CPU1_CPURST*
P3.3V_MICOM
6
17) KBC3_PWRGD
6) MEM1_VREF
2) VDC
SC486
PWROK
AC_DC / Battery
5) KBC3_SUSPWR
17) KBC3_PWRGD
10-2) 0.9V
19) PLT3_RST*
SC486
10) P1.5V
CL_PWROK
ICSL6256
Sheet 50
GMCH
10
10) P5.0V
AP4435
2) VDC
6) P1.8V_AUX
10) P1.1
2
10) P1.05V (IGFX_CORE)
10-1) P3.3V
9-1
Sheet 15-19
ISL6227
PM-model only
9) KBC3_PWRON
10) P1.05V
2-1) P12.0V_ALW
9-1) KBC3_PWRON_INV#
11-1) GFX_CORE
3
10-1) P3.3V
P3.3V_AUX & P5V_AUX
11) VCCP3_PWRGD
B
PCIe
B
SC471
TPS51120
10-1) P1.8V
12)GCORE_PWRGD
Devices
P5.0V_ALW
6) P5.0V_AUX
9
6) P3.3V_AUX
11
10) P1.5V
12
10-1) P3.3V
AP6680A
19
9) KBC3_PWRON
Sheet 40
P3.3V_MICOM
6
6) P1.8V_AUX
10-1) P1.2V
11-1) P1.8V
AP6680A
11) VCCP3_PWRGD
2) VDC
6) P1.8V_AUX
PEG
Sheet 40
DDR3
10-1) P3.3V
10-2) P0.9V
Memory
Sheet 20-21
10-1) P3.3V
PCI
10-1) P1.8V
19) PCI3_RST*
Devices
LOM
6-1) P1.2V_LAN
10) P1.5V
BCP69
A
A
Marvell
6-1) P1.8V/P2.5V_LAN
Sheet 46
DRAW
DATE
TITLE
Sheet 46-47
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
POWER SEQUENCE
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
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Battery
Adapter
4) POWER_SW*
2) VDC
6) P3.3V_AUX
8) KBC3_SUSPWR
9) KBC3_PWRON
6) P3.3V_AUX
LAN100_SLP
INTVRMEN
http://mycomp.su/x/
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THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CLOCK DISTRIBUTION Rev. 0.1
P3.3V
FS(2:0)
D
266
MHz
CLK0_HOST_CPU/CPU*
D
CPU
BSEL
CLK3_PWRGD*
1
FSB
667/800 MHz
ITP_EN
333/400 MHz
CLK1_MCLK0/0#
CPU_STP*
266
MHz
CLK0_HOST_GMCH/GMCH*
Main PLL
HPLL
SSC
MPLL
SODIMM #0
333/400 MHz
CLK1_MCLK1/1#
100
MHz (SRC0)
CLK1_PEG/PEG*
PCI Express Gfx
Cantiga
333/400 MHz
PEG
CLK1_MCLK3/3#
MCH3_CLKREQ*
MCH
SODIMM #1
100
MHz (SRC4)
CLK1_MCH3GPLL/3GPLL*
333/400 MHz
CLK1_MCLK4/4#
PCIE PLL
CLK1_DREFCLK/CLK*
96 MHz
DPLLA
100
MHz
SS(96/100) SEL
CLK1_DREFSSC/SSC*
C
PLL3
C
DPLLB
MIN3_CLKREQ*
SSC
MINI PCIE
CLK1_MINIPCIE/PCIE*
100
MHz (SRC 6)
CARD 1
DMI
100
MHz (SRC 6,8,9,10)
ITM3_CLKREQ*
MINI PCIE
CLK1_MINI2PCIE/PCIE*
100
MHz (SRC 8)
CARD 2
100
MHz (SRC 3)
CLK1_PCIEICH/ICH*
LOM3_CLKREQ*
PCIEPLL
ICH9-M
PCIE LAN
100
MHz (SRC 9)
CLK1_PCIELOM/LOM*
48MHz PLL
48
MHz
CLK3_USB48
(Marvell)
USBPLL
25 MHz
CHP3_SATACLKREQ*
EXP3_CLKREQ*
100
MHz (SRC 2)
CLK1_SATA/SATA*
SATAPLL
CLK1_EXPCARD#
EXPRESS CARD
14.318 MHz
CLK3_ICH14
32.768 KHz
B
33
MHz
CLK3_PCLKICH
B
OSC
AUD3_BCLK
HD Audio
HD 24 MHz
MDC3_BCLK
33 MHz
33
MHz
CLK3_PCLKMICOM
RTC Clock
MDC
PCI_STP*
KBC
10 MHz
Buffer
32.768 KHz
17.86 MHz
SPI3_CLK
SPI
33
MHz
CLK3_PCLKPORT80
PORT 80
14 MHz
A
OSC
A
14.318 MHz
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
Page 8
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN
APPROVAL
REV
PART NO.
CLOCK DIAGRAM
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
7
49
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OF
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xSLG8SP513r05)
MUX
MUX
MUX
http://mycomp.su/x/
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PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
THERMAL SENSOR & FAN CONTROL
D
D
P5.0V
P3.3V_AUX
P3.3V
P3.3V_AUX
R545
49.9
1%
Check if PU is doubled to Micom Side.
C537
THM3_VDD_5V_MN
THM3_VDD_3V_MN
C538
C551
10000nF-X5R
100nF
100nF
6.3V
10V
10V
U505
EMC2112-BP-TR
1
14
34-B3,49-B3
VDD_3V
SMDATA
KBC3_THERM_SMDATA
16
15
34-B3,49-C3
C
VDD_5V_1
SMCLK
KBC3_THERM_SMCLK
C
19
VDD_5V_2
12
48-B2 22-C3,34-C3
ALERT#
8
34-D1,48-B4
SYS_SHDN#
THM3_ALERT#
THM3_STP#
9
RESET#
2
10-C4,48-D2
DN1
CPU2_THERMDC
10mil width and 10mil spacing.
3
C552
DP1
P3.3V_AUX
8-B2,48-D4
2.2nF
10-C4,48-D2
For Intel 45nm(From penryn)
FAN5_VDD
17 18 FAN_1
CPU2_THERMDA
4
50V
THM3_THERMDN_MN
FAN_2
DP3_DN2
8-B2,48-C2
20
5
THM3_THERMDP_MN
FAN3_FDBACK#
TACH
DN3_DP2
R546
10
0
ADDR_SEL
2
THM3_SHDN_SEL_MN
6
C642
MMBT3904
SHDN_SEL
THM3_TRIP_SET_MN
7
11
2.2nF
1
Q509
TRIP_SET
CLK
50V
3
13
GND
21
R532
R533
THERMAL_PAD
1.5K
0
Opposite side of CPU.
1%
1209-001887
TRIP_SET 1500 : 95 degree
nostuff
SMBUS Address 7Ah
B
B
P3.3V
M503
M501
M504
M502
HEAD
HEAD
HEAD
HEAD
DIA
DIA
DIA
DIA
R544
Line Width = 20 mil
LENGTH
LENGTH
LENGTH
LENGTH
10K
BA61-01090A
BA61-01090A
BA61-01090A
BA61-01090A
1%
SHDN_SEL MODE
J1
HDR-4P-1R-SMD
INTEL TR MODE
0
FAN5_VDD
1
HIGH Z
AMD CPU/DIODE MODE
8-C3,48-D4
2
FAN3_FDBACK#
3
EXT.DIODE 2 MODE
1
8-C3,48-C2
4
5
MNT1
6
C6
MNT2
10000nF-X5R
6.3V
3711-000456
ADDRESSS_SEL MODE
To support heatsink
0
0101
111xb
HIGH Z
0111
101xb (7A)
1
0101
110xb
A
A
DESIGN
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
THERMAL SENSOR
APPROVAL
REV
PART NO.
THERMAL SENSOR EMC2112
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
8
49
June 03, 2009 16:14:25 PM
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OF
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3
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1%10KR530
10KR529
1%
1%R531
10K
10KR534
1%
http://mycomp.su/x/
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
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1
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THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
P1.05V
R656
CPU1-2
CPU1-1
56
PENRYN
PENRYN
2 / 4
CPU1_D#(15:0)
CPU1_D#(47:32)
1 / 4
0 E22
Y22
32
CPU1_A#(16:3)
D0#
D32#
3 J4
H1
1 F24
AB24
33
A3#
ADS#
CPU1_ADS#
D1#
D33#
4 L5
E2
2 E26
V24
34
A4#
BNR#
CPU1_BNR#
D2#
D34#
5 L4
G5
3 G22
V26
35
A5#
BPRI#
CPU1_BPRI#
D3#
D35#
6 K5
4 F23
V23
36
A6#
D4#
D36#
7 M3
F1
5 G25
T22
37
A7#
BR0#
CPU1_BREQ#
D5#
D37#
8 N2
6 E25
U25
38
A8#
D6#
D38#
9 J1
H5
7 E23
U23
39
A9#
DEFER#
CPU1_DEFER#
D7#
D39#
10 N3
F21
8 K24
Y25
40
A10#
DRDY#
CPU1_DRDY#
D8#
D40#
11 P5
E1
9 G24
W22
41
A11#
DBSY#
CPU1_DBSY#
D9#
D41#
12 P2
10 J24
Y23
42
A12#
D10#
D42#
13 L2
D20
CPU1_IERR#_MN
11 J23
W24
43
A13#
IERR#
D11#
D43#
14 P4
B3
12 H22
W25
44
A14#
INIT#
CPU1_INIT#
D12#
D44#
15 P1
13 F26
AA23
45
C
A15#
D13#
D45#
C
16 R1
H4
14 K22
AA24
46
A16#
LOCK#
CPU1_LOCK#
D14#
D46#
M1
15 H23
AB25
47
CPU1_ADSTB0#
ADSTB0#
D15#
D47#
C1
J26
Y26
RESET#
CPU1_CPURST#
CPU1_DSTBN0#
DSTBN0#
DSTBN2#
CPU1_DSTBN2#
F3
H26
AA26
RS0#
CPU1_RS0#
CPU1_DSTBP0#
DSTBP0#
DSTBP2#
CPU1_DSTBP2#
F4
H25
U22
CPU1_A#(35:17)
RS1#
CPU1_RS1#
CPU1_DBI0#
DINV0#
DINV2#
CPU1_DBI2#
17 Y2
G3
A17#
RS2#
CPU1_RS2#
CPU1_D#(31:16)
CPU1_D#(63:48)
18 U5
G2
16 N22
AE24
48
A18#
TRDY#
CPU1_TRDY#
D16#
D48#
19 R3
17 K25
AD24
49
A19#
D17#
D49#
20 W6
G6
18 P26
AA21
50
A20#
HIT#
CPU1_HIT#
D18#
D50#
21 U4
E4
19 R23
AB22
51
A21#
HITM#
CPU1_HITM#
D19#
D51#
22 Y5
20 L23
AB21
52
A22#
D20#
D52#
23 U1
A6
21 M24
AC26
53
A23#
A20M#
CPU1_A20M#
D21#
D53#
24 R4
A5
22 L22
AD20
54
A24#
FERR#
CPU1_FERR#
D22#
D54#
25 T5
C4
23 M23
AE22
55
A25#
IGNNE#
CPU1_IGNNE#
D23#
D55#
26 T3
24 P25
AF23
56
A26#
D24#
D56#
27 W2
D5
25 P23
AC25
57
A27#
STPCLK#
CPU1_STPCLK#
D25#
D57#
28 W5
C6
26 P22
AE21
58
A28#
LINT0
CPU1_INTR
D26#
D58#
29 Y4
B4
27 T24
AD21
59
A29#
LINT1
CPU1_NMI
D27#
D59#
30 U2
A3
28 R24
AC22
60
A30#
SMI#
CPU1_SMI#
D28#
D60#
31 V4
29 L25
AD23
61
A31#
CPU1_REQ#(4:0)
D29#
D61#
32 W3
K3
0
30 T25
AF22
62
A32#
REQ0#
D30#
D62#
33 AA4
H2
1
31 N25
AC23
63
A33#
REQ1#
D31#
D63#
34 AB2
K2
2
L26
AE25
A34#
REQ2#
CPU1_DSTBN1#
DSTBN1#
DSTBN3#
CPU1_DSTBN3#
35 AA3
J3
3
M26
AF24
A35#
REQ3#
CPU1_DSTBP1#
DSTBP1#
DSTBP3#
CPU1_DSTBP3#
V1
L1
4
N24
AC20
CPU1_ADSTB1#
ADSTB1#
REQ4#
CPU1_DBI1#
DINV1#
DINV3#
CPU1_DBI3#
0143854500|bga_479p_sock
0143854500|bga_479p_sock
B
B
CPU Socket : 3704-001153
M505
SUPLECODE
1
MNT1
2
MNT2
3
MNT3
4
MNT4
BA75-02034A
CPU Mount
A
A
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
CPU
APPROVAL
REV
PART NO.
PENRYN (1/3)
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
9
49
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June 03, 2009 16:14:25 PM
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OF
4
3
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1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
0
ADDR GROUP 1
ADDR GROUP
ICH
CONTROL
DATA GRP 1
DATA GRP 0
DATA GRP 3
DATA GRP 2
http://mycomp.su/x/

http://mycomp.su/x/

4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
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CPU1-3
PENRYN
3 / 4
P1.5V
A22
B26
CLK0_HCLK0
BCLK0
VCCA_1
A21
C26
CLK0_HCLK0#
BCLK1
VCCA_2
C49
C50
D
10000nF
D
D7
K6
10nF
CPU Core Voltage Table
CPU1_SLP#
SLP#
VCCP_1
6.3V
IMVP-6
B5
J6
25V
CPU1_DPSLP#
DPSLP#
VCCP_2
E5
M6
CPU1_DPRSTP#
DPRSTP#
VCCP_3
D24
N6
CPU1_DPWR#
DPWR#
VCCP_4
D6
T6
CPU1_PWRGDCPU
PWRGOOD
VCCP_5
AE6
35-C1
R6
CPU1_PSI#
PSI#
VCCP_6
Active Mode
K21
Active/Deeper Sleep
Dual Mode Region
CPU1_VID(6:0)
VCCP_7
Deeper Sleep/Extended Deeper Sleep
Dual Mode Region
6
AE2
J21
VID_6
VCCP_8
P1.05V
5
AF3
M21
VID_5
VCCP_9
P1.05V
P1.05V
4
AE3
N21
nostuff
VID(6:0)
Voltage
VID(6:0)
Voltage
VID(6:0)
Voltage
VID_4
VCCP_10
nostuff
3
AF4
T21
VID_3
VCCP_11
0
0
0
0
0
0
0
1.5000
V
0
1
0
1
0
0
0
1.0000
V
1 0
0
1 0
0
1
0.4875
V
2
AE5
R21
EC512
VID_2
VCCP_12
C682
C681
C680
C668
C667
C666
0
0
0
0
0
0
1
1.4875
V
0
1
0
1
0
0
1
0.9875
V
1 0
0
1 1
0
0
0.4750
V
1
AF5
V21
R662
220uF
R655
VID_1
VCCP_13
100nF
100nF
100nF
100nF
100nF
100nF
0
0
0
0
0
1
0
1.4750
V
0
1
0
1
0
1
0
0.9750
V
1 0
0
1 1
0
1
0.4625
V
0
AD6
W21
2.5V
56
56
VID_0
VCCP_14
10V
10V
10V
10V
10V
10V
0
AD
0
0
0
0
1
1
1.4625
V
0
1 V
0
1 1
0
1
0.9625
1 0
0
1
1
0
0
0.4500
V
V6
VCCP_15
nostuff
0
0
0
0
1
0
0
1.4500
V
0
1 V
0
1 0
1
0
0.9500
1 0
0
1 V
1
0
1
0.4375
CPU1_PROCHOT#_MN
D21
G21
PROCHOT#
VCCP_16
0
0
0
0
1
0
1
1.4375
V
0
1 V
0
1 1
0
1
0.9375
1 0
0
1 V
1
1
0
0.4250
A24
CPU2_THERMDA
THRMDA
-> delete and change layout (ECAE)
0
0
0
0
1
1
0
1.4250
V
0
1
0
1
1
1
0
0.9250
V
1 0
0
1
1
1
1
0.4125
V
B25
AC1
CPU2_THERMDC
THRMDC
PREQ#
P1.05V
0
0
0
0
1
1
1
1
1
1.4125
V
0
1 1
0
1
1
1
1
1
0.9125
V
1 1
0
1 0
0
0
0
0.4000
V
R661
0
C7
AC2
CPU1_THRMTRIP#
THERMTRIP#
PRDY#
0
0
0
1
0
0
0
1.4000
V
0
1 0
1
0
0
0
0.9000
V
1 1
0
1 0
0
1
0.3875
V
AC4
BPM3#
0
0
0
1
0
0
1
1.3875
V
0
1
1
0
0
0
1
0.8875
V
1 1
0
1 0
1
0
0.3750
V
C21
AD1
CPU1_BSEL2
BSEL2
BPM2#
0
0
0
1
0
1
0
1.3750
V
0
1
1
0
0
1
0
0.8750
V
1 1
0
1 0
1
1
0.3625
V
B23
AD3
R644
CPU1_BSEL1
BSEL1
BPM1#
0
0
0
1
0
1
1
1.3625
V
0
1 0
1
0
1
1
0.8625
V
1 1
0
1 1
0
0
0.3500
V
B22
AD4
1K
CPU1_BSEL0
BSEL0
BPM0#
0
0
0
1
1
0
0
1.3500
V
0
1 0
1
1
0
0
0.8500
V
1 1
0
1
1
0
1
0.3375
V
1%
0
0
0
1
1
0
1
1.3375
V
0
1
1
0
1
0
1
0.8375
V
1 1
0
1
1
1
0
0.3250
V
CPU1_GTLREF_MN
AD26
AC5
GTLREF
TCK
CPU1_TCK
0
0
0
1
1
1
0
1.3250
V
0
1 0
1
0
1
1
0.8250
V
1 1
0
1
1
1
1
0.3125
V
AA6
TDI
CPU1_TDI
0
0
0
1
1
1
1
1.3125
V
0
1 1
1
0
1
1
0.8125
V
1 0
1
0
0
0
0
0.3000
V
R673
54.9
1%
CPU1_COMP3_MN
Y1
AB3
R643
C657
COMP3
TDO
0
0
1
0
0
0
0
1.3000
V
0
1 1
1
0
0
0
0.8000
V
1 0
1
0
0
0
1
0.2875
V
R672
27.4
1%
CPU1_COMP2_MN
AA1
AB5
C
2K
100nF
COMP2
TMS
CPU1_TMS
C
0
0
1
0
0
0
1
1.2875
V
0
1 1
1
1
0
0
0.7875
V
1 0
1
0
0
1
0
0.2750
V
1%
R645
54.9
1%
CPU1_COMP1_MN
U26
AB6
10V
COMP1
TRST#
CPU1_TRST#
0
1
R646
0
0
0
1
0
1.2750
V
0
1 0
1
1
0
1
0.7750
V
1 0
1
0
0
1
1
0.2625
V
27.4 1%
CPU1_COMP0_MN
R26
C20
COMP0
DBR#
ITP3_DBRESET#
0
0
1
0
0
1
1
1.2625
V
0
1 V
1
1 1
0
1
0.7625
1 0
1
0
1
0
0
0.2500
V
0
0
1
0
1
0
0
1.2500
V
0
1 V
1
1 0
1
0
0.7500
1 0
1
0
1
0
1
0.2375
V
11-C4,43-A449-B4
AF7
M4
CPU1_VCCSENSE
VCCSENSE
RSVD_1
0
0
1
0
1
0
1
1.2375
V
0
1 V
1
1 1
1
0
0.7375
1 0
1
0
1
1
0
0.2250
V
11-B4,43-A449-B4
AE7
N5
CPU1_VSSSENSE
VSSSENSE
RSVD_2
0
0
1
0
1
1
0
1.2250
V
0
1 V
1
1 0
1
1
0.7250
1 0
1
0
1
1
1
0.2125
V
T2
RSVD_3
0
0
1 1
0
1
1
1
1
1
1.2125
V
0
1
1 1
1
1
1
1
1
1
0.7125
V
1 1
1
0
0
0
0
1 0
0.2000
V
C23
V3
TEST1
RSVD_4
SI team request
0
0
1
1
0
0
0
1.2000
V
1
0
0
0
0
0
0
0.7000
V
1 1
1
0
0
0
1
0.1875
V
D25
B2
TEST2
RSVD_5
0
0
1
1
0
0
1
1.1875
V
1
0
0
0
0
0
1
0.6875
V
1 1
1
0
0
1
0
0.1750
V
C24
D2
TEST3
RSVD_6
0
0
1
1
0
1
0
1.1750
V
1
0
0
0
0
1
0
0.6750
V
1 1
1
0
0
1
1
0.1625
V
AF26
D22
TEST4
RSVD_7
0
0
1
1
0
1
1
1.1625
V
1
0
0
0
0
1
1
0.6625
V
1 1
1
0
1
0
0
0.1500
V
AF1
D3
TEST5
RSVD_8
0
0
1
1
1
0
0
1.1500
V
1
0
0
0
1
0
0
0.6500
V
1 1
1
0
1
0
1
0.1375
V
A26
F6
TEST6
RSVD_9
0
0
1
1
1
0
1
1.1375
V
1
0
0
0
1
0
1
0.6375
V
1 1
1
0
1
1
0
0.1250
V
C3
TEST7
0
0
1
1
1
1
0
1.1250
V
1
0
0
0
1
1
0
0.6250
V
1 1
1
0
1
1
1
0.1125
V
0
0
1
1
1
1
1
1.1125
V
1
0
0
0
1
1
1
0.6125
V
1 0
1
1
0
0
0
0.1000
V
0
1
0
0
0
0
0
1.1000
V
1
0
0
1
0
0
0
0.6000
V
1 0
1
1
0
0
1
0.0875
V
0143854500|bga_479p_sock
0
1
0
0
0
0
1
1.0875
V
1
0
0
1
0
0
1
0.5875
V
1 0
1
1
0
1
0
0.0750
V
0
1
0
0
0
1
0
1.0750
V
1
0
0
1 1
0
0
0.5750
V
1 0
1
1
0
1
1
0.0625
V
0
1
0
0
0
1
1
1.0625
V
1
0
0
1 1
0
1
0.5625
V
1 0
1
1
1
0
0
0.0500
V
0
1
0
0
1
0
0
1.0500
V
1
0
0
1 0
1
0
0.5500
V
1 0
1
1
1
0
1
0.0375
V
0
1
0
0
1
0
1
1.0375
V
1
0
0
1 1
1
0
0.5375
V
1 0
1
1
1
1
0
0.0250
V
0
1
0
0
1
1
0
1.0250
V
1
0
0
1
1
1
0
0.5250
V
1 0
1
1
1
1
1
0.0125
V
0
1 1
0
0
1 1
1
1
1
1.0125
V
1
0
0
0
1
1 1
1
1
1
0.5125
V
1 1
1 1
1
0
1 0
0
0.0000
V
CPU Socket : 3704-001153
1
0 1
1
0
0
0
0
0
0
0.5000
V
1 1
1
1
0
0
1
0.0000
V
1 1
1
1
0
1
0
0.0000
V
1 1
1
1
0
1
1
0.0000
V
Deeper Slp
Active
1 1
1
1
1
0
0
0.0000
V
DPRSLPVR
1
DPRSLPVR
0
1 1
1
1
1
0
1
0.0000
V
B
1 1
1
1
1
1
0
0.0000
V
DPRSTP*
0
FSC
FSB
FSA
FRQ
DPRSTP*
1
P1.05V
1 1
1
1
1
1
1
0.0000
V
0
0
0
266M
PSI2*
0 or 1
PSI2*
0 or 1
*"1111111" : 0V power good asserted.
0
1
0
200M
0
1
1
166M
*Yonah Processor (2.33 GHz / 800 MHz : TBD)
GTLREF : Keep the Voltage divider within 0.5"
near the CPU
of the first GTLREF0 pin with Zo=55ohm trace.
Minimize coupling of any switching signals to this net.
BSEL
COMP0,2(COMP1,3) should be connected with Zo=27.4ohm(55ohm)
trace shorter than 1/2" to their respective Banias socket pins.
CPU1_TDI
Pull-down
CPU1_TMS
CPU1_TCK
FSB 1067 MHz
FSB 800 MHz
BSEL0, BSEL1, BSEL2
BSEL0, BSEL2
CPU1_TRST#
GND test points within 100mil of the VCC/VSSsense at the end of the line.
Route the VCC/VSSsense as a Zo=55ohm traces with equal length.
Observe 3:1 spacing b/w VCC/VSSsense lines and 25mil away
(preferred 50mil) from any other signal. And GND via 100mil away
from each of the VCC/VSS test point vias.
A
A
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
CPU
APPROVAL
REV
PART NO.
PENRYN (2/3)
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
10
49
undefined
June 03, 2009 16:14:25 PM
PAGE
OF
4
3
2
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
54.9R74
1%
54.9R72
1%
54.9R73
1%
54.9R75
H CLK
THERMAL
RSVD
XDP/ITP SIGNALS
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
D
A11
K1
VSS_1
VSS_120
CPU_CORE
CPU_CORE
A14
J5
VSS_2
VSS_119
A16
J25
VSS_3
VSS_118
A19
J22
VSS_4
VSS_117
A2
A10
AE9
J2
VSS_5
VCC_1
VCC_51
VSS_116
A23
A12
AF10
H6
VSS_6
VCC_2
VCC_52
VSS_115
A25
A13
AF12
H3
VSS_7
VCC_3
VCC_53
VSS_114
A4
A15
AF14
H24
VSS_8
VCC_4
VCC_54
VSS_113
A8
A17
AF15
H21
VSS_9
VCC_5
VCC_55
VSS_112
AA11
A18
AF17
G4
VSS_10
VCC_6
VCC_56
VSS_111
AA14
A20
AF18
G26
VSS_11
VCC_7
VCC_57
VSS_110
AA16
A7
AF20
G23
VSS_12
VCC_8
VCC_58
VSS_109
AA19
A9
AF9
G1
VSS_13
VCC_9
CPU1-4
VCC_59
VSS_108
CPU_CORE
AA2
AA10
B10
F8
VSS_14
VCC_10
VCC_60
VSS_107
AA22
AA12
B12
F5
VSS_15
VCC_11
PENRYN
VCC_61
VSS_106
AA25
AA13
B14
F25
VSS_16
VCC_12
VCC_62
VSS_105
AA5
AA15
B15
F22
VSS_17
VCC_13
VCC_63
VSS_104
AA8
AA17
B17
F2
VSS_18
VCC_14
4 / 4
VCC_64
VSS_103
AB1
AA18
B18
F19
VSS_19
VCC_15
VCC_65
VSS_102
AB11
AA20
B20
F16
VSS_20
VCC_16
VCC_66
VSS_101
AB13
AA7
B7
F13
VSS_21
VCC_17
VCC_67
VSS_100
AB16
AA9
B9
F11
C
VSS_22
VCC_18
VCC_68
VSS_99
C
0143854500|bga_479p_sock
AB19
AB10
C10
E8
VSS_23
VCC_19
VCC_69
VSS_98
AB26
AB12
C12
E6
VSS_24
VCC_20
VCC_70
VSS_97
AB4
AB14
C13
E3
VSS_25
VCC_21
VCC_71
VSS_96
R671
100
1%
AB8
AB15
C15
E24
CPU1_VCCSENSE
VSS_26
VCC_22
VCC_72
VSS_95
10-C4,43-A4
AC11
AB17
C17
E21
VSS_27
VCC_23
VCC_73
VSS_94
49-B4
AC14
AB18
C18
E19
VSS_28
VCC_24
VCC_74
VSS_93
AC16
AB20
C9
E16
VSS_29
VCC_25
VCC_75
VSS_92
AC19
AB7
D10
E14
VSS_30
VCC_26
VCC_76
VSS_91
AC21
AB9
D12
E11
VSS_31
VCC_27
VCC_77
VSS_90
AC24
AC10
D14
D8
VSS_32
VCC_28
VCC_78
VSS_89
AC3
AC12
D15
D4
VSS_33
VCC_29
VCC_79
VSS_88
AC6
AC13
D17
D26
VSS_34
VCC_30
VCC_80
VSS_87
AC8
AC15
D18
D23
VSS_35
VCC_31
VCC_81
VSS_86
AD11
AC17
D9
D19
VSS_36
VCC_32
VCC_82
VSS_85
R670
100
1%
AD13
AC18
E10
D16
CPU1_VSSSENSE
VSS_37
VCC_33
VCC_83
VSS_84
10-C4,43-A4
AD16
AC7
E12
D13
VSS_38
VCC_34
VCC_84
VSS_83
49-B4
AD19
AC9
E13
D11
VSS_39
VCC_35
VCC_85
VSS_82
AD2
AD10
E15
D1
VSS_40
VCC_36
VCC_86
VSS_81
AD22
AD12
E17
C8
VSS_41
VCC_37
VCC_87
VSS_80
AB23
AD14
E18
C5
VSS_42
VCC_38
VCC_88
VSS_79
AD25
AD15
E20
C25
Prodlizer & Cbulk common used(Socket inside)
VSS_43
VCC_39
VCC_89
VSS_78
AD5
AD17
E7
C22
VSS_44
VCC_40
VCC_90
VSS_77
AD8
AD18
E9
C2
VSS_45
VCC_41
VCC_91
VSS_76
AE1
AD7
F10
C19
VSS_46
VCC_42
VCC_92
VSS_75
AE11
AD9
F12
C16
VSS_47
VCC_43
VCC_93
VSS_74
AE14
AE10
F14
C14
VSS_48
VCC_44
VCC_94
VSS_73
AE16
AE12
F15
C11
VSS_49
VCC_45
VCC_95
VSS_72
AE19
AE13
F17
B8
VSS_50
VCC_46
VCC_96
VSS_71
B
AE23
AE15
F18
B6
B
VSS_51
VCC_47
VCC_97
VSS_70
AE26
AE17
F20
B24
VSS_52
VCC_48
VCC_98
VSS_69
AE4
AE18
F7
B21
VSS_53
VCC_49
VCC_99
VSS_68
AE8
AE20
F9
B19
VSS_54
VCC_50
VCC_100
VSS_67
AF11
B16
VSS_55
VSS_66
AF13
B13
VSS_56
VSS_65
AF16
B11
VSS_57
VSS_64
AF19
AF8
VSS_58
VSS_63
AF2
AF6
VSS_59
VSS_62
AF21
AF25
VSS_60
VSS_61
A
A
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
CPU
APPROVAL
REV
PART NO.
PENRYN (3/3)
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
11
49
undefined
June 03, 2009 16:14:25 PM
PAGE
OF
4
3
2
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
C69
10000nF-X5R 6.3V
10%
C70
10000nF-X5R 6.3V
10%
C73
10000nF-X5R 6.3V
C72
10000nF-X5R 6.3V
C61
10000nF-X5R 6.3V
C59
10000nF-X5R 6.3V
C62
10000nF-X5R 6.3V
C74
10000nF-X5R 6.3V
C60
10000nF-X5R 6.3V
C65
10000nF-X5R 6.3V
C76
10000nF-X5R 6.3V
C75
10000nF-X5R 6.3V
C66
10000nF-X5R 6.3V
C68
10000nF-X5R 6.3V
C67
10000nF-X5R 6.3V
C71
10000nF-X5R
6.3V
Y6
VSS_163
Y3
K23
VSS_162
VSS_121
Y24
K26
VSS_161
VSS_122
Y21
K4
VSS_160
VSS_123
W4
L21
VSS_159
VSS_124
W26
L24
VSS_158
VSS_125
W23
L3
VSS_157
VSS_126
W1
L6
VSS_156
VSS_127
V5
M2
VSS_155
VSS_128
V25
M22
VSS_154
VSS_129
V22
M25
VSS_153
VSS_130
V2
M5
VSS_152
VSS_131
U6
N1
VSS_151
VSS_132
U3
N23
VSS_150
VSS_133
U24
N26
VSS_149
VSS_134
U21
N4
VSS_148
VSS_135
T4
P21
VSS_147
VSS_136
T26
P24
VSS_146
VSS_137
T23
P3
VSS_145
VSS_138
T1
P6
VSS_144
VSS_139
R5
R2
VSS_143
VSS_140
R25
R22
VSS_142
VSS_141
http://mycomp.su/x/
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
CK505M
D
D
FSA
FSB
FSC
P1.5V
P3.3V
HOST CLK
BSEL0
BSEL1
BSEL2
0
0
0
266
MHz
B517
B518
0
0
1
333
MHz
BLM18PG181SN1
BLM18PG181SN1
0
1
0
200
MHz
VDD_SRC_IO
VDD_CPU_IO
VDD_PLL3_IO
VDD_IO
VDD_REF
VDD_48
VDD_PCI
VDD_PLL3
VDD_SRC
VDD_CPU
0
1
1
400
MHz
1
0
0
133
MHz
1
0
1
100
MHz
1
1
0
166
MHz
1
1
1
RSVD
nostuff
CLK3_VDD_SRC_IO_MN
CLK3_VDD_REF_MN
nostuff
nostuff
C
U5
C
31-B4
R88
33
CLK3_FM48
SLG8SP513
22-A3
R86
33
CLK3_USB48
19
4
VDD_IO
VDD_REF
10-C4,13-A3
R87
2.2K
33
16
CPU1_BSEL0
VDD_SRC_IO1
VDD_48
43
9
VDD_SRC_IO2
VDD_PCI
52
23
nostuff
VDD_SRC_IO3
VDD_PLL3
56
VDD_CPU_IO
C142
27
46
VDD_PLL3_IO
VDD_SRC
0.022nF
62
VDD_CPU
10-C4,13-A3
50V
55
CPU1_BSEL1
NC
10-C4,13-A3
R96
10K
1%
61
10-D4
CPU1_BSEL2
CPU0
CLK3_USB48_R_MN
17
USB_FS_A
CPU0#
60
10-D4
CLK0_HCLK0
CLK0_HCLK0#
22-A3
R97
33
64
CLK3_ICH14
FSB_TESTMODE
CLK3_ICH14_R_MN
5
58
13-B1
REF_FS_C_TEST_SEL
CPU1_MCH
57
13-B1
CPU1_MCH#
CLK0_HCLK1
CLK0_HCLK1#
22-C3,48-B2
44
CHP3_CPUSTP#
CPUSTOP#
22-C3,48-B2
45
CHP3_PCISTP#
PCISTOP#
SRC11_CLKREQH#
40
30-B3,48-B2
SRC11#_CLKREQG#
39
LOM3_CLKREQ#
22-B3
63
CLK3_PWRGD
CLKPWRGD_PWRDN#
41
SRC10
21-C2
R90
22
5%
CLK3_PCLKICH_R_MN
14
CLK3_PCLKICH
PCIF_5_ITP_EN
SRC10#
42
25-A4
R91
22
5%
CLK3_DBGLPC_R_MN
13
37
30-A4
CLK3_DBGLPC
PCI_4_SEL_LCDCLK#
SRC9
SRC9#
38
30-A4
CLK1_PCIELOM
CLK1_PCIELOM#
12
PCI_3
54
SRC8_ITP
34-B4
R93
22
5%
CLK3_PCLKMICOM_R_MN
11
CLK3_PCLKMICOM
PCI_2
SRC8#_ITP#
53
B
14-A1,48-B2
R94
475
1%
MCH3_CLKREQ#_R_MN
10
51
B
MCH3_CLKREQ#
PCI_1_CLKREQ_B#
SRC7_CLKREQF#
50
32-C4,49-C4
SRC7#_CLKREQE#
MIN3_CLKREQ#
22-B3,49-C3
R95
475
1%
CHP3_SATACLKREQ#_R_MN
8
CHP3_SATACLKREQ#
PCI_0_CLKREQ_A#
48
32-C4
SRC6
18-B4,19-B4
22-B4,48-D4
7
32-C4
SMB3_CLK
SCL
SRC6#
47
CLK1_MINIPCIE
CLK1_MINIPCIE#
18-B4,19-B4
22-B4,48-B4
6
SMB3_DATA
SDA
34
14-B1
SRC4
3
14-B1
XTAL_IN
SRC4#
35
CLK1_MCH3GPLL
CLK1_MCH3GPLL#
2
XTAL_OUT
31
22-C1
SRC3_CLKREQC#
18
32
22-C1
VSS_48
SRC3#_CLKREQD#
CLK1_PCIEICH
CLK1_PCIEICH#
59
Y2
VSS_CPU
22
28
20-B1
VSS_IO
SRC2
15
29
20-B1
VSS_PCI
SRC2#
CLK1_SATA
CLK1_SATA#
26
VSS_PLL3
1
24
14-C1
14.31818MHz
VSS_REF
LCDCLK_27M
30
14-C1
2801-004667
VSS_SRC1
LCDCLK#_27M_SS
25
CLK1_DREFSSCLK
CLK1_DREFSSCLK#
36
VSS_SRC2
C147
C146
49
20
14-C1
VSS_SRC3
SRC0_DOT96
0.018nF
0.018nF
21
14-C1
SRC0#_DOT96#
CLK1_DREFCLK#
50V
CLK1_DREFCLK
50V
1205-003156
CLK REQ
DEVICE
SRC PORT
CLK REQ A
SATA
SRC2
CLK REQ B
GMCH
SRC4
Place 14.318MHz within
500mils of CK-505
This part is 64pin QFN package.
A
CLK REQ E
MINI CARD
SRC6
A
CLK REQ F
EXP3_CLKREQ#
SRC8
IDT : 1205-003159
SL : 1205-003533
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
SEL_LCDCLK*
Pin 20/21
Pin 24/25
CHECK
DEV. STEP
ELECTRONICS
HK.PARK
PR
MAIN_CLOCK_CIRCUIT
LOW
DOT_96/DOT_96#
PEG_CLK/PEG_CLK#
APPROVAL
REV
PART NO.
CK_Clock_505M
HIGH
SRC_0/SRC_0#
27M & 27M_SS
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
12
49
undefined
June 03, 2009 16:14:25 PM
PAGE
OF
4
3
2
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
1
2
C692
10000nF-X5R
6.3V
C698
100nF
10V
C143
0.033nF
50V
C695
10000nF-X5R
5%
6.3V
C144
0.033nF
50V
5%
C145
0.033nF 50V
5%
C693
100nF
10V
C694
10000nF-X5R
6.3V
1%
10KR92
1%
10KR89
C717
100nF
10V
C691
10000nF-X5R
6.3V
65
THERM_GND
C721
100nF
10V
C718
100nF
10V
C719
10000nF-X5R
6.3V
C720
100nF
10V
C697
100nF
10V
C696
10000nF-X5R
6.3V
http://mycomp.su/x/

http://mycomp.su/x/

4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P1.05V
P1.05V
nostuff
EC508
nostuff
C599
C647
C645
C597
nostuff
220uF
10000nF-X5R
100nF
100nF
100nF
2.5V
EC501
6.3V
10V
10V
10V
C556
C554
C555
AD
220uF
1000nF-X5R
10000nF-X5R
10000nF-X5R
2.5V
6.3V
6.3V
6.3V
AD
CPU1_A#(35:3)
22-D2
D
CPU1_D#(63:0)
D
A14
3
H_A#_3
0 F2
C15
4
H_D#_0
H_A#_4
1 G8
F16
5
H_D#_1
H_A#_5
2 F8
H13
6
H_D#_2
H_A#_6
3 E6
C18
7
H_D#_3
H_A#_7
4 G2
M16
8
H_D#_4
H_A#_8
5 H6
J13
9
H_D#_5
H_A#_9
6 H2
P16
10
H_D#_6
H_A#_10
7 F6
VCC CORE
VTT
R16
11
H_D#_7
H_A#_11
8 D4
N17
12
H_D#_8
H_A#_12
9 H3
M13
13
H_D#_9
H_A#_13
10 M9
E17
14
H_D#_10
H_A#_14
11 M11
P17
15
H_D#_11
H_A#_15
12 J1
F17
16
H_D#_12
H_A#_16
13 J2
G20
17
H_D#_13
H_A#_17
P1.05V
14 N12
B19
18
H_D#_14
H_A#_18
15 J6
J16
19
H_D#_15
H_A#_19
16 P2
E20
20
H_D#_16
H_A#_20
17 L2
H16
21
R535
H_D#_17
H_A#_21
18 R2
J20
22
221
H_D#_18
H_A#_22
19 N9
L17
23
1%
H_D#_19
H_A#_23
20 L6
A17
24
MCH1_HXSWING
H_D#_20
H_A#_24
21 M5
U3-1
B17
25
H_D#_21
H_A#_25
22 J3
L16
26
R43
C32
H_D#_22
H_A#_26
23 N2
C21
27
100
100nF
H_D#_23
H_A#_27
24 R1
GL40
J17
28
1%
10V
H_D#_24
H_A#_28
25 N5
H20
29
H_D#_25
H_A#_29
26 N6
B18
30
C
H_D#_26
H_A#_30
C
27 P13
1 OF 5
K17
31
H_D#_27
H_A#_31
28 N8
B20
32
H_D#_28
H_A#_32
29 L7
F21
33
H_D#_29
H_A#_33
30 N10
K21
34
H_D#_30
H_A#_34
31 M3
L20
35
H_D#_31
0904-002489
H_A#_35
32 Y3
H_D#_32
33 AD14
H12
H_D#_33
H_ADS#
CPU1_ADS#
34 Y6
B16
H_D#_34
H_ADSTB#_0
CPU1_ADSTB0#
35 Y10
G17
H_D#_35
H_ADSTB#_1
CPU1_ADSTB1#
36 Y12
A9
H_D#_36
H_BNR#
CPU1_BNR#
37 Y14
F11
H_D#_37
H_BPRI#
CPU1_BPRI#
38 Y7
G12
H_D#_38
H_BREQ#
CPU1_BREQ#
39 W2
H_D#_39
P1.05V
40 AA8
E9
H_D#_40
H_DEFER#
CPU1_DEFER#
41 Y9
B10
H_D#_41
H_DBSY#
CPU1_DBSY#
42 AA13
J11
H_D#_42
H_DPWR#
CPU1_DPWR#
43 AA9
F9
R549
H_D#_43
H_DRDY#
CPU1_DRDY#
44 AA11
1K
H_D#_44
45 AD11
H9
1%
H_D#_45
H_HIT#
CPU1_HIT#
46 AD10
E12
MCH1_HVREF
H_D#_46
H_HITM#
CPU1_HITM#
47 AD13
H11
H_D#_47
H_LOCK#
CPU1_LOCK#
48 AE12
C9
R547
H_D#_48
H_TRDY#
CPU1_TRDY#
49 AE9
2K
H_D#_49
50 AA2
AH7
1%
H_D#_50
HPLL_CLK
CLK0_HCLK1
51 AD8
AH6
H_D#_51
HPLL_CLK#
CLK0_HCLK1#
52 AA3
H_D#_52
53 AD3
J8
H_D#_53
H_DINV#_0
CPU1_DBI0#
54 AD7
L3
H_D#_54
H_DINV#_1
CPU1_DBI1#
B
55 AE14
Y13
B
H_D#_55
H_DINV#_2
CPU1_DBI2#
56 AF3
Y1
H_D#_56
H_DINV#_3
CPU1_DBI3#
57 AC1
H_D#_57
58 AE3
L10
H_D#_58
H_DSTBN#_0
CPU1_DSTBN0#
59 AC3
M7
H_D#_59
H_DSTBN#_1
CPU1_DSTBN1#
60 AE11
AA5
H_D#_60
H_DSTBN#_2
CPU1_DSTBN2#
61 AE8
AE6
H_D#_61
H_DSTBN#_3
CPU1_DSTBN3#
62 AG2
H_D#_62
63 AD6
L9
H_D#_63
H_DSTBP#_0
CPU1_DSTBP0#
M8
H_DSTBP#_1
CPU1_DSTBP1#
C12
AA6
CPU1_CPURST#
H_CPURST#
H_DSTBP#_2
CPU1_DSTBP2#
E11
AE5
CPU1_SLP#
H_CPUSLP#
H_DSTBP#_3
CPU1_DSTBP3#
CFG
NC
CPU1_REQ#(4:0)
C5
B15
0
MCH1_HXSWING
H_SWING
H_REQ#_0
MCH1_H_RCOMP_MN
E3
K13
1
H_RCOMP
H_REQ#_1
F13
2
R536
24.9
1%
H_REQ#_2
B11
B13
3
MCH1_HVREF
H_DVREF
H_REQ#_3
A11
B14
4
1608
H_AVREF
H_REQ#_4
MCH1_VTTLF1_MN
A8
B6
VTTLF_1
H_RS#_0
CPU1_RS0#
MCH1_VTTLF2_MN
AB2
F12
VTTLF_2
H_RS#_1
CPU1_RS1#
MCH1_VTTLF3_MN
L1
C8
VTTLF_3
H_RS#_2
CPU1_RS2#
*POCAFEB-12 Only (Remove in MP Model)
Current Setting
(def. : default Option)
CFG#
P1.05V
Low
High
CPU1_BSEL0
MCH1_CFG6_MN
A
CPU1_BSEL1
CFG(5)
DMIx2
DMIx4 (def.)
iTPM Host Interface Disable (def.)
ME Crypto confidentiality (def.)
Normal
PCIE Loop Back Disable(def)
A
CPU1_BSEL2
CFG(6)
R586
CFG(7)
DRAW
DATE
TITLE
2.2K
SY.KIM
9/23/2008
SAMSUNG
CFG(9)
BONN-L
nostuff
CFG(10)
CHECK
DEV. STEP
ELECTRONICS
iTPM option
HK.PARK
PR
MCH_CANTIGA_GM_DDR2
CFG(16)
Dynamic ODT
Enabled (def.)
CFG(19)
iTPM Host Interface Enable
ME Crypto no confidentiality
PEG Reversal (def.)
PCIE Loop Back Enable
Dynamic ODT Disabled
DMI Lane Normal (def.)
SDVO or PCIE X1
Only(def.)
DMI Lane Reversal
APPROVAL
REV
PART NO.
CANTIGA (1/5)
H.J.KIM
1.2
BA41-
CFG(20)
SDVO and PCIE X1
Simultaneously
MODULE CODE
LAST EDIT
13
49
undefined
June 03, 2009 16:14:25 PM
PAGE
OF
4
3
2
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
470nFC35
470nFC540
470nFC539
16V
16V
16V
VTTLF
T25
HOST DATA BUS
CFG_0
R25
AA28
CFG_1
VCC_1
P25
AA33
CFG_2
VCC_2
P20
AA34
CFG_3
VCC_3
P24
AB34
CFG_4
VCC_4
C25
AC26
CFG_5
VCC_5
N24
AC28
CFG_6
VCC_6
M24
AC33
CFG_7
VCC_7
E21
AC34
CFG_8
VCC_8
C23
AE26
CFG_9
VCC_9
C24
AE33
CFG_10
VCC_10
N21
AF23
CFG_11
VCC_11
P21
AF25
CFG_12
VCC_12
T21
AF28
CFG_13
VCC_13
R20
AF33
CFG_14
VCC_14
M20
AG24
CFG_15
VCC_15
L21
AG25
CFG_16
VCC_16
H21
AG26
CFG_17
VCC_17
P29
AG33
CFG_18
VCC_18
R28
AG34
CFG_19
VCC_19
T28
AH23
CFG_20
VCC_20
AH25
VCC_21
AA29
AH28
VCC_NCTF_1
VCC_22
AA30
AJ23
VCC_NCTF_2
VCC_23
AA32
AJ26
VCC_NCTF_3
VCC_24
AB30
AJ33
VCC_NCTF_4
VCC_25
AC29
AK33
VCC_NCTF_5
VCC_26
AC30
AM33
VCC_NCTF_6
VCC_27
AC32
T32
VCC_NCTF_7
VCC_28
AE29
U33
VCC_NCTF_8
VCC_29
AE30
U34
VCC_NCTF_9
VCC_30
AE32
V33
VCC_NCTF_10
VCC_31
AF30
V34
VCC_NCTF_11
VCC_32
AG29
W33
VCC_NCTF_12
VCC_33
AG30
Y33
VCC_NCTF_13
VCC_34
AG32
Y34
VCC_NCTF_14
VCC_35
AH29
VCC_NCTF_15
AH30
VCC_NCTF_16
AH32
T10
VCC_NCTF_17
VTT_1
AJ29
T11
VCC_NCTF_18
VTT_2
AJ32
T12
VCC_NCTF_19
VTT_3
AK23
T13
VCC_NCTF_20
VTT_4
AK24
T2
VCC_NCTF_21
VTT_5
AK25
T5
VCC_NCTF_22
VTT_6
AK26
T6
VCC_NCTF_23
VTT_7
AK28
T7
VCC_NCTF_24
VTT_8
AK29
T8
VCC_NCTF_25
VTT_9
AK30
T9
VCC_NCTF_26
VTT_10
AK32
U1
VCC_NCTF_27
VTT_11
AL26
U10
VCC_NCTF_28
VTT_12
AL28
U11
VCC_NCTF_29
VTT_13
AL29
U12
VCC_NCTF_30
VTT_14
AL30
U13
VCC_NCTF_31
VTT_15
AL32
U2
VCC_NCTF_32
VTT_16
AM30
U3
VCC_NCTF_33
VTT_17
AM32
U5
VCC_NCTF_34
VTT_18
U30
U6
VCC_NCTF_35
VTT_19
U32
U7
VCC_NCTF_36
VTT_20
V29
U8
VCC_NCTF_37
VTT_21
V30
U9
VCC_NCTF_38
VTT_22
W29
V1
VCC_NCTF_39
VTT_23
W30
V2
VCC_NCTF_40
VTT_24
W32
V3
VCC_NCTF_41
VTT_25
Y29
VCC_NCTF_42
Y30
VCC_NCTF_43
Y32
HOST ADDRESS BUS
VCC_NCTF_44
HOST CONTROL
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
P3.3V
R771
20K
1%
R770
7.5K
1%
D
D
1608
P1.05V_PEG
27-B4,48-C2
H32
T37
R639
49.9
1%
CRT3_DDCCLK
CRT_DDC_CLK
PEG_COMPI
27-B4,48-D2
J32
T36
CRT3_DDCDATA
CRT_DDC_DATA
PEG_COMPO
MCH1_COMPIO_R_MN
27-C4,48-C3
R579
40.2
1%
J29
B33
CRT3_HSYNC
CRT_HSYNC
GFX_VID_0
27-C4,48-C3
R582
40.2
1%
L29
B32
CRT3_VSYNC
CRT_VSYNC
GFX_VID_1
G33
GFX_VID_2
27-C3,48-C4
E28
F33
CRT3_BLUE
CRT_BLUE
GFX_VID_3
27-C3,48-C3
G28
E33
CRT3_GREEN
CRT_GREEN
GFX_VID_4
27-C3,48-D4
J28
CRT3_RED
CRT_RED
PCIE GFX
1.02kohm
C34
PCIE GFX
GFX_VR_EN
R576
1K
1%
E29
CRT_TVO_IREF
G29
AE41
CRT_IRTN
DMI_RXN_0
DMI1_TXN_0
AE37
DMI_RXN_1
DMI1_TXN_1
C31
U3-2
AE47
TV_DCONSEL_0
DMI_RXN_2
DMI1_TXN_2
E32
AH39
TV_DCONSEL_1
DMI_RXN_3
DMI1_TXN_3
R580
75
1%
F25
AE40
TVA_DAC
GL40
DMI_RXP_0
DMI1_TXP_0
R583
75
1%
H25
AE38
TVB_DAC
DMI_RXP_1
DMI1_TXP_1
R584
75
1%
K25
AE48
TVC_DAC
DMI_RXP_2
DMI1_TXP_2
AH40
DMI_RXP_3
DMI1_TXP_3
H24
TV_RTN
AE35
Default : TV Disable
DMI_TXN_0
DMI1_RXN_0
AE43
C
DMI_TXN_1
DMI1_RXN_1
C
26-A1,49-D4
K33
AE46
LCD3_EDID_CLK
L_DDC_CLK
DMI_TXN_2
DMI1_RXN_2
26-A1,49-C3
J33
AH42
LCD3_EDID_DATA
L_DDC_DATA
DMI_TXN_3
DMI1_RXN_3
M32
AD35
L_CTRL_CLK
DMI_TXP_0
DMI1_RXP_0
M33
AE44
L_CTRL_DATA
DMI_TXP_1
DMI1_RXP_1
AF46
DMI_TXP_2
DMI1_RXP_2
26-C2,49-D4
M29
AH43
MCH3_LCDVDDON
L_VDD_EN
DMI_TXP_3
DMI1_RXP_3
26-C4,48-B2
G32
MCH3_BKLTEN
L_BKLT_EN
26-B2,48-C4
L32
B38
12-A1
LCD3_BRIT
L_BKLT_CTRL
DPLL_REF_CLK
CLK1_DREFCLK
A38
12-A1
DPLL_REF_CLK#
CLK1_DREFCLK#
26-A1
H47
LCD1_ADATA0#
LVDSA_DATA#_0
26-A2
E46
GFX VCC
E41
12-A1
LCD1_ADATA1#
LVDSA_DATA#_1
GFX VCC NCTF
DPLL_REF_SSCLK
CLK1_DREFSSCLK
26-B1
G40
F41
12-A1
LCD1_ADATA2#
LVDSA_DATA#_2
DPLL_REF_SSCLK#
CLK1_DREFSSCLK#
A40
2 OF 5
0904-002489
LVDSA_DATA#_3
F43
PEG_CLK
CLK1_MCH3GPLL
26-B1
H48
E43
LCD1_ADATA0
LVDSA_DATA_0
PEG_CLK#
CLK1_MCH3GPLL#
P1.05V
26-B2
D45
GFX VCC NCTF
LCD1_ADATA1
LVDSA_DATA_1
26-B1
F40
AH37
LCD1_ADATA2
LVDSA_DATA_2
CL_CLK
CHP3_CL_CLK_0
B40
AH36
LVDSA_DATA_3
CL_DATA
CHP3_CL_DATA_0
AN36
R590
CL_PWROK
KBC3_PWRGD
26-B2
C40
AJ35
1K
LCD1_ACLK
LVDSA_CLK
CL_RST#
CHP3_CL_RST_0#
C601
26-B2
C41
1%
LCD1_ACLK#
LVDSA_CLK#
100nF
AH34
MCH1_CL_VREF_MN
CL_VREF
26-B1
A41
10V
LCD1_BDATA0#
LVDSB_DATA#_0
26-B2
H38
R29
R640
LCD1_BDATA1#
LVDSB_DATA#_1
PM_SYNC#
CHP3_PM_SYNC#
26-B1
G37
B7
35-C1
23-D4
11-D3
499
LCD1_BDATA2#
LVDSB_DATA#_2
PM_DPRSTP#
CPU1_DPRSTP#
J37
R32
37-C3
11-D3
1%
LVDSB_DATA#_3
DPRSLPVR
CHP3_DPRSLPVR
B
26-B1
B42
AT40
22-B3,34-C448-B3
B
LCD1_BDATA0
LVDSB_DATA_0
PWROK
KBC3_PWRGD
26-B2
G38
AT11
LCD1_BDATA1
LVDSB_DATA_1
RSTIN#
26-B1
F37
PLT3_RST#_R_MN
R589
LCD1_BDATA2
LVDSB_DATA_2
K37
T20
CPU1_THRMTRIP#_R_MN
0
LVDSB_DATA_3
THERMTRIP#
CPU1_THRMTRIP#
N33
49-C3
PM_EXT_TS#_0
26-B2
A37
P32
10-C4,20-B1
LCD1_BCLK
LVDSB_CLK
PM_EXT_TS#_1
26-B2
B37
LCD1_BCLK#
LVDSB_CLK#
N28
DDPC_CTRLCLK
R48
2.4K
1%
C44
M28
LVDS_IBG
DDPC_CTRLDATA
34-B3
21-C1,25-A4
30-B3,32-C3
B43
LVDS_VBG
PLT3_RST#
E37
G36
R539
100
LVDS_VREFH
SDVO_CTRLCLK
1%
P3.3V
E38
E36
LVDS_VREFL
SDVO_CTRLDATA
NC
RSVD
B28
K36
R637
10K
1%
HDA_BCLK
CLKREQ#
A28
R588
10K
1%
HDA_SYNC
B30
H36
HDA_RST#
ICH_SYNC#
P3.3V
B29
B12
HDA_SDI
TSATN#
R585
4.7K
C29
HDA_SDO
MCH3_CLKREQ#
MCH3_ICHSYNC#
P1.05V
P3.3V
P1.05V
IGFX_CORE
ME Debug Port
R548
56
R636
10K
EC504
A
C598
C595
C557
C553
C596
MCH3_CLKREQ#
A
220uF
10000nF-X5R
10000nF
1000nF-X5R
100nF
100nF
2.5V
6.3V
6.3V
6.3V
10V
10V
AD
DRAW
DATE
TITLE
SY.KIM
9/23/2008
SAMSUNG
BONN-L
22uF->10uF
470nF->100nF
CHECK
DEV. STEP
220uF->100uF
ELECTRONICS
HK.PARK
PR
MCH_CANTIGA_GM_DDR2
APPROVAL
REV
PART NO.
CANTIGA (2/5)
H.J.KIM
1.2
BA41-
MODULE CODE
LAST EDIT
For ESD
14
49
undefined
June 03, 2009 16:14:25 PM
PAGE
OF
4
3
2
1
D:/users/mobile64/mentor/r519/pr_re1.1_0603
50V
50V
50V
0.033nFC588
0.033nFC589
0.033nFC590
150R577
1%
1%150R578
150R581
1%
TV
VGA
LVDSHDA
A43
H44
NC_1
PEG_RX#_0
A44
J46
NC_2
PEG_RX#_1
A46
L44
NC_3
PEG_RX#_2
A47
L40
NC_4
PEG_RX#_3
A5
N41
NC_5
PEG_RX#_4
A6
P48
NC_6
PEG_RX#_5
B4
AE16
AA15
N44
NC_7
VCC_AXG_NCTF_8
VCC_AXG_1
PEG_RX#_6
B45
AE17
AA20
T43
NC_8
VCC_AXG_NCTF_9
VCC_AXG_2
PEG_RX#_7
B47
AE19
AA21
U43
NC_9
VCC_AXG_NCTF_10
VCC_AXG_3
PEG_RX#_8
B48
AF16
AA23
Y43
NC_10
VCC_AXG_NCTF_11
VCC_AXG_4
PEG_RX#_9
BC1
AF17
AA24
Y48
NC_11
VCC_AXG_NCTF_12
VCC_AXG_5
PEG_RX#_10
BC48
AF19
AA25
Y36
NC_12
VCC_AXG_NCTF_13
VCC_AXG_6
PEG_RX#_11
BD1
AG16
AB15
AA43
NC_13
VCC_AXG_NCTF_14
VCC_AXG_7
PEG_RX#_12
BD48
AG17
AB20
AD37
NC_14
VCC_AXG_NCTF_15
VCC_AXG_8
PEG_RX#_13
BE2
AG19
AB23
AC47
NC_15
VCC_AXG_NCTF_16
VCC_AXG_9
PEG_RX#_14
BE47
AH16
AB25
AD39
NC_16
VCC_AXG_NCTF_17
VCC_AXG_10
PEG_RX#_15
BF1
AH17
AC20
NC_17
VCC_AXG_NCTF_18
VCC_AXG_11
BF3
AH19
AC21
H43
NC_18
VCC_AXG_NCTF_19
VCC_AXG_12
PEG_RX_0
BF46
AJ16
AC23
J44
NC_19
VCC_AXG_NCTF_20
VCC_AXG_13
PEG_RX_1
BF48
AJ19
AC24
L43
NC_20
VCC_AXG_NCTF_21
VCC_AXG_14
PEG_RX_2
BG1
AK16
AE15
L41
NC_21
VCC_AXG_NCTF_22
VCC_AXG_15
PEG_RX_3
BG2
AK17
AE20
N40
NC_22
VCC_AXG_NCTF_23
VCC_AXG_16
PEG_RX_4
BG4
AK19
AE21
P47
NC_23
VCC_AXG_NCTF_24
VCC_AXG_17
PEG_RX_5
BG45
AK20
AE23
N43
NC_24
VCC_AXG_NCTF_25
VCC_AXG_18
PEG_RX_6
BG47
AK21
AE24
T42
NC_25
VCC_AXG_NCTF_26
VCC_AXG_19
PEG_RX_7
BG48
AL16
AE25
U42
NC_26
VCC_AXG_NCTF_27
VCC_AXG_20
PEG_RX_8
BH2
AL19
AF15
Y42
NC_27
VCC_AXG_NCTF_28
VCC_AXG_21
PEG_RX_9
BH3
AL21
AF20
W47
NC_28
VCC_AXG_NCTF_29
VCC_AXG_22
PEG_RX_10
BH43
AM16
AG15
Y37
NC_29
VCC_AXG_NCTF_30
VCC_AXG_23
PEG_RX_11
BH44
AM17
AG21
AA42
NC_30
VCC_AXG_NCTF_31
VCC_AXG_24
PEG_RX_12
BH46
AM19
AH15
AD36
NC_31
VCC_AXG_NCTF_32
VCC_AXG_25
PEG_RX_13
BH47
AM20
AH20
AC48
NC_32
VCC_AXG_NCTF_33
VCC_AXG_26
PEG_RX_14
BH5
AM21
AJ15
AD40
NC_33
VCC_AXG_NCTF_34
VCC_AXG_27
PEG_RX_15
BH6
U16
AJ21
NC_34
VCC_AXG_NCTF_35
VCC_AXG_28
C3
U19
AL15
J41
NC_35
VCC_AXG_NCTF_36
VCC_AXG_29
PEG_TX#_0
C46
U20
AM14
M46
NC_36
VCC_AXG_NCTF_37
VCC_AXG_30
PEG_TX#_1
C48
U21
AM15
M47
NC_37
VCC_AXG_NCTF_38
VCC_AXG_31
PEG_TX#_2
D2
V16
AN14
M40
NC_38
VCC_AXG_NCTF_39
VCC_AXG_32
PEG_TX#_3
D47
V17
T14
M42
NC_39
VCC_AXG_NCTF_40
VCC_AXG_33
PEG_TX#_4
E1
V19
T16
R48
NC_40
VCC_AXG_NCTF_41
VCC_AXG_34
PEG_TX#_5
E48
V21
T17
N38
NC_41
VCC_AXG_NCTF_42
VCC_AXG_35
PEG_TX#_6
F1
V23
U14
T40
NC_42
VCC_AXG_NCTF_43
VCC_AXG_36
PEG_TX#_7
F48
V24
U15
U37
NC_43
VCC_AXG_NCTF_44
VCC_AXG_37
PEG_TX#_8
V25
V15
U40
VCC_AXG_NCTF_45
VCC_AXG_38
PEG_TX#_9
V26
Y15
Y40
VCC_AXG_NCTF_46
VCC_AXG_39
PEG_TX#_10
AH10
V28
Y21
AA46
RSVD_1
VCC_AXG_NCTF_47
VCC_AXG_40
PEG_TX#_11
AH12
W16
Y24
AA37
RSVD_2
VCC_AXG_NCTF_48
VCC_AXG_41
PEG_TX#_12
AH13
W17
Y26
AA40
RSVD_3
VCC_AXG_NCTF_49
VCC_AXG_42
PEG_TX#_13
AH9
W19
AD43
RSVD_4
VCC_AXG_NCTF_50
PEG_TX#_14
AK34
W20
AC46
RSVD_5
RSVD11
VCC_AXG_NCTF_51
PEG_TX#_15
AL34
W21
RSVD_6
RSVD10
VCC_AXG_NCTF_52
AM35
W23
J42
RSVD_7
RSVD13
VCC_AXG_NCTF_53
PEG_TX_0
AN35
W24
AA16
L46
RSVD_8
RSVD12
VCC_AXG_NCTF_54
VCC_AXG_NCTF_1
PEG_TX_1
AY21
W25
AA19
M48
RSVD_9
VCC_AXG_NCTF_55
VCC_AXG_NCTF_2
PEG_TX_2
B2
W26
AB16
M39
RSVD_10
VCC_AXG_NCTF_56
VCC_AXG_NCTF_3
PEG_TX_3
B31
W28
AB17
M43
RSVD_11
VCC_AXG_NCTF_57
VCC_AXG_NCTF_4
PEG_TX_4
BF18
Y16
AB19
R47
RSVD_12
VCC_AXG_NCTF_58
VCC_AXG_NCTF_5
PEG_TX_5
BF23
Y17
AC16
N37
RSVD_13
VCC_AXG_NCTF_59
VCC_AXG_NCTF_6
PEG_TX_6
BG23
Y19
AC17
T39
RSVD_14
VCC_AXG_NCTF_60
VCC_AXG_NCTF_7
PEG_TX_7
BH18
U36
RSVD_15
PEG_TX_8
K12
U39
RSVD_16
PEG_TX_9
M1
Y39
RSVD_17
PEG_TX_10
M36
Y46
RSVD_18
PEG_TX_11
N36
AA36
RSVD_19
PEG_TX_12
R33
AA39
RSVD_20
PEG_TX_13
T24
AD42
RSVD_21
PEG_TX_14
T33
AD46
RSVD_22
PEG_TX_15
DMICLKMEPMMISC
http://mycomp.su/x/
4 3 2 1 SAMSUNG PROPRIETARY THIS DOCUMENT CONTAINS CONFIDENTIAL PROPRIETARY INFORMATION THAT IS SAMSUNG
4
3
2
1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
PLACE EACH CAP NEAR AV42 PIN
MEM1_ADQ(63:0)
MEM1_VREF
0
1
2
3
4
5
6
7
8
9
10 11
12 1314 1516 17 18 19 20 21
22 23 24 25 26 27 28 29 30 3132 33 34 3536 37 38 39 40 41
42 43 44 45 46 4748 4950 51
52 53 54 55 56 5758 59 60 6162 63
C651
C650
100nF
100nF
MEM1_SM_REXT_MN
10V
10V
R46
499 1%
nostuff
nostuff
D
MEM1_ABS(2:0)
D
0
BD21
BF17
SA_BS_0
SM_REXT
1
BG18
AV42
SA_BS_1
SM_VREF
MEM1_VREF
SM_PWROK
2
AT25
SA_BS_2
BC36
DDR2 : GND
MEM1_ADM(7:0)
SM_DRAMRST#
0
AM37