Rising edge/falling edge

Truth Table

D FF with asynchronous input

Rising Edge Triggered D Flip-Flop with Asynchronous Preset and Clear

Rising Edge Triggered D FlipFlop

library ieee; use ieee.std_logic_1164.all; ENTITY dff IS PORT( D, Clk, Clr, Pre : IN STD_LOGIC; Q, Qbar : OUT STD_LOGIC); END dff; ARCHITECTURE behavioral OF dff IS BEGIN PROCESS(Clk) --We only care about Clk BEGIN IF (Clk'event) AND (Clk='1') THEN -- Positive Edge Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral;

Rising Edge Triggered D FlipFlop - alternate

ARCHITECTURE behavioral2 OF dff IS BEGIN PROCESS(Clk) --We only care about Clk BEGIN WAIT UNTIL Clk='1' -- Positive Edge Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral2;

 process(C,Clear) begin if (Clear) then Q <= '0'; elsif (rising_edge(C)) then if (R = '1') then Q <= '0' ; elsif (S = '1') then Q <= '1' ; end if; end if; end process;

D Latch
library ieee; use ieee.std_logic_1164.all ENTITY gated_D IS PORT( D, Clk : IN STD_LOGIC; Q, Qbar : OUT STD_LOGIC); END gated_D; ARCHITECTURE behavioral OF gated_D IS BEGIN PROCESS(D, Clk) BEGIN IF Clk = '1' THEN -- Implied memory Q <= D; Qbar <= not D; END IF; END PROCESS; END behavioral;

SR Flip Flop
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY SRff IS PORT ( S, R, Clock, Clear: IN STD_LOGIC; Q: OUT STD_LOGIC); END SRff; ARCHITECTURE Behavior OF SRff IS BEGIN PROCESS(Clock, Clear) -- sensitivity list is used BEGIN IF (Clear = '1') THEN Q <= '0'; ELSE IF Clock'EVENT AND Clock = '1' THEN IF (R = '1') THEN Q <= '0'; ELSIF (S = '1') THEN Q <= '1'; END IF; END IF; END IF; END PROCESS; END Behavior;