Table of Contents

Topic Title Page Acknowledgement ABSTRACT Page No. i ii iii

1. Introduction 2. Flash Memory 2.1 History 2.2 Principle of Operation 2.3 Programming 2.4 Erasing 3. SONOS 3.1 Principle of Operation 3.2 Vertical Type 4-Bit SONOS and Its Scaling Issue 4. Unique 3-D Vertical NOR Array(U3VNOR) 5. CELL OPERATION OF THE U3VNOR 5.1Operation Voltage Scheme 4.1 Simulation Models and Method 4.2 Operation Simulation Result 4.3 PCI and Scaling Limitation of the U3VNOR 6.Advantages of U3VNOR 7.Conclusion 8. References

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Figures 1.1. Programming of a Flash memeory cell 1.2. Erasing of a Flash memeory cell 2. SONOS memory cell 3. Vertical Type 4.bit SONOS 4. Leakage current vs fin width 5. 3-D depiction of the U3VNOR array structure 6. Top view of the U3VNOR array 7. Critical fabrication steps 8. Equivalent circuit of the U3VNOR 9. Voltage operation scheme including float condition 10. Parallel reading scheme for bottom bits 11. Parallel reading scheme for top bits 12. Birds eye view of the U3VNOR structure 13. Changes of a trapped bit charge during CHEI 14. Changes of a trapped bit charge during HHI erase 15. IV characteristics of the U3VNOR 16. PCI phenomenon versus fin width

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