Return Received: by jupiter ranbus.com (6.2/SH2-4.1) 06:36 2ST Td AALGSO7: Tue, 16 Feb 93 From: geate (Geof! Tate! Sessage-14: <9302170006.AA1650792up: Syne DRAMS / High Bandwidth 16 Feb 93 16:06:36 PST version 2.3 PLII1 ny SE Times and Electronic Suyers News MrgHLTGHTS nouncing competing 1éMbic Sync ORAKS chis week rooms Sansung - sampled a few accounts: general sampling by march. fterences Detween Samsung, NEC and JEDEC standards samsung clains Oki as second source and IBM as major custoner, NEC claims it is ~aligned* wich JEDEC standard coshiba, Fujitsu. Hitachi, Miteubishi, Micron all say they'll sample in 2nd fal and “tine up’ with JEDEC standard. coments that the JEDEC standard is an ‘envelope’ and it will be like VANS Shere the concepts are the sane but che vendor's parts all differ in decail site hope £0 have LVTTL working at 100Mhz on the chip” sai Micron‘s VP narketing. "Sur somewhere Detween 66 and 7Svhz, the bus design gets very Iienging. At 100Mhz you have a design you don't give to an engineer ‘of college. You may have a design that’s only doable on @ module. feat that speed you have to read che specs carefully or you are 9 th get Danboozled by the vendors, It may say you can do i00Mhe, but fe print it mentions that che latency goes way up.” ECTRONIC BUYERS NEWS HIGHLIGHTS availability of SDRAMs now secs che stage for a brewing bactle will be wage Between SORAMS and a competing memory interface being Licensed by Ranbus ine." Sansugn seid st $2 pricing its SDRAMS at 2 208 premium over comparable asynchronous (commodity) DRAM {CROPROCESSOR REPORTS Microprocessor Report is doing a 3-part story on High Bandvidth memories. Pare f showed up in today's edicion. I’ve got if posted outside my cube OUTSIDE COUNSEL ONLY Resear ¢x0688-001 |they cover ‘evolutionary: architectures in part 1. Rambus will be in part 2 Dcomparigon will be in part 3 Lights: ce going up in size faster than computer main menory systems - s0 the fof DRAMs in a system has decreased significantly. Also ister than SRAM speeds, (sound familiar so ‘the end result is a growing gap between che capabilities of menory systens and feds of che processors Co which they are connected. This trend is speceiily pronounced at the low end of che spectrum where low cost, Simplicity and small size are crucial Wider page ode DRANG - helps but not for long: and can‘t go much wider, Syne DRAM = 3.3V LVTTL 66¥hie. “LVTTL signal quality will be inadequate at, Towne for most memory system.” “The question that che marketplace will iitimately answer is whether SORAMS provide adequate Dandwidth and design Facility to serve as a long-term replacement for the current interface or whether a nore revolutionary alternative will also be needed by mainstrean DRAM applicacions.* ISSCC HIGH-BANDWIDTH MEMORY PANEL Richard Crisp has gone te # lot of work to set up @ panel session at ISSCC fo discuss the meriea of the energing high-bandwidth architectures, Mike Farmwald will be on che panel evangelizing the Rasbus view siary is increased calk about SDRAMS, RORAMs, etc. is great. We're not going ali of the Limelight but it ail of the talk makes people nore receptive co a) Listening and b) taking action, In the end. che marker needs vs. the technology alternatives’ features and Benefits will setile matters. And on that score we win: personal/porceble. systens need HIGH bandiwdth out of FEW drans and Ranbus does it. The syne ‘DRAM guys are at S6Mhz / 100Mhz for CHIP-specs (derace to reality after Going the interconnect design). Ranbus cones with the interconnect selution provided. Rambus is 5-8 times faster ar the same cost with # single Standard. . FYI. Geott OUTSIDE COUNSEL ONLY Risser? ¢x0688-002 |