Return-Path: Received: from Dialupfudora (jupiter) by 2upiter-rambus.com (¢.1/SMI AA27670; Wed, 15 Mar 95 18:03:34 PST Message-Id: <9503160203 .AA27670@jup2: Dace: Wed, 15 Mar 1995 18:01:20 -0800 To: bdnarket, exec From: crisp@jupiter (Richard Crisp) X-Sender: crispéjupiter (Unversfied) Subject: je42 Meeting (DRAM and SRAM! ce: erisp -rambus.com> Hallway chaccer/G2 x found out that Hyundai is having a discussion in April to decide on the next round of the projects they plan on developing. GM Han (che guy working for K.H. Ho (the technical marketing guy}) told me that he wants to discuss 2 few itens while we are together. I have asked him to have dinner with me Conight, which he has agreed to do. Farhad walked up as we finished our conversation. so he may try to figure out what is up and may try to kill che discussion, time will tell Willi Meyer of Siemens asked me about what I know of the discussions between Sienens and us. He said that when Michell was in last time that the issue of die size adder cane up. He said that Jeff cold him something less chan 108 but he said that they had seen a die photo from the press just before the meeting (I don’t think chat he told Jeff about chis!, and their estimate was that the adder was more like 208. I spent time with him explaining how the numbers are different for different suppliers, why they are different, and the sort of things affecting it (metal 2 pitch, core rules vs periphery rules, standard cells versus hand pack etc] He also said they are trying to figure out what we compare against. I told that we try to compare die size against devices of the same organization with the same design rules (like 2Mx8) He told me that 64M is still an option but they do not think they will do a 16m. I cold him that we will have @ significant advantage over other 64H devices useful in PCs. I went through the big differences in the organization needed for 64M of use in PCs versus the needs for servers and mainfranes (ie the server/mainfrane part is a xl or a x¢ not a x32 or a x6¢ (or even a x128]). Willi seened to understand this and his body language said chat he agreed even though he did not make that statement. I further stated that there was a lot of volume happening in the iémeg density for us in 1996 in the PC execution memory. I quickly went through the multinedia Story performance/cost and motherboard space issues. I also explained to him how the Taiwan guys selling motherboards like the fact chat they can put a whole system on the motherboard using our technology and how their OEM customers like the fact that they save money by buying a fully integrated motherboard. I hope he walked away with a bit of new information/ideas about how we are going to be used over che next A2-LBmonths especially in the 1émeg generation. So maybe this will help chen along? During the pacent review session it was noted that ATT has a patent on EDO. ‘They are now trying to figure out what the patent covers and what policy ATT will adopt relative to licensing OUTSIDE COUNSEL ONLY Rissass ‘x0786-001ie was also noted that there may be sone 39 RAM activities being included An the JCé2 meetings in the future. Apparently there is enough interest a the indusery in the 3D area to maybe justify work in standardization in che graphics RAM area. 2 noticed that Farhad has had the Ranlink spec printed along with sone overview slides and he has distributed this to certain individuals (MOSAZD included). Foss told me that he did not know anything about ::. and that ne pust received it this morning I have downloaded the latest spec from the HP Labs server. It is in scrisp/ramlink directory, I will check to ensure that the protections are set properiy so that others can access it. Since it is in Adobe Acrobat forrat (why did they change from Frane????), I had to downoad an Acrobat viewer too. So grab both files in che directory if you want 2¢ viewer only rund on the Mac by the way. If someone would print ir out before I return on Thursday afternoon, then he ecture guys can get a look at it earlier. 2 spoke with Mitsuo Yasuhira of Marsushica today (we had lunch together! He is representing Matsushita at this JEDEC meeting. He is actually a processing type guy, but seems to have knowledge about system issues as Weili2?). I wanted to make sure he knew that we had the Nintendo design-in and what the reasons were, We went over the pincount and the Gollars/megabyte for 16M vs 4M issues. He was obviously impressed and the comparative photos of the other PCI graphics cards made a strong impression on Rim. I told him that even if they were not interested in developing RORANS, they will find that che use of the RORAMS will save then a lot of y Of Of graphics and video type products. I specifically mentioned savings of pins and die area for MPEG decode, settop box, and other digital video products. I also suggested that in the area of Digital TV and or ai VCR/Cancorder, be visiting 300 on Thursday and may have time to vist us later in |. Ewill be a bit surprised if he has time tomorrow, but he did say he'd be happy to put us in touch with the right development people in jach of che above named areas. I told him that would be great and thanked fe interest in developing RORAMS for hire. I said that from time to time some of companies we work with may not have a design team ready co do the job or may be only interested in manufacturing, not designing. He said they would be very interested in this. He will be in the bay area next week s0 we will see if we can have an informal discussion on Friday or Saturday next week. z had a brief discusion with DY Park of Samsung right after lunch. He told me that they are thinking about developing the OMbit RORAM. He says that Cirrus was speaking with them recently about it and that they were very impressed by the strong level of support Cirrus has for Rambus. Currently he said the tapeout date is in the third quarter of 95:1 I am not sure if he is weli plugged into Choi or not. I had believed that the design is staiied at the moment based on the last enail from Allen regarding che terest Choi has in meeting with our engineering guys. lips of IBM [the guy that presented the data taken from the SDRAN OUTSIDE COUNSEL ONLY Rissess ‘cx0786-002Samsung presented their timing diagrans for their Pipelined Burst £D0 DRAM. The major issues are how to terminate the burst. Causing WE to cransition while CAS is low is one of the methods discussed. Also causing WE to transition while CAS is high is another way. Both methods are used in their proposal depending cn how one wants to use the device in terns of what type of cycle combinations are needed. Their proposal focused only on the functionality, not the organization but are 16M generation 1mxl6. The idea is for use in main memory. Micron wants no graphics featu: the devices. This is great since it will make it tougher to use these in unified designs. I know I have been hearing about folks thinking about developing unified designs using wide EDO. By the way, the name is now Pipelined Nibble Mode rather than Pipelined Burt EDO Ti would 1ike to make CAS latency #1 optional rather than required as don't see anyone using it since everyone wants the highest clock rate SDRAMS. Mosaid suggested removing the CS access latency of zero so as to permit lower non chipselected power. He says the typical standby power at 100M: greater than 100nW for devices deselected by chip select. He says that the nunber of pins will be further increasing as the clock rates increase. He says the time to do this is for 64M and beyond. First showings ‘Toshiba presented a 16M SDRAM (x32 organization) in a 100pin POFP for compatibility with the 6M SDRAM, No block write is supported. 300 presented a 16M SDRAM (256Kx32x2 organization) in a 100pin POFP and also an 8M (single bank device) in the same package. The committee is Viewing these as second showings as they are so similar to the existing standards. Graphics Memories ‘The @M SGRAMs all passed council (100 pin pafp and tsop2). The 8M SVRAM (20pqép) also passed council. The 4M SGRAM TSOP2 also passed council ‘The @M SVRAM (100pin POFP) ballot passed. The 6M burstmode VRAM truth table ballot aisc passed. Both were sent to council, TE presented a 16M SDRAM (SGRAM) (512x512x32x2banks (256Kx32 x 2banks) Zt has LVTTL/HSTL interfaces. The speed target is 80-125iGiz. It uses the SDRAN truth table. It is in a 70 pin TSOP2 package. Operating at 125mhz, it would deliver 500mB/sec peak bandwidth. 3D0 presented a 16M SGRAK. Theirs is in a 100pin POFP (20mmxiénm). Their goal is to be able to make a small change to the pinout of the 100pin aM SGRAM (add another address) to make for an easy density upgrade (at the sane bandwidth, or half the BW/MB) OUTSIDE COUNSEL ONLY Rissesé ‘cx0786-003