soram rage 1 ore Subject: JEDEC Meeting Notes 2/27, 2/28 T staff To: garrett JEDEC 42.3 Meeting Seattle Washington, Feb. 27-28 1992 Attended by Billy Garrett INTERESTING TID-BIT. Fujitsu submitted a proposal for 16 Mbit generation DRAMS in x8, x4 and x1 configurations in the VSMP package. They provided details of the package. showed a sample and said something like: "You will see introduced in the next two weeks a high-speed ORAM running at 500 MHz reported in EE Times." Obviously, | was surprised, but no one in the room flinched (| suspect most of them know about us). Fujitsu indicated that they do have patents applied for, but that they will comply with the JEDEC requirements to make it a standard!!! Notes from Sync DRAM sessions. | have copy of Patent list. Included in stack of documents. The expectation is that people are moving rapidly toward a consensus on SDRAMs. Howard Sussman from NEC is really pushing this issue hard, and wants to get consensus in the next few meetings. Everyone thought that an additional meeting would be necessary, so April 8,9 in Dallas (hosted by TI) will be the next ad-hoc meeting. A regular meeting wil be in May with another full (special Sth meeting this year) scheduled in July. | expect a ballot in either May or July. No idea yet on if everyone will/can agree on the details. Everyone reached agreement that a LVTTL (low-voltage TTL, which is apparently a standard from JC-16 (which by the way someone from Rambus should attend just for info)) part could fit in a 34 pin SOJ type package, although much discussion centered on the fact at a 44 pin TSOP package would have the same footprint, and give many more pins for future expansion. Many are interested in GTL for the highest speed SDRAMs, but they realize that this won't fit in a 34 pin SOJ package. As for I/O, everyone agrees that at about 100MHZ signals will have to be terminated, that it cannot be rail-to-rail, and that it cannot rely on an internal Vref (i.e. that there would be an external Vref). There was no general consensus. Howard Sussman will remain the focal point on the pinout/functionality of the parts. The committee is very interested in getting a GOOD standard issued as soon as possible. It does not want to issue a BAD standard, nor does it want vendors coming out with many in-compatible parts. Although everyone says that they will conform to the final standard, | get the feeling that several companies (i.e. TI and NEC) will introduce parts (or announce or sample or talk about) SDRAMs of their own design this year. | think most people believe that the regular 16 Mbit DRAM will reach crossover early next year (putting price pressure on 4 Mbit generation parts) and that SDRAMs will get into volume in 1994. | think itis felt that 100MHz and above will be later than that. The committee is going to work hardest on a LVTTL (3.3V supply) standard first, but provide quick (i.e. six months) standards emerging for reduced voltage-swing parts. ‘We could influence the voltage standard if we want, or we could use our patents to keep Current-mode interfaces off of DRAMs (assuming that is what we patented it that way and that is what we want to do). SDRAMs will happen. They may happen sooner than we want, and they may become quite standardized and highly multi-sourced. | also met Francoise Le-Mouel from HP. Her title is DRAM/VRAM Manager. She said that she wants to make sure all design centers in HP are aware of Rambus, and that they can consider their use without Desi's blessing. She said that they have some sort of update meeting in late March and that she would like us to come and present at that. I'l let David Vornholt contact her; she has requested current information. | also met with two people from Siemens (Willi Meyer and Johann Harter). The latter is involved in the Siemens/IBM 64Mbit DRAM development and is very interested, especially in partials! Please look carefully through the presentations. Fujitsu's presentation was particularly good and well thought of. Mitsubitshis is very different than December, recommending a 44 pin TSOP. Much interest in this. HP, Sun and Intel stated their desires for SDRAMs (VERY IMPORTANT, READ THROUGH THEM). What has happened in the last week borders on the remarkable. There is general agreement on two banks and two RASes (NEC is just about the lone hold-out pushing for pulsed RAS). Many discussions on pins/pinout and package type. General notes on JEDEC. The beginning of the R 200470 OUTSIDE COUNSEL ONLY ‘x0672-001soram Fuge =u meeting started with the 64M proposals, which have been in front of JEDEC for several meetings. The group spent at least two hours discussing CBR refresh. Many people want it stated that this is the ONLY way 64M's will be refreshed, but there was a long protracted discussion on 2K vs 4K refresh for those not using CBR. Just a note on how much. disagreement there was on how to explain refresh preference (since in reality you cannot prevent a user from refreshing by accessing all the rows himself). This would seem to indicate that detail specifications on Sync DRAMS will be a long way off. But you never know. Billy OUTSIDE COUNSEL ONLY R2oo47h ‘x0672-002