‘e Lhouphs on cieks and ULL
‘Subject: Re: Thoughts on clocks and DLL.
Date: Wed, [3 Mar 1996 10:44:15 -0800
From: adiepenb@jupiter (Tony Diepenbrock)
‘To: roberts@jupiter (Allen Roberts)
20n the clocking pacen
portant. I suggest we do 4 very
'@ clains pethaps even with 2 third party (Hocowite, £4 f
2797) before we allow the patent co issue,
2¥ou brought up 4 good point about the phase relationship. £ don't think
othis 1s in the original teachings, but 1 could be wrong
Dear Allen,
just to check I ran a word search on the ‘755 patent, the original filing
in Apeil of 1990, for “edge.” The word is only used in conjunction with the
clock recovery circuit in which the internal clock is positioned in tine
halfway between the two external clocks. The wards “odd cycle" and “eves
cycie" are used to describe the transmission and reception of data int}
bus interface portion of the memory device. An add cycle 19 defined 23 the
time when the internal clock is a 1 and an evan clock is defined as ene
time whenthe internal clock is a0, The input receivers are then described
a8 clocked receivers which receive odd cycle input and even cycle inputs
The operation of the output drivers is a little more vague. The output
dkivers are described as using the internal clock and internal clock
complement to drive the interface
Fethaps both of these descriptions would lead one skilled in the art to
ude that bus signals are transmitted and received *=during™* the txo
Phases of the intecnal clock and not on the **edges"* of that clock.
Tf "in response to an edge of a clock” is used to mean the operation of an
edge triggered device as opposed to a level operated device, this use could
imply a structural difference in the circuits discussed above
So there are two problems here. The first is that the specification does
fot support the use of "edge" in conjunction with the driver and receivers
instead it discusses the operation of these circuits in terms of periods of
the internal clack.
Second, is that "in response to an edge of a clock" may be used to imply
Structural distinction that was never intended. I'm sue whoever wrote the
clains thought that there was no difference between the language of tne
claim and the language of the specification and thus simply employed tne
language without out too mich care.
The general rule for claims interpretation is that the clains are
interpreted in light of the specification and prosecution history. Using
Seis rule one would certainly argue that the claims mean that the ciecustey
operates during the phase of the internal clock and that the phase starts
in response to an edge of the clock.
As a result I'm not sure that there is enough here to justify withdrawing
the application from issue.
RH 386344
AS a general point x agree that we should review the claims in Povlc2
Towards that end I can send Mark Horowite a copy of the claims as T nave R 233850
diagramed then. OUTSIDE COUNSEL ONLY
of 42002217 EM
“ex0871-001Re: Thoughts on locks and DLL
As a backup situation we will try to claim the input and output
a more Broad fashion in POOIC3, the application which will be fi
fhe prosiene with 755)
a to fix.
Limit this concept ta mem
know of any examples) that
chips wien
tks have used
The Claims in POULCZ are limited to either DRAMs or memory storage system:
20n che PLE/DLL on ORAMS
>the idea here is for active (feedback) clock compensation on ORAMS with 4
pelock (periodic waveform). I don't think chis ig wnat the current claims
bare for
The current claims for this feature are contained in P0070, in which the
claims protect a menory device having a memory artay, a clock signal
Feceiving circuit for receiving an external clock and generating a local
Glock signal and a PLL connected to the clock signal receiving circuit and
for providing a variable delay to the local clock signal so that if is
Synchonized vith the external clock signal.
This is a pretty broad claim, but che problem with it is that word, PLL, is
never used in the specification. In fact, there is no mention of a’ phase
jockled) loop or a any kind of iock(ed) loop or any kind of loop at all. So
the interpretation of the word PLL would be in accord with its ordinary
meaning, according to a 1988 Federal Circuit Case. This means that PLL
could be interpreted to mean a PLL with a VCO, and not a DLL (using those
terms as Rambus would use them), So what does this claim cover? Doss it
cover OLL implementations?
To get around this interpretation problem I have instructed outside counsel
to Fedraft the broad claim so that the functionality is claimed without the
use of the words DLL or PLL
Language such as
"means for continuously and actively maintaining @ constant phase
relationship Between the local clock signal and external clock signal so
that the skew between the two signals is minimizes
might say what we want better,
Fhis language would read on any implenentation of such a clock compensation
loop. Again there still is the question of whether the specification
supports such a broad claim.
I should point out, however, that some very damaging prior art was recently
“discovered” py Richard Crisp. Richard brought to light a presentation done
at ISSCC by MIPs some time before April of 1990. This presentation shews
MIPS using a DLL (as ve understand the term) to remove clock skew between @
Processor and a coprocessor which share the same bus
This puts into question wnether we can obtain the claims as they stand in
P0O7D. The only thing that may save the claims is that (1) we use a StL on
a menory device and MIPS used the DLL on a processor device and (2) we are
solving’a slightly different problen than the problem that MIPs solved. We .
are using active clock compensation te minimize timing losses so that the RH 386345
system can have a very fast clock. MIPs purpose was to prevent bus crashes
between the two processors.
R 233851
‘OUTSIDE COUNSEL ONLY
“ex0871-002ots
2 hope the shove discussion addresses your coi
know what I have not covered so that T nay act
, please Let me
RH 386346
R 233852
‘OUTSIDE COUNSEL ONLY
2902217 PSE
“ex0871-003