Rambus Confidential: Approved QUA for ls patent ‘Subject: Rambus Confidential: Approved Q&A for latest patent Date: Fri, 15 Aug 1997 19:16:45 -0800 From: mclarke@rambus.com (Michele Clarke) To: exeo@rambus.com, bdmarket(@rambus.com ch juguee 12tn, Ranbus was issued the following patent Patent No.1 §,687,481 ("Rambus ‘481 le! Memory Cavice With Phase Locked Loop Cir: oe Date 1397 Filing date: vovenber 15, 1996 Sority Date: Apri! 13, 1990 ainsi 18 with S independent claims ‘She 5 independent claims cover the following ia) A memory device that ceceives an external clock and creates = local Glock and includes phase locked loop circuitry which varies the delay of the Loeai clock signal to create an internal, syncnconized clock to operate the interface ciscuitry on the menory device (b) A computer system having a bus, a bus master and the menory device in (3) {c} R memory device as in (a) but also having an input receiver that is used to sample the external clock. (a) A senory device as in (a) but having phase locked leop circuitry sample the external clock to produce an internal clock synchronized to the external clock and having a controlled phase relationship with the external Shock (s) A memory device in a computer system having a multiline bus, the mencry device as in (a) but also having a receiver circuit coupled to the multiline bus for receiving address, data and control information. Since sone media outlets (e.g, The Microprocessor Report) report on the Granting of such patents, and since this patent covers fundamental memory hnolagy, we've created a ‘party line’ to nelp addrese any inquiries. 7 responses have been approved by legal, so if someone asks something that's not covered here, please try to get back to the person with the answer, pis. let me know if anytaing's unclear. Thx, Michele This patent Ls broad in scope. What, specifically, does this patent cover? Ar It covers memory devices with phase-locked loop circuitry as well as the bus-based system designs that employ these devices. We still need to evaluate which specific memory devices come under the scope of this patent (02: Do synchronous ORAMS (SDRAMS} use this patent? Ar If a memory device does not incorporate phase-locked loop circuitry, it Soesn't come under the scope of this patent. Q3: D0 Couble bata Rate (ODR) SDRAMs use this patent? We don't know yet. No O0R products exist for us to evaluate. 04: Do SyncLink DAAMS (SLORAMS) use this patent? Ar We don't know yet. No SLORAM products exist for use to evaluate. QS: Co static RAMS (SRAMS) use this patent? Which SRAYS use this patent? 63 A: We don't know yet. We still need to evaluate which specific menory baked Gavices cone unaef the scope of this patent. Q6: Wii Rambus seek royalties from SRAM companies? R 233869 ‘OUTSIDE COUNSEL ONLY "ex0948-001“amus Contigenal: Approved Q&A fr last gent Ar Since we don't yet know if SRAHS come under the scope of this patent, ‘not prepared to comment at this tine thig patent mean that you've patented a conputer system design av uses 4 bus, a bus master, and enory? A: tio, it means that we've patented a computer system design that uses 3 bus, a bue master aad chiz particular type of memory G8: Will Rambus 30 after systems companies who ship at violates Ranbus patents? products using nenory nstant in this req meus just being greedy? Ai An essential part of the Rambus business medel is the creation and Licensing cf intellectual property. Tais patent is fundarental to our business 10: When was this patent filed? How Long did you have to wait to get this Patent granted? Ar The date of this patent is April 18, 1990 te RH 386364 R 233870 ‘OUTSIDE COUNSEL ONLY “ex0948-002