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Sudharsan Engineering College

Sathiyamangalam622 501, Pudukkottai (Dt.)

B.E. / B.Tech. Degree - Cycle Test I/ II

Sub Code EE2255 Class : II-EEE Time: 2 hours marks -------- SEMESTER Subject Name: DIGITAL LOGIC CIRCUITS Date : Maximum : 60 Answer ALL Questions PART A (6 x 2 = 12 Marks)

1. What is a data selector? 2. Mention the uses of decoders. 3. Distinguish between combinational & sequential logic circuits.. 4. Give the state diagram of Jk ff? 5. Write the characteristic equation of SR ff? 6. Distinguish between combinational & sequential logic circuits PART B Marks) 7. (4 x 12 = 48

Using Quine Mc Clusky method find all the prime implicants and the minimum SOP for the function F ( a, b, c, d) = m(0,4,5,7,8,11,12,15)
(OR) 8. a) Design a full adder & a full subtractor b) Implement the Boolean function using 8:1 mux.

F (A, B, C, D) =ABD+ACD+BCD+ACD.
9. Design a two bit magnitude Comparator (OR) 10. Design a 4 bit BCD to Excess- 3 code converter. 11. (OR) 12. A sequential circuit with 2 D flip-flops A and B and input X and output Y is specified by the

following next state and output equations. A (t + 1) = AX + BX B (t + 1) = AX Y = (A + B) X i. Draw the logic diagram of the circuit ii. Derive the state table iii.Derive the state diagram
13.a) Realize D and T flip flops using Jk flip flops (OR) 14. Design a mod- 7 counter using JK flip-flops