CADENCE VIRTUOSO

Lab File

AMITY UNIVERSITY
--------------------------UTTAR PRADESH-----------------------------

AMITY SCHOOL OF ENGINEERING AND TECHNOLOGY

INDEX

S.No.
1. 2. 3. 4.

Name of Experiment
To find the Gain from Gain v/s frequency characteristic of CS stage with resistive load. To find the Gain from Gain v/s frequency characteristic of CS stage with diode connected load. To design 2:1 MUX using transmission gate. To design RS Flip-Flop. To Design JK Flip-Flop.

Date

Sign.

5. To design 5 stage Ring Oscillator. 6. 7. 8. To design 8*3 Encoder. To design 3*8 Decoder.

Experiment: 1
Aim: To find the Gain from Gain v/s frequency characteristic of CS stage with resistive load. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory :
A MOSFET converts its gate-source voltage to a small-signal drain current, which can pass through a resistor to generate an output voltage.

Waveforms :

Observations and Result:

The operation of CS stage with resistive load has found to be same as typical one and its gain is coming out as 10.321 db.

Experiment:2
Aim: To find the Gain from Gain v/s frequency characteristic of CS stage with diode connected load. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:
Diode-Connected MOSFET is only a name. In BJT if Base and Collector are shortcircuited, then the BJT acts exactly as a diode. A MOSFET converts its gate-source voltage to a small-signal drain current, which can pass through a resistor to generate an output voltage.

Waveforms :

Observations and Result:

The operation of CS stage with diode connected has found to be same as typical one and its gain is coming out as 10.048 db.

Experiment:3
Aim: To design 2:1 MUX using transmission gate. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:
The multiplexer (or mux) is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. [1] A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to the output. [2] Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called a data selector. An electronic multiplexer makes it possible for several signals to share one device or resource, for example one A/D converter or one communication line, instead of having one device per input signal. An electronic multiplexer can be considered as a multiple-input, singleoutput switch. The schematic symbol for a multiplexer is an isosceles trapezoid with the longer parallel side containing the input pins and the short parallel side containing the output pin. The schematic on the right shows a 2-to-1 multiplexer on the left and an equivalent switch on the right. The sel wire connects the desired input to the output.

Waveforms :

Observations and Result:

The waveform of Multiplexer has been observed and found to be same as the typical one.

Experiment: 4
Aim: To design RS Flip-Flop. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. A synchronous SR latch (sometimes clocked SR flip-flop) can be made by adding a second level of NAND gates to the inverted SR latch (or a second level of AND gates to the direct SR latch). The extra gates further invert the inputs so the simple SR latch becomes a gated SR latch (and a simple SR latch would transform into a gated SR latch with inverted enable). With E high (enable true), the signals can pass through the input gates to the encapsulated latch; all signal combinations except for (0,0) = hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent. With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high. The enable input is sometimes a clock signal, but more often a read or write strobe.

Truth Table:

Action

Restricted combination

Q=1

Q=0

No Change

Waveform:

Observations and Result:

The waveform of RS Flip-Flop has been observed and found to be same as the typical one.

Experiment: 5
Aim: To design JK Flip-Flop. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:
A flip-flop or latch is a circuit that has two stable states and can be used to store state information. A flip-flop is a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J. Similarly, to synthesize a T flip-flop, set K equal to J. The JK

flip-flop is therefore a universal flip-flop, because it can be configured to work as an SR flipflop, a D flip-flop, or a T flip-flop. The characteristic equation of the JK flip-flop is:

Truth Table:
J K Qnext Comment

No change

Reset

Set

Toggle

Waveform:

Observations and Result:

The waveform of JK Flip-Flop has been observed and found to be same as the typical one.

Experiment:6
Aim: To design 5 stage Ring Oscillator.

Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:

A ring oscillator is a device composed of an odd number of NOT gates whose output oscillates between two voltage levels, representing true and false. The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first. A single inverter computes the logical NOT of its input, it can be shown that the last output of a chain of an odd number of inverters is the logical NOT of the first input. This final output is asserted a finite amount of time after the first input is asserted; the feedback of this last output to the input causes oscillation. The stages of the ring oscillator are often differential stages, that are more immune to external disturbances. This renders available also non inverting stages. A ring oscillator can be made with a mix of inverting and non inverting stages, provided the total number of inverting stages is odd. The oscillator period is in all cases equal to twice the sum of the individual delays of all stages.

Fig: 5 stage Ring oscillator

Waveforms :

Observations and Result:

The waveform of Ring Oscillator has been observed and found to be same as typical one.

Experiment:7

Aim: To design 8*3 Encoder. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:

A simple encoder circuit is a one-hot to binary converter. That is, if there are 2n input lines, and at most only one of them will ever be high, the binary code of this 'hot' line is produced on the n-bit output lines. For example, a 4-to-2 simple encoder takes 4 input bits and produces 2 output bits. The illustrated gate level example implements the simple encoder defined by the truth table, but it MUST be understood that for all the non-explicitly defined input combinations (i.e. inputs containing 0, 2, 3, or 4 high bits) the outputs are treated as don't cares.

Truth Table:

Waveform:

Observation and result:

The waveform of Encoder has been observed and found to be same as typical one.

Experiment:8

Aim: To design 3*8 Decoder. Software used: Cadence - Virtuoso Simulator: Virtuoso

Schematic:

Theory:
A decoder is a device which does the reverse operation of an encoder, undoing the encoding so that the original information can be retrieved. The same method used to encode is usually

just reversed in order to decode. It is a combinational circuit that converts binary information from n input lines to a maximum of 2n unique output lines. A decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2 n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

Truth Table:

Waveform:

Observation and result:

The waveform of Decoder has been observed and found to be same as typical one.