SN54/74LS112A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse.

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)

J SUFFIX CERAMIC CASE 620-09

16 1

Q 5(9) 6(7)

CLEAR (CD) 15(14) J 3(11) 1(13) CLOCK (CP)

SET (SD) 4(10) K 2(12)

16 1

N SUFFIX PLASTIC CASE 648-08

16 1

D SUFFIX SOIC CASE 751B-03

ORDERING INFORMATION MODE SELECT TRUTH TABLE

INPUTS OPERATING MODE SD Set Reset (Clear) *Undetermined Toggle Load 0 (Reset) Load 1 (Set) Hold L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l Q H L H q L H q Q L H H q H L q OUTPUTS SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC

LOGIC SYMBOL
4 3 1 2 J CP K CD Q 15 VCC = PIN 16 GND = PIN 8 SD Q 5 13 11 J CP 7 10 SD Q 9

* Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Dont Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) l, h (q) = one set-up time prior to the HIGH to LOW clock transition.

6 12 K C Q D 14

FAST AND LS TTL DATA 5-1

SN54/74LS112A
GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current High Output Current Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 0.4 4.0 8.0 Unit V C mA mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits S b l Symbol VIH VIL VIK VOH P Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage O Output HIGH Voltage V l 54 74 54, 74 VOL Output LOW Voltage 74 J, K Set, Clear Clock IIH Input HIGH Current J, K Set, Clear Clock J, K Clear, Set, Clk 20 0.35 0.5 20 60 80 0.1 0.3 0.4 0.4 0.8 100 6.0 V A 25 2.5 2.7 54 74 0.65 35 3.5 3.5 0.25 0.4 Min 2.0 0.7 0.8 1.5 V V V V Typ Max U i Unit V V T C di i Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VCC = MIN, IIN = 18 mA , IOH = MAX, MAX, VIN = VIH VCC = MIN MIN, or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table

VCC = MAX, VIN = 2.7 V

mA

VCC = MAX, VIN = 7.0 V

IIL IOS ICC

Input LOW Current

mA mA mA

VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX

Short Circuit Current (Note 1) Power Supply Current

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V)

Limits S b l Symbol fMAX tPLH tPHL P Parameter Maximum Clock Frequency Propagation Delay, p g y, Clock Clear, Set to Output Min 30 Typ 45 15 15 20 20 Max U i Unit MHz ns ns VCC = 5.0 50V CL = 15 pF T Test C Conditions di i

AC SETUP REQUIREMENTS (TA = 25C, VCC = 5.0 V)

Limits S b l Symbol tW tW ts th P Parameter Clock Pulse Width High Clear, Set Pulse Width Setup Time Hold Time Min 20 25 20 0 Typ Max U i Unit ns ns ns ns VCC = 5 5.0 0V T Test C Conditions di i

FAST AND LS TTL DATA 5-2