Design of Decimators and Interpolation filters using hdl.

The process of decreasing the sampling rate is called decimation. Decimation is down sampling with appropriate filtering. To decimate (down sample) a signal collecting every Mth value of to a new signal. This is given by by a factor of M implies .

Down sampling by an integer factor M implies retaining one sample and discarding the remaining M-1 samples and this is done for every M samples.

The process of increasing the sampling rate is called interpolation. Interpolation is up sampling followed by appropriate filtering. as: obtained by interpolating , is generally represented

The simplest method to interpolate by a factor of L is to add L-1 zeros in between the samples, multiply the amplitude by L and filter the generated signal, with a so-called anti-imaging low pass filter at the high sampling frequency.

In digital signal processing, decimation is a technique for reducing the number of samples in a discrete-time signal. The element which implements this technique is referred to as a decimator.

Decimation is a two-step process: Low-pass anti-aliasing filter

Down sampling An example of decimation: the frequency of a recorded sound can be raised an octave (in other words, doubled in frequency) by eliminating every other sample without changing the sampling rate. This will result in aliasing if the sound contains overtones whose (doubled) frequency will exceed half the sampling rate. Decimation aliasing can be avoided by eliminating those overtones with a low pass filter before down sampling.

The use of Verilog HDL has many advantage compared to the traditional schematic based design. Designs can be described at very abstract level using HDL. Designers can write their design description without choosing any specific fabrication technology. If a new technology emerges, designers do not need to redesign their circuit. They simply input the design program to the logic synthesis tool and create a new gate level netlist using the new fabrication technology. The logic synthesis tool will optimize the circuit in area and timing for the new technology.

By describing the design in HDL, functional verification of the design can be done early in the design cycle. Since designers work at the high level language, they can optimize and modify the design module until it meets the desired functionality. Most of the design bugs are eliminated at this point.