The following shows the contents of ctstch file.

Here for clocks clk1 clk2 , we are assuming the routing CLK_ROUTE. CLK_ROUTE is defined as top routing layer no. 5 bottom routing layer no. 3 And we can mention non default rules apply or not ( which means some times for clock route we use non default rules like.. extra spacing .. and extra metal width etc.

Root pins: its like origination of clock. From external clk pin there will b direct contact to root pins. And from root pins clk tree will start getting building. Our design may have one or more root pins. Period: tells abt the clk period Min delay: max delay: these are constraints on max. insertion delay and min insertion delay Max skew: constraint on how much max skew can be Buffer: here we tell what all the buffers which my tool must use during clock tree building. Nogating: we shud use gting or not this tells Route type: this tells to the tool that for that root pin use this routing type(routing type is mentioned on top of ctstch file Sinkmaxtrans: Bufmaxtrans: tells max transition time which can be found at the buffers or sink points

/* beginning of ctstch file

ClkGrp +clk1 +clk2 RouteTypeName CLK_ROUTE TopPreferredLayer 5 BottomPreferredLayer 3 NonDefaultRule WideWire PreferredExtraSpace 0 End #-----------------------------------------------------------# Clock Root : clk1 # Clock Name : clk1 # Clock Period : 2ns #-----------------------------------------------------------AutoCTSRootPin clk1 Period 2ns MaxDelay 2ns MinDelay 0ns MaxSkew 150ps SinkMaxTran 200ps BufMaxTran 200ps AddDriverCell CLKBUFX16 Buffer CLKINVX8 CLKINVX12 CLKINVX16 NoGating NO DetailReport YES SetDPinAsSync YES

SetIoPinAsSync YES RouteClkNet YES RouteType CLK_ROUTE END #-----------------------------------------------------------# Clock Root : clk2 # Clock Name : clk2 # Clock Period : 2ns #-----------------------------------------------------------AutoCTSRootPin clk2 Period 2ns MaxDelay 2ns MinDelay 0ns MaxSkew 150ps SinkMaxTran 200ps BufMaxTran 200ps AddDriverCell CLKBUFX16 Buffer CLKINVX8 CLKINVX12 CLKINVX16 NoGating NO DetailReport YES SetDPinAsSync YES SetIoPinAsSync YES RouteClkNet YES RouteType CLK_ROUTE END