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6.

002x

CIRCUITS AND ELECTRONICS

State and Memory


t

Review Recall vI + R + vC

RC

Reading: Section 10.3 and Chapter 11

This sequence will dwell on the memory property of capacitors

For the RC circuit in the previous slide vI


Notice that the capacitor voltage for t0 is independent of the form of the input voltage before t=0.

t vC

Instead, it depends only on the capacitor voltage at t=0, and the input voltage for t0.

State

State

ZIR and ZSR


We are often interested in circuit response for

One application of STATE

DIGITAL MEMORY

Memory Abstraction

Remembers input when store goes high. Like a camera that records input (dIN) when the user presses the shutter release button. The recorded value is visible at dOUT .

Building a memory element

Minimum store pulse width A

dIN store = 1

v * C dOUT C

dIN
store

dOUT
10

Storage time A

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Storage time A

dIN store = 0

v * C dOUT C RL

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Building a memory element second attempt B Second attempt buffer

dIN

C store

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Building a memory element buffer, refresh C Third attempt buffer + refresh

dIN store

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Building a memory element buffer,decoupled refresh D Fourth attempt buffer + decoupled refresh

dIN store

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A Memory Array 4-bit memory


dIN S M dIN S M
dOUT

dOUT

dIN S M
dOUT

dIN S M

dOUT

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Truth table for decoder

IN store Address
4-bit memory

OUT
A
dIN S M dIN S M

00

dOUT

Decoder

01

a0a1 2 Address

dOUT

1 10

dIN S M
dOUT

111

D
IN store

dIN S M

dOUT

OUT

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