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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS

Section 14
ShiIt Registers
Einite State Machines (ESM)
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers
ShiIt Registers are a
useIuI part oI digitaI
design in:
SeriaI to ParaIIeI
Conversion.
Pattern Detection
EIement Extraction
Etc.
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers SeriaI to ParaIIeI
The data input stream is
scaIar (1-bit) the data
output stream is an 8-bit
vector.
The data output cIock
wiII be 1/8
th
the speed oI
the input cIock.
moduIe sertopar (DOUT.DIN.INCLK.OUTCLK.RESET);
input DIN. INCLK. OUTCLK. RESET;
output |7:0] DOUT;
reg |7:0] DOUT. shItreg;
aIways (posedge INCLK or posedge RESET) begin
iI (RESET) shItreg 0;
eIse begin
shItreg|7] shItreg|6];
shItreg|6] shItreg|5];
shItreg|5] shItreg|4];
shItreg|4] shItreg|3];
shItreg|3] shItreg|2];
shItreg|2] shItreg|1];
shItreg|1] shItreg|0];
shItreg|0] DIN;
end
end
aIways (posedge OUTCLK or posedge RESET) begin
iI (RESET) DOUT 0;
eIse DOUT shItreg;
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers SeriaI to ParaIIeI
AIternate Eorm Ior ShiIt
Register.
Move bIocks when
shiIting rather than bits.
moduIe sertopar (DOUT.DIN.INCLK.OUTCLK.RESET);
input DIN. INCLK. OUTCLK. RESET;
output |7:0] DOUT;
reg |7:0] DOUT. shItreg;
aIways (posedge INCLK or posedge RESET) begin
iI (RESET) shItreg 0;
eIse begin
shItreg|7:1] shItreg|6:0];
shItreg|0] DIN;
end
end
aIways (posedge OUTCLK or posedge RESET) begin
iI (RESET) DOUT 0;
eIse DOUT shItreg;
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Register - SeriaI to ParaIIeI
Testbench
Why is OUTCLK
deIayed by 1ms?
`timescaIe 1ms/10us
moduIe tb;
reg DIN. INCLK. OUTCLK. RESET;
integer i;
wire |7:0] DOUT;
sertopar u1 (DOUT.DIN.INCLK.OUTCLK.RESET);
aIways #10 INCLK INCLK;
initiaI begin
#1;
Iorever #80 OUTCLK OUTCLK;
end
initiaI begin
DIN. INCLK. OUTCLK. RESET} 0;
#1 RESET 1;
#2 RESET 0;
Ior (i 0; i 2048; i i 1) begin
(negedge INCLK) DIN $random;
end
#100 $Iinish;
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers Pattern Detection
PATTERNMATCH wiII
go high whenever the
vaIue oI the shiIt register
matches the PATTERN
parameter.
Use conditionaI
constructs to Iind patterns
in Data.
moduIe pattern (PATTERNMATCH.DIN.CLK.RESET);
input DIN. CLK. RESET;
output PATTERNMATCH;
parameter PATTERN 8'b11001100;
reg |7:0] shItreg;
assign PATTERNMATCH (PATTERN shItreg) ? 1 : 0;
aIways (posedge CLK or posedge RESET) begin
iI (RESET) begin
shItreg 0;
end
eIse begin
shItreg|7:1] shItreg|6:0];
shItreg|0] DIN;
end
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers Pattern Detection
Testbench
`timescaIe 1ms/10us
moduIe tb;
reg DIN. CLK. RESET;
integer i;
pattern u1 (PATTERNMATCH.DIN.CLK.RESET);
aIways #10 CLK CLK;
initiaI begin
DIN. CLK. RESET} 0;
#1 RESET 1;
#2 RESET 0;
repeat (2) begin
Ior (i 0; i 64; i i 1) begin
(negedge CLK) DIN $random;
end
#100;
(negedge CLK) DIN 1;
(negedge CLK);
(negedge CLK) DIN 0;
(negedge CLK);
(negedge CLK) DIN 1;
(negedge CLK);
(negedge CLK) DIN 0;
(negedge CLK);
end
#100 $Iinish;
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers EIement Extraction
Data can be embedded in
synchronization code.
Eor ExampIe 8 bit data
embedded in 5 sync bits
oI Ieading data. and 4
sync bits oI traiIing data.
Data stream :
10110011110101001
moduIe eIementextract (DOUT.DIN.CLK.RESET);
input DIN. CLK. RESET;
output |7:0] DOUT;
reg |16:0] shItreg;
reg |7:0] DOUT;
parameter Ieadingsync 5'b10110;
parameter traiIingsync 4'b1001;
aIways (posedge CLK or posedge RESET) begin
iI (RESET) begin
DOUT 0;
shItreg 0;
end
eIse begin
shItreg|16:1] shItreg |15:0];
shItreg|0] DIN;
iI ((shItreg|16:12] Ieadingsync) & (shItreg|3:0] traiIingsync))
DOUT shItreg|11:4];
eIse
DOUT 'bz;
end
end
endmoduIe
Leading
Sync Data
Data
TraiIing
Sync Data
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
ShiIt Registers EIement Extraction
Testbench
`timescaIe 1ms/10us
moduIe tb;
reg CLK. RESET. DIN;
integer i;
wire |7:0] DOUT;
// Ieadingsync 5'b10110; traiIingsync 4'b1001;
eIementextract u1 (DOUT.DIN.CLK.RESET);
aIways #10 CLK CLK;
initiaI begin
RESET.CLK} 0;
#2 RESET 1;
#1 RESET 0;
repeat (40) (negedge CLK) DIN $random;
repeat (10) begin
(negedge CLK) DIN 1;
(negedge CLK) DIN 0;
(negedge CLK) DIN 1;
(negedge CLK);
(negedge CLK) DIN 0;
repeat (8) (negedge CLK) DIN $random;
(negedge CLK) DIN 1;
(negedge CLK) DIN 0;
(negedge CLK);
(negedge CLK) DIN 1;
end // repeat (10)
#100 $stop;
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machines
Einite State Machine
EIements:
A state register is deIined
States deIined as
Parameters.
Not necessary. but much
easier to read and program.
State changes handIed in
case statements.
State 0 State 1
N == 1
N == 0
moduIe expIicitIsm (OUT. CLK. IN. RESET);
input CLK. IN. RESET
output OUT;
reg STATE. OUT;
parameter state0 0;
parameter state1 1;
aIways (posedge CLK or posedge RESET)
iI (RESET)
STATE.OUT} 2`b00;
eIse
case (STATE)
state0: begin
OUT 0;
iI (IN) STATE 0;
eIse STATE 1;
end
state1: begin
OUT IN;
STATE 0;
end
deIauIt: STATE.OUT} 2`b00;
endcase
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machines ExampIe 1
State Diagram
dle
(0)
State 1
State 2
OUT2 = 0
if N1 == 1 or N2 == 1: OUT1 = 1
otherwise: OUT1 = 0
N
1
=
=
1

N
2

=
=

1
N1 != 1
OUT2 = 0
OUT1 = 0
N
2
!=
1
OUT2 = 1
OUT1 = 0
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machines ExampIe 1
RTL Code
module fsm (OUT1,OUT2,CLK,IN1,IN2,RESET);
input CLK, RESET, IN1, IN2;
output OUT1,OUT2;
reg OUT1, OUT2;
reg [1:0| current_state, next_state;
parameter idle = 0;
parameter state1 = 1;
parameter state2 = 2;
always @ (posedge CLK or posedge RESET)
if (RESET)
current_state <= idle;
else
current_state <= next_state;
always @ (current_state or IN1 or IN2)begin
case(current_state)
idle : begin
OUT2 = 0;
if (IN1 ]] IN2) OUT1 = 1;
else OUT1 = 0;
if(IN1 == 1) next_state = state1;
else next_state = idle;
end
state1 : begin
OUT2 = 1; OUT1 = 0;
if(IN2 == 1) next_state = state2;
else next_state = idle;
end
state2 : begin
OUT2 = 0; OUT1 = 0;
next_state = idle;
end
default : begin
OUT1 = 1'b1; OUT2 = 1'b1;
next_state = idle;
end
endcase
end
endmodule
Some designers wiII expIicitIy encode their state variabIes to avoid gIitches (i.e. Gray code or One-Hot). Others
wiII add synthesis constraints to Iorce encoding. such as:
#Synopsys Design CompiIer ESM Encoding Constraint
setIsmencodingstyIe onehot
At synthesis. this wouId change the state encoding to:
idIe 3`b001;
state1 3`b010;
state2 3`b100;
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machine ExampIe 2
TraIIic Light ControIIer
SimpIe intersection Iight
with East-West and
North-South controI.
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machine ExampIe 2
DeIauIt (NSGEWR) is
North-South Iight green.
East-West Iight red.
Light wiII change Irom
green to yeIIow aIter 30
seconds.
Light wiII remain yeIIow
Ior 5 seconds.
Both Iights wiII be red
Ior two seconds.
ExternaI timers wiII be
controIIed by the State
Machine.
RESET
EWYNSR
EWGNSR
NSREWR
NSYEWR
NSGEWR
EWRNSR
TMER30 = 1
TMER5 = 1
TMER2 = 1
TMER30 = 1
NSGREEN = 1
NSYELLOW = 0
NSRED = 0
EWGREEN = 0
EWYELLOW = 0
EWRED = 1
TMER30START = 1
TMER5START =0
TMER2START = 0
NSGREEN = 0
NSYELLOW = 1
NSRED = 0
EWGREEN = 0
EWYELLOW = 0
EWRED = 1
TMER30START = 0
TMER5START = 1
TMER2START = 0
NSGREEN = 0
NSYELLOW = 0
NSRED = 1
EWGREEN = 0
EWYELLOW = 0
EWRED = 1
TMER30START = 0
TMER5START = 0
TMER2START = 1
NSGREEN = 0
NSYELLOW = 0
NSRED = 1
EWGREEN = 1
EWYELLOW = 0
EWRED = 0
TMER30START = 1
TMER5START = 0
TMER2START = 0
NSGREEN = 0
NSYELLOW = 0
NSRED = 1
EWGREEN = 0
EWYELLOW = 1
EWRED = 0
TMER30START = 0
TMER5START = 1
TMER2START = 0
TMER5 = 1
NSGREEN = 0
NSYELLOW = 0
NSRED = 1
EWGREEN = 0
EWYELLOW =
EWRED = 1
TMER30START = 0
TMER5START = 0
TMER2START = 1
TMER2 = 1
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machine ExampIe 2
moduIe traIIicIight (NSGREEN. NSYELLOW. NSRED. EWGREEN.
EWYELLOW. EWRED. TIMER30START.
TIMER5START. TIMER2START. CLK. RESET.
TIMER30. TIMER5. TIMER2);
input CLK. RESET. TIMER30. TIMER5. TIMER2;
output NSGREEN. NSYELLOW. NSRED. EWGREEN. EWYELLOW.
EWRED. TIMER30START. TIMER5START. TIMER2START;
reg NSGREEN. NSYELLOW. NSRED. EWGREEN. EWYELLOW.
EWRED. TIMER30START. TIMER5START. TIMER2START;
reg |2:0] STATE. NEXTSTATE;
parameter NSGEWR 0;
parameter NSYEWR 1;
parameter NSREWR 2;
parameter EWGNSR 3;
parameter EWYNSR 4;
parameter EWRNSR 5;
aIways (posedge CLK or posedge RESET) begin
iI (RESET) STATE state0;
eIse STATE NEXTSTATE;
end
aIways (TIMER30. TIMER5. TIMER2. STATE) begin
case (STATE)
NSGEWR : begin
NSGREEN 1;
NSYELLOW 0;
NSRED 0;
EWGREEN 0;
EWYELLOW 0;
EWRED 1;
TIMER30START 1;
TIMER5START 0;
TIMER2START 0;
iI (TIMER30 1) NEXTSTATE NSYEWR;
eIse NEXTSTATE STATE;
end
NSYEWR : begin
NSGREEN 0;
NSYELLOW 1;
NSRED 0;
EWGREEN 0;
EWYELLOW 0;
EWRED 1;
TIMER30START 0;
TIMER5START 1;
TIMER2START 0;
iI (TIMER5 1) NEXTSTATE NSREWR;
eIse NEXTSTATE STATE;
end
NSREWR : begin .
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machine ExampIe 2
NSREWR : begin
NSGREEN 0;
NSYELLOW 0;
NSRED 1;
EWGREEN 0;
EWYELLOW 0;
EWRED 1;
TIMER30START 0;
TIMER5START 0;
TIMER2START 1;
iI (TIMER2 1) NEXTSTATE EWGNSR;
eIse NEXTSTATE STATE; end
EWGNSR : begin
NSGREEN 0;
NSYELLOW 0;
NSRED 1;
EWGREEN 1;
EWYELLOW 0;
EWRED 0;
TIMER30START 1;
TIMER5START 0;
TIMER2START 0;
iI (TIMER30 1) NEXTSTATE EWYNSR;
eIse NEXTSTATE STATE; end
EWYNSR : begin
NSGREEN 0;
NSYELLOW 0;
NSRED 1;
EWGREEN 0;
EWYELLOW 1;
EWRED 0;
TIMER30START 0;
TIMER5START 1;
TIMER2START 0;
iI (TIMER5 1) NEXTSTATE EWRNSR;
eIse NEXTSTATE STATE; end
EWRNSR : begin
NSGREEN 0;
NSYELLOW 0;
NSRED 1;
EWGREEN 0;
NWYELLOW 0;
EWRED 1;
TIMER30START 0;
TIMER5START 0;
TIMER2START 1;
iI (TIMER2 1) NEXTSTATE NSGEWR;
eIse NEXTSTATE STATE; end
deIauIt : begin
NSGREEN 1;
NSYELLOW 0;
NSRED 0;
EWGREEN 0;
EWYELLOW 0;
EWRED 1;
TIMER30START 1;
TIMER5START 0;
TIMER2START 0;
NEXTSTATE NSGEWR;
end
endcase
end
endmoduIe
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Einite State Machine ExampIe 2
Synthesis tooI shouId
recognize the state
machine.
=======================================
* HDL Synthesis *
=======================================
Synthesizing Unit <trafficlight>.
Related source file is trafficlight.v.
Found finite state machine <FSM_0>
for signal <STATE>.
--------------------------------------
| States | 6
|
| Transitions | 12
|
| Inputs | 3
|
| Outputs | 9
|
| Reset type | asynchronous
|
| Encoding | automatic
|
| State register | d flip-flops
|
--------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <trafficlight> synthesized.
======================================
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VeriIog HDL (EE 499/599 CS 499/599) 2004 AMIS
Review
What uses to ShiIt Registers have?
How do you shiIt data through a ShiIt Register?
Are ESMs synthesizabIe?
What is the recommended was to decIare your
state variabIes?