CLOCKLESS

CHIPS
Submitted by
Abi Mathew
Roll No:1
CONTENTS
1. INTRODUCTION
2. BASIC CONCEPT OF CLOCK
3. WORKING OF SYNCHRONIZE CHIPS
4. ADVANTAGES & DISADVANTAGES
5. WORKING OF ASYNCHRONOUS CHIPS
6. ADVANTAGES AND DISADVANTAGES
7. TYPES OF ASYNCHRONOUS DESIGN
8. COMPARISON
9. APPLICATIONS OF CLOCKLESS CHIPS
10. BRIEF HISTORY
11. CONCLUSION
INTODUCTION
 CLOCKLESS CHIPS OR ASYNCHRONOUS CHIPS DON’T HAVE
A GLOBAL CLOCK.
 BUT THERE SHOULD BE SOME CONTROL MECHANISM
INSTEAD OF GLOBAL CLOCK.
 CLOCKED CHIPS OR SYNCHRONOUS CHIPS HAVE A GLOBAL
CLOCK FOR CONTROLLING TIMING OF ENTIRE CHIP.
 CLOCKLESS CHIPS HAVE SOME ADVANTAGES LIKE LOW
POWER CONSUMPTION,HIGH SPEED & LESS
ELECTROMAGNETIC NOISE OVER CLOCKED CHIP.
CONCEPT OF CLOCK
Clock is a tiny crystal oscillator.
Clock regulates the rate at which the
instructions are executed. This rate is known
as clock rate or clock speed. The clock speed
can be expressed in terms of gigahertz and
megahertz.
One advantage of clock is that
the clock signals to various components
inside a chip when to input and output can
be determined very easy.
Because of this clock there
are some disadvantages like high power
consumption, low speed which can be
overcome by clockless chips.
BLOCK DIAGRAM OF SYNCHRONOUS
CIRCUIT
SYNCHRONOUS CHIPS
ADVANTAGE
 CHIP DESIGN VERY SIMPLE BECAUSE OF
CLOCK
DISADVANTAGES
 WASTAGE OF COMPUTATIONAL TIME
AFFECTS THE SPEED OF CHIP
 HIGHER POWER CONSUMPTION

 DESIGN OF COMPLEX CIRCUITS CANNOT BE

DONE BECAUSE OF HIGH POWER
CONSUMPTION
BLOCK DIAGRAM OF
ASYNCHRONOUS CHIPS
 MERITS OF
ASYNCHRONOUS
CIRCUITS
 Increase in speed.
 Reduced power consumption.
 Less electromagnetic noise.
 The ability to provide superior encryption.
 It is very flexible.
 Replacing any part with a faster version improves
the speed again and again
 Designers have more freedom in choosing the
system’s part.
LIMITATIONS OF
ASYNCHRONOUS CIRCUITS
 Design difficulties.
 Lack of good tools.
 Testing difficulties.
 TYPES OF
IMPLEMENTATIONS
 BOUNDED DELAY METHOD
 DELAY INSENSITIVE METHOD
 NULL CONVENTIONAL LOGIC(NCL)
SPEED COMPARISON
POWER COMPARISON
A BRIEF HISTORY
 COMPANY ACHIEVEMENTS GOALS
SUN Prototypes have Gradually integrate
MICROSYSTEMS demonstrated two “islands” of
Palo Alto, CA to three times the clockless logic into
speed of future
Standard chips. Generations of
microprocessors.
INTEL Clockless prototype Stay current with
Santa Clara, CA in 1997 ran three clockless R&D.
times faster than
the conventional
chip equivalent, on
half the power.
ASYNCHRONOUS Founded by Produce chips for
DIGITAL DESIGN students of cell phones and
Pasadena, CA Caltech’s Alain other low-power
Martin, who communications
developed the First devices; expected
asynchronous to announce plans
microprocessor. by
Year-end.
THESEUS LOGIC Patented “null License designs to
Maitland, FL convention logic,” manufacturers of
a way of letting smart cards and
clockless chips mobile devices;
know when an Motorola is a
operation is current customer.
Complete.
PHILIPS Markets a Clockless chips
ELECTRONICS clockless chip that for mobile devices
Eindhoven, gives its pagers and smart cards.
Netherlands up to twice the
battery life of
competitors.
SELF-TIMED Founded Steve Clockless chips
SOLUTIONS Furber who has for smart cards.
Manchester, developed
England clockless chips for
communications
devices.
The Caltech Asynchronous
Microprocessor is the world’s first
asynchronous microprocessor
(1989).
APPLICATIONS
 MOBILEELECTRONICS
 PERSONAL COMPUTERS

 ENCRYPTION DEVICES
CONCLUSION
Clocks are getting faster, while chips are getting bigger, both
of which make clock distribution harder. Chips are also
becoming more heterogeneous, with functions like memory
and network interfaces being considered, all of which
complicates the global timing analysis necessary for a
synchronous design. Finally, we are entering an age when
processors will be just about everywhere, and this will
require very low power designs. It’s just not practical to
expect a clean, skew-free clock for every (say) piece of
clothing with a processing element.
But this can only happen if more focus, especially at the
university level, is given to asynchronous design. Most of
today’s designers don’t understand it well enough to use it,
and may even regard it with suspicion. It is certainly a
challenge, but just as the software community is moving
towards more concurrency, the hardware community must
move to incorporate asynchronous logic.
THANK YOU!!!