BI TP LN S 2

MN: VHDL
H v tn: Mai Tr Th
MSSV:

11265541

Cu 1:
Hy thit k FSM dng T_FF c grap trng thi nh hnh sau:

Gii
Cch 1: Vit m t cu trc
-------------------------T_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY t_ff IS
PORT(
T,CLK,CLR,PR: IN STD_LOGIC;
Q: BUFFER STD_LOGIC;
END t_ff;
ARCHITECHTURE t_ff OF t_ff IS
SIGNAL Q_int: STD_LOGIC;

BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF (CLR=1) THEN
Q<=0;
ELSIF (PR=1) THEN
Q<=1;
ELSIF RISING_EDGE(CLK) THEN
CASE T IS
WHEN 1=>Q<=NOT Q;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS;
END t_ff;
-------------------------------BAI1---------------------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY bai1 IS
PORT(
C,CLK,RESET : IN STD_LOGIC;
A,B : OUT STD_LOGIC);
END bai1;
ARCHITECTURE structure OF bai1 IS

COMPONENT t_ff
PORT(
T,CLK,CLR,PR : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL T0,T1,Q0,Q1,PR: STD_LOGIC;
BEGIN
U1: t_ff PORT MAP(T0,CLK,RESET,PR,Q0);
U2: t_ff PORT MAP(T1,CLK,RESET,PR,Q1);
PR<=0;T0<=C OR NOT Q1 OR Q0;
T1<=( C OR Q1 OR Q0)AND(NOT C OR Q1 OR NOT Q0);
A<=NOT Q1 AND Q0;
B<=Q1 AND Q0;
END structure;
Cch 2: Vit theo mc hnh vi
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai1 IS
PORT (
C: IN STD_LOGIC;
CLK,RESET: IN STD_LOGIC;
A,B: OUT STD_LOGIC);
END bai1;
------------------------------------------------------ARCHITECTURE behavioral OF bai1 IS
TYPE states IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: -------------------------PROCESS (CLK,RESET)

BEGIN
IF (RESET='1') THEN
pr_state <= S0;
ELSIF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
A&B <= 00;
IF (C=0) THEN nx_state <= S1;
ELSE nx_state<=S3;
END IF;
WHEN S1 =>
A&B <= 10;
IF (C=0) THEN nx_state <= S2;
ELSE nx_state<=S0;
END IF;
WHEN S2 =>
A&B <= 00;
IF (C=0) THEN nx_state <= S0;
ELSE nx_state <=S1;
END IF;
WHEN S3 =>
A&B <= 01;
nx_state <= S0;
END CASE;
END PROCESS;
END behavioral;

Cu 2:
Hy thit k FSM dng D_FF c grap trng thi nh hnh sau:

Gii
Cch 1: Vit m t cu trc
-------------------------D_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY d_ff IS
PORT(
D,CLK,CLR,PR: IN STD_LOGIC;
Q: OUT STD_LOGIC;
END d_ff;
ARCHITECHTURE d_ff OF d_ff IS
BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF (CLR=1) THEN
Q<=0;
ELSIF (PR=1) THEN

Q<=1;
ELSIF RISING_EDGE(CLK) THEN
Q<=D;
END IF;
END PROCESS;
END d_ff;
-------------------------------BAI2---------------------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY bai2 IS
PORT(
A,B,CLK,RESET : IN STD_LOGIC;
XY : OUT STD_LOGIC);
END bai2;
ARCHITECTURE structure OF bai2 IS
COMPONENT d_ff
PORT(
D,CLK,CLR,PR : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL D0,D1,Q0,Q1,PR: STD_LOGIC;
BEGIN
U1: d_ff PORT MAP(D0,CLK,RESET,PR,Q0);
U2: d_ff PORT MAP(D1,CLK,RESET,PR,Q1);

PR<=0;D0<=NOT(A XOR Q0);

D1<=( B AND NOT Q1 AND Q0) OR (A AND Q1);
XY<=NOT Q0 OR Q1;
END structure;
Cch 2: Vit theo mc hnh vi
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai2 IS
PORT (
A,B: IN STD_LOGIC;
CLK,RESET: IN STD_LOGIC;
XY: OUT STD_LOGIC);
END bai2;
------------------------------------------------------ARCHITECTURE behavioral OF bai2 IS
TYPE states IS (S0, S1, S2, S3);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: -------------------------PROCESS (CLK,RESET)
BEGIN
IF (RESET='1') THEN
pr_state <= S0;
ELSIF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
XY <= 1;
IF (A=1) THEN nx_state <= S0;
ELSE nx_state<=S1;
END IF;
WHEN S1 =>
XY <= 0;

IF (A&B=00) THEN nx_state <= S0;

ELSIF (A&B=01) THEN nx_state <= S2;
ELSIF (A&B=10) THEN nx_state <= S1;
ELSE nx_state<=S3;
END IF;
WHEN S2 =>
XY <= 1;
IF (A=1) THEN nx_state <= S2;
ELSE nx_state <=S1;
END IF;
WHEN S3 =>
XY <= 1;
IF (A=1) THEN nx_state <= S3;
ELSE nx_state <=S0;
END IF;
END CASE;
END PROCESS;
END behavioral;

Cu 3:
Hy vit m t phn cng cho hnh sau:

Gii
Cch 1: Vit m t cu trc
-------------------------D_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY d_ff IS
PORT(
D,CLK,CLR: IN STD_LOGIC;
Q: OUT STD_LOGIC;
END d_ff;
ARCHITECHTURE d_ff OF d_ff IS
BEGIN
PROCESS(CLK,CLR)
BEGIN
IF (CLR=1) THEN
Q<=0;
ELSIF RISING_EDGE(CLK) THEN
Q<=D;
END IF;
END PROCESS;
END d_ff;

-------------------------------BAI3---------------------------------LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL
ENTITY bai3 IS
PORT(
S,CLK,RESET : IN STD_LOGIC;
N,M : OUT STD_LOGIC);
END bai3;
ARCHITECTURE structure OF bai3 IS
COMPONENT d_ff
PORT(
D,CLK,CLR: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL D0,D1,D2,Q0,Q1,Q2: STD_LOGIC;
BEGIN
U1: d_ff PORT MAP(D0,CLK,RESET,Q0);
U2: d_ff PORT MAP(D1,CLK,RESET,Q1);
U3: d_ff PORT MAP(D2,CLK,RESET,Q2);
D0<=(NOT Q0 AND Q1) OR (NOT S AND NOT Q1 AND NOT Q0)
OR (S AND Q2 AND Q0);
D1<=(NOT Q2 AND NOT Q0) OR (NOT Q2 AND NOT Q1 AND Q0)
OR(NOT S AND Q2 AND NOT Q1 AND NOT Q0);
D2<=NOT Q1 OR (Q0 AND NOT Q2);
N<=Q2 AND Q1 AND Q0;
M<=NOT Q2 AND Q1 AND NOT Q0;
END structure;

Cch 2: Vit theo mc hnh vi

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai3 IS
PORT (
S: IN STD_LOGIC;
CLK,RESET: IN STD_LOGIC;
N,M: OUT STD_LOGIC);
END bai3;
------------------------------------------------------ARCHITECTURE behavioral OF bai3 IS
TYPE states IS (S0, S1, S2, S3,S4,S5,S6,S7);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: -------------------------PROCESS (CLK,RESET)
BEGIN
IF (RESET='1') THEN
pr_state <= S0;
ELSIF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
N&M <= 00;
IF (S=1) THEN nx_state <= S6;
ELSE nx_state<=S7;
END IF;
WHEN S1 =>
N&M <= 00;
nx_state <= S6;
WHEN S2 =>
N&M <= 01;
nx_state <= S3;
WHEN S3 =>
N&M <= 00;
nx_state <= S4;

WHEN S4 =>
N&M <= 00;
IF (S=1) THEN nx_state <= S4;
ELSE nx_state<=S7;
END IF;
WHEN S5 =>
N&M <= 00;
IF (S=1) THEN nx_state <= S5;
ELSE nx_state<=S4;
END IF;
WHEN S6 =>
N&M <= 00;
nx_state <= S6;
WHEN S7 =>
N&M <= 10;
IF (S=1) THEN nx_state <= S1;
ELSE nx_state<=S0;
END IF;
END CASE;
END PROCESS;
END behavioral;

Cu 4:
Thit k FSM m t hot ng ca n giao thng 1 tr :

stop
RESET

FSM

ck

Yu cu:
Thi gian sng ca cc n nh sau:
n xanh : 12s

n vng: 3s

n : 15s

Dng T Flip Flop (chn Cl, Pr tch cc mc cao)

Chn Reset ni vi nt nhn,khi nhn nt Reset th chu trnh bt u li

t u vi n xanh sng

Chn stop ni vi cng tc,khi gt cng tc stop th n sng

Gii
Cch 1: Vit m t cu trc
-------------------------T_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY t_ff IS
PORT(
T,CLK,CLR,PR: IN STD_LOGIC;
Q: BUFFER STD_LOGIC;
END t_ff;
ARCHITECHTURE t_ff OF t_ff IS
SIGNAL Q_int: STD_LOGIC;
BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF (CLR=1) THEN
Q<=0;
ELSIF (PR=1) THEN
Q<=1;
ELSIF RISING_EDGE(CLK) THEN

CASE T IS
WHEN 1=>Q<=NOT Q;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS;
END t_ff;
-------------------------------BAI4---------------------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY bai4 IS
PORT(
CLK,R,STOP : IN STD_LOGIC;
X,V,D : OUT STD_LOGIC);
END bai4;
ARCHITECTURE structure OF bai4 IS
COMPONENT t_ff
PORT(
T,CLK,CLR,PR : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL T0,T1,T2,T3,Q0,Q1,Q2,Q3,CLR,PR: STD_LOGIC;
BEGIN
U1: t_ff PORT MAP(T0,CLK,CLR,STOP,Q0);

U2: t_ff PORT MAP(T1,CLK,STOP,PR,Q1);

U3: t_ff PORT MAP(T2,CLK,STOP,PR,Q2);
U4: t_ff PORT MAP(T3,CLK,CLR,STOP,Q3);
PR<=0;CLR<=0;
T0<=(R OR Q3 OR Q0) AND (R OR Q2 OR Q0);
T1<=( NOT R AND NOT Q3 AND Q1) OR(R AND NOT Q3 AND Q0);
T2<=( NOT R AND NOT Q3 AND Q2) OR(R AND NOT Q3 AND Q0
AND Q1);
T3<=( NOT R AND Q3 AND NOT Q2 AND NOT Q1) OR (R AND
NOT Q3 AND Q2 AND Q1 AND Q0) OR (Q3 AND NOT Q2 AND NOT Q1
AND Q0);
X<=NOT Q3 AND NOT Q2;
V<=NOT Q3 AND Q2 AND NOT Q1 AND Q0;
D<=(NOT Q3 AND Q2 AND Q0) OR (NOT Q3 AND Q2 AND Q1) OR
(Q3 AND NOT Q2 AND NOT Q1);
END structure;
Cch 2: Vit theo mc hnh vi
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai4 IS
PORT (
R,S: IN STD_LOGIC;
CLK: IN STD_LOGIC;
XVD: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END bai4;
------------------------------------------------------ARCHITECTURE behavioral OF bai4 IS
TYPE states IS (S0, S1, S2, S3,S4,S5,S6,S7,S8,S9);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: --------------------------

PROCESS (CLK,R,S)
BEGIN
IF (S=1) THEN
--Stop tch cc mc cao
pr_state<=S9;
ELSIF (R='0') THEN
--Reset tch cc mc thp
pr_state <= S0;
ELSIF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
XVD <= 100;
nx_state <= S1;
WHEN S1 =>
XVD <= 100;
nx_state <= S2;
WHEN S2 =>
XVD <= 100;
nx_state <= S3;
WHEN S3 =>
XVD <= 100;
nx_state <= S4;
WHEN S4 =>
XVD <= 010;
nx_state <= S5;
WHEN S5 =>
XVD <= 001;
nx_state <= S6;
WHEN S6 =>
XVD <= 001;
nx_state <= S7;
WHEN S7 =>
XVD <= 001;
nx_state <= S8;
WHEN S8 =>
XVD <= 001;
nx_state <= S9;
WHEN S9 =>
XVD <= 001;

nx_state <= S0;

END CASE;
END PROCESS;
END behavioral;

Cu 5:
Thit k FSM m t hot ng ca b m ln/xung ca s BCD 1 digit,
hin th trn Led 7 on loi anode chung

74LS4
7

FSM

ck
RESET
Yu cu:
-

Dng T Flip Flop (Cl tch cc cao, Pr tch cc thp)

khi nhn nt Reset th led hin th s 0

khi S= 0 th b m m xung, khi S= 1 th b m m ln.

Thi gian sng ca cc s l 1 s

Gii
Cch 1: Vit m t cu trc
-------------------------T_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY t_ff IS

PORT(
T,CLK,CLR,PR: IN STD_LOGIC;
Q: BUFFER STD_LOGIC;
END t_ff;
ARCHITECHTURE t_ff OF t_ff IS
SIGNAL Q_int: STD_LOGIC;
BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF (CLR=1) THEN

--CLR tch cc mc cao

Q<=0;
ELSIF (PR=0) THEN --PR tch cc mc thp
Q<=1;
ELSIF RISING_EDGE(CLK) THEN
CASE T IS
WHEN 1=>Q<=NOT Q;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS;
END t_ff;
-------------------------------BAI5---------------------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL

ENTITY bai5 IS
PORT(
CLK,S : IN STD_LOGIC;
D,C,B,A : OUT STD_LOGIC);
END bai5;
ARCHITECTURE structure OF bai5 IS
COMPONENT t_ff
PORT(
T,CLK,CLR,PR : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL T0,T1,T2,T3,Q0,Q1,Q2,Q3,CLR,PR: STD_LOGIC;
BEGIN
U1: t_ff PORT MAP(T0,CLK,CLR,PR,Q0);
U2: t_ff PORT MAP(T1,CLK,CLR,PR,Q1);
U3: t_ff PORT MAP(T2,CLK,CLR,PR,Q2);
U4: t_ff PORT MAP(T3,CLK,CLR,PR,Q3);
PR<=1;CLR<=0;
T0<=1;
T1<=( NOT S AND NOT Q3 AND Q2 AND NOT Q0) OR(NOT S AND
NOT Q3 AND Q1 AND Q1 AND NOT Q0) OR (NOT S AND Q3 AND NOT
Q2 AND NOT Q1 AND NOT Q0) OR (S AND NOT Q3 AND Q0);
T2<=( NOT S AND NOT Q3 AND Q2 AND NOT Q1 AND NOT Q0)
OR(NOT S AND Q3 AND NOT Q2 AND NOT Q1 AND NOT Q0) OR (S
AND NOT Q3 AND Q1 AND Q0);

T3<=( NOT S AND NOT Q2 AND NOT Q1 AND NOT Q0) OR (S

AND NOT Q3 AND Q2 AND Q1 AND Q0) OR (S AND Q3 AND NOT Q2
AND NOT Q1 AND Q0);
D<=Q3 AND NOT Q2 AND NOT Q1;
C<=NOT Q3 AND Q2;
B<=NOT Q3 AND Q1;
A<=(NOT Q3 AND Q0) OR (NOT Q2 AND NOT Q1 AND Q0);
END structure;
Cch 2: Vit theo mc hnh vi
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai5 IS
PORT (
CLK,S: IN STD_LOGIC;
DCBA: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END bai5;
------------------------------------------------------ARCHITECTURE behavioral OF bai5 IS
TYPE states IS (S0, S1, S2, S3,S4,S5,S6,S7,S8,S9);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: -------------------------PROCESS (CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
DCBA <= 0000;
IF (S =1) THEN nx_state <= S1;
ELSE nx_state<=S9;

END IF;
WHEN S1 =>
DCBA <= 0001;
IF (S =1) THEN nx_state <= S2;
ELSE nx_state<=S0;
END IF;
WHEN S2 =>
DCBA <= 0010;
IF (S =1) THEN nx_state <= S3;
ELSE nx_state<=S1;
END IF;
WHEN S3 =>
DCBA <= 0011;
IF (S =1) THEN nx_state <= S4;
ELSE nx_state<=S2;
END IF;
WHEN S4 =>
DCBA <= 0100;
IF (S =1) THEN nx_state <= S5;
ELSE nx_state<=S3;
END IF;
WHEN S5 =>
DCBA <= 0101;
IF (S =1) THEN nx_state <= S6;
ELSE nx_state<=S4;
END IF;
WHEN S6 =>
DCBA <= 0110;
IF (S =1) THEN nx_state <= S7;
ELSE nx_state<=S5;
END IF;
WHEN S7 =>
DCBA <= 0111;
IF (S =1) THEN nx_state <= S8;
ELSE nx_state<=S6;
END IF;
WHEN S8 =>
DCBA <= 1000;
IF (S =1) THEN nx_state <= S9;
ELSE nx_state<=S9;
END IF;
WHEN S9 =>
DCBA <= 1001;

IF (S =1) THEN nx_state <= S0;

ELSE nx_state<=S8;
END IF;
END CASE;
END PROCESS;
END behavioral;
Cu 6:
Thit k FSM m t hot ng ca b m ln ca s BCD 2 digit (0012), hin th trn Led 7 on loi anode chung

Yu cu:
-

Dng T Flip Flop (Cl tch cc cao, Pr tch cc thp)

khi nhn nt Reset th led hin th s 00

- Thi gian sng ca cc s l 0.5 s

Gii
Cch 1: Vit m t cu trc
-------------------------T_FF----------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY t_ff IS
PORT(
T,CLK,CLR,PR: IN STD_LOGIC;
Q: BUFFER STD_LOGIC;
END t_ff;
ARCHITECHTURE t_ff OF t_ff IS
SIGNAL Q_int: STD_LOGIC;

BEGIN
PROCESS(CLK,CLR,PR)
BEGIN
IF (CLR=1) THEN

--CLR tch cc mc cao

Q<=0;
ELSIF (PR=0) THEN --PR tch cc mc thp
Q<=1;
ELSIF RISING_EDGE(CLK) THEN
CASE T IS
WHEN 1=>Q<=NOT Q;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS;
END t_ff;
-------------------------------BAI6---------------------------------LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL
ENTITY bai6 IS
PORT(
CLK,RESET : IN STD_LOGIC;
E,D,C,B,A : OUT STD_LOGIC);
END bai6;
ARCHITECTURE structure OF bai6 IS

COMPONENT t_ff
PORT(
T,CLK,CLR,PR : IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT;
SIGNAL T0,T1,T2,T3,Q0,Q1,Q2,Q3,PR: STD_LOGIC;
BEGIN
U1: t_ff PORT MAP(T0,CLK,RESET,PR,Q0);
U2: t_ff PORT MAP(T1,CLK,RESET,PR,Q1);
U3: t_ff PORT MAP(T2,CLK,RESET,PR,Q2);
U4: t_ff PORT MAP(T3,CLK,RESET,PR,Q3);
PR<=1;
T0<=NOT Q3 OR NOT Q2;
T1<=(NOT Q3 AND Q0) OR (NOT Q2 AND Q0);
T2<=( NOT Q3 AND Q1 AND Q0) OR (NOT Q2 AND Q1 AND Q0)
OR (Q3 AND Q2 AND NOT Q1 AND NOT Q0);
T3<=( Q3 AND Q2 AND NOT Q1 AND NOT Q0) OR (NOT Q3 AND
Q2 AND Q1 AND Q0);
E<=Q3 AND NOT Q2 AND Q1 AND NOT Q0;
D<=Q3 AND NOT Q2 AND NOT Q1;
C<=NOT Q3 AND Q2;
B<=(NOT Q3 AND Q1) OR (Q3 AND Q2 AND NOT Q1 AND NOT
Q0);
A<=(NOT Q3 AND Q0) OR (NOT Q2 AND Q0);
END structure;

Cch 2: Vit theo mc hnh vi

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
------------------------------------------------------ENTITY bai6 IS
PORT (
CLK,RESET: IN STD_LOGIC;
EDCBA: OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END bai6;
------------------------------------------------------ARCHITECTURE behavioral OF bai6 IS
TYPE states IS (S0, S1, S2, S3,S4,S5,S6,S7,S8,S9,S10,S11,S12);
SIGNAL pr_state, nx_state: states;
BEGIN
---------- Lower section: -------------------------PROCESS (CLK)
BEGIN
IF (RESET=1) THEN
pr_state<=S0;
ELSIF RISING_EDGE(CLK) THEN
pr_state <= nx_state;
END IF;
END PROCESS;
---------- Upper section: -------------------------PROCESS (pr_state)
BEGIN
CASE pr_state IS
WHEN S0 =>
EDCBA <= 00000;
nx_state <= S1;
WHEN S1 =>
EDCBA <= 00001;
nx_state <= S2;
WHEN S2 =>
EDCBA <= 00010;
nx_state <= S3;
WHEN S3 =>
EDCBA <= 00011;
nx_state <= S4;
WHEN S4 =>
EDCBA <= 00100;
nx_state <= S5;

WHEN S5 =>
EDCBA <= 00101;
nx_state <= S6;
WHEN S6 =>
EDCBA <= 00110;
nx_state <= S7;
WHEN S7 =>
EDCBA <= 00111;
nx_state <= S8;
WHEN S8 =>
EDCBA <= 01000;
nx_state <= S9;
WHEN S9 =>
EDCBA <= 01001;
nx_state <= S10;
WHEN S10 =>
EDCBA <= 10000;
nx_state <= S11;
WHEN S11 =>
EDCBA <= 10001;
nx_state <= S12;
WHEN S12 =>
EDCBA <= 10010;
nx_state <= S0;
END CASE;
END PROCESS;
END behavioral;