Академический Документы
Профессиональный Документы
Культура Документы
CHARTS
By:
Dr K S Gurumurthy,
UVCE, Bangalore
In this chapter we first start with a brief introduction to state machines. Then we describe
the properties of SM charts and how these are used in the design of state machines. Then
two examples are discussed. One for a multiplier and the second for a dice game controller.
Then construction of VHDL descriptions of these systems directly from the respective SM
charts is dealt with. We then proceed with the design and show how PLA tables and logic
equations can be derived from SM charts. Showing how alternative designs can be obtained
by transforming the SM charts concludes the chapter.
A combinational circuit is a circuit whose outputs are determined totally by its external
inputs, on other hand a circuit is sequential if its output are determined not only by its
external inputs but also by the past history of the circuit.
System clock
Fig 1.1 Moore type machine
The external outputs in the synchronous state machine circuit model shown in fig 1.2 are
dependant on both the external inputs and the present state of the circuit. These are called
Mealy state machines.
System clock
Fig 1.2 Mealy type machine.
The circuit model illustrated in fig 1.3 is a synchronous state machine with both Moore and
Mealy type external outputs is called a mixed type machine.
System clock
2. If n arcs exit state Sk and the n arcs have input labels I1, I2,…………In, respectively,
then I1 + I2 +. …………+ In =1
The conditions for a proper state graph are automatically satisfied for an SM chart. A given
SM chart can be converted into several equivalent forms, and each form leads directly to a
hardware realization.
An SM chart is different from an ordinary flow chart. Certain specific rules must be
followed in constructing the SM chart. When these rules are followed, the SM chart is
equivalent to a state graph, and it directly leads to a hardware realization.
1.3.1 State Box: A state box represents the state of the system. The state box contains a
state name followed by a slash (/) and an optional output list. After a state assignment has
been made, a state code may be placed outside the box at the top.
1.3.2 Decision Box: This box will have two branches. The condition placed in the box
is a Boolean expression that is evaluated to determine which branch to select.
1.3.3 The conditional output box: It contains a conditional output list. The
conditional outputs depend on both the state of the system and the inputs.
1.4 Construction of SM charts: SM chart is constructed from SM blocks. Each SM
block contains exactly one state box, together with the decision boxes and conditional
output boxes associated with that state. An SM block has one entrance path and one or
more exit paths. Each SM block describes the machine operation during the time the
machine is in one state. When a digital system enters the state associated with a given SM
block, the outputs on the output list in the state box become true. The conditions in the
decision boxes are evaluated to determine which path is followed through SM block. When
a conditional output box is encountered along such a path, the corresponding outputs
become true. If an output is not encountered along a path, that output is false by default. A
path through an SM block from entrance to exit is referred to as a “link path”.
0 1
Link path a X1 Link path b
Z3,Z4
0
1 0 1
X2
X3
Z5
1
2 3 4
To next states………………………………………………………
Fig1.5
S1-State name,
Z1, Z2……….List of outputs,
X1, X2………Inputs.
When the machine enters the stat S1, outputs Z1 and Z2 become 1. If input X1=0, Z3 and
Z4 become 1. If X1 = X2 = 0, at the end of the state time the machine goes to the next via
exit path1. On the other hand, if X1 = 1 and X3 = 0, the output Z5 = 1, and exit to the next
state will occur via exit path 3. Since Z3 and Z4 are not encountered along this link path,
Z3 = Z4 =0 by default.
S1/Z1
S1/Z1
0 1
0 1 X2
X1
Z2 1 1 1
X1 X1
0 1 0 0
X2
Z2 Z2
S2/ S3/
S2/ S3/
00 b/ 00
a/0 0
10 10
R 0 Q’ 10
b/0
R’
c) ASM Chart Fig.1.7 S-R Latch
1.4 Derivation of SM charts: In this section, method used to design and construct an
SM chart for a given sequential control network is discussed. Two examples of SM charts
are taken up. They are i) Binary multiplier ii) An electronic dice game. Conversion of an
SM chart to a VHDL code process is discussed at the end of this section.
Product
Accumulator
C Load
O SH 8 7 6 5 4 3 2 1 0
N
T
R ADD
O
L Multiplier
Done DONE Cm 4-bit Adder
ST Clk
Multiplicand
1.7.1Design: In this section a multiplier for unsigned binary numbers is discussed and
designed. If the product aimed at is A*B, the first operand A is called multiplicand and the
second operand is called multiplier. Binary multiplication requires shifting and adding
operations.
Illustration: Let us take an example where in A = 12 (multiplicand) and B =11(multiplier)
1 1 0 0 *1 0 1 1
1 1 0 0 (multiply by M = 1)
1 1 0 0 - (multiply by M = 1 and shift)
100100 (add)
0000-- (multiply by M = 0 and shift)
1 0 0 1 0 0 (add)
1 1 0 0 - - - (multiply by M = 1 and shift)
8 7 6 5 4 3 2 1 0 M(11)
Initial contents of product 0 0 0 0 0 1 0 1 1
register
Add multiplicand(12)since M=1 1 1 0 0
After addition 0 1 1 0 0 1 0 1 1
After shift 0 0 1 1 0 0 1 0 1
Add multiplicand since M=1 1 1 0 0
After addition 1 0 0 1 0 0 1 0 1
After shift 0 1 0 0 1 0 0 1 0
Skip addition since M=0
After shift 0 0 1 0 0 1 0 0 1
Add multiplicand since M=1 1 1 0 0
After addition 1 0 0 0 0 1 0 0 1
After shift (final answer) 132 0 1 0 0 0 0 1 0 0
St Done
Load
Add or shift Ad
M control Sh
K
Counter
Fig 1.10 Multiplier control.
S0/
0 St 1
Load
S1/
0 1
M
Sh Ad
0
K S2/sh
1 1 K
0
S3/Done
This is a game based on a dice, which will have 6 faces with numbers 1,2,3,4,5,6. In this
game two dices will be thrown, and depending on the sum of the numbers seen on the faces
of the dices, the result is decided. One can come out with many conditions to decide
whether a player has won or not. The purpose of this example is to design a circuit that will
simulate the above said idea.
Fig.1.14 shows the block diagram for the dice game. Two counters are used to simulate the
ROLL of DICE. Each counter counts in the sequence 1,2,3,4,5,6,1,………Thus after the
ROLL of the DICE the SUM of the values in the two counters will be in the range 2
through 12.The rules of the game are as follows:
1. After the first ROLL of the DICE, the player wins if the SUM is 7 or 11.Th player
LOSES if the SUM is 2,3 or 12. Otherwise the SUM the player obtained on the first ROLL
is referred to as a POINT, and the player must ROLL the DICE again.
2. On the second or subsequent ROLL of the DICE, the player WINS if the SUM is 7.
Otherwise, the player must ROLL again until he or she finally WINS or LOSES or
RESETS (starts a new game).
The inputs to the DICE game come from push buttons RB (Roll Button) and RESET.
RESET is used to initiate a new game. When the ROLL button is pushed, the DICE
counters count at high speed. So the values cannot be read on the display. When the Roll
Button is released the values in the two counters are displayed and the game can proceed. If
the WIN light is not on, the player must push the Roll Button again.
entity Multi is
port (CLK, St, K, M: in bit;
Load, Sh.Ad, Done: out bit);
end Mult;
Display Display
RB
ROLL
1-6 counter 1-6 counter C RESET
O
N
Adder
D7 T
Sum
Test
D7, 11
R WIN
Logic
O
D2, 3,12 L
POINT Comparato Eq LOSE
Register r
Sp
Roll dice
Y N
S=7/
11
N Y
S=2,3,
12
Store sum in
point Reg
Roll Dice
Y N
S=
Point
Su
N
m
Win Y
Lose
Y N N Y
Res
Y Re
et set
Using the control signals defined above, SM chart is derived and the same is shown in Fig
1.15.The control network waits in state S0 until the roll button is pressed (RB = 1). Then it
goes to state S1, and the ROLL counters are enabled as long as RB = 1. As soon as the
ROLL button is released (RB = 0), D7, 11 is tested. If the sum is 7 or 11, the network goes
to states S2 and turns on the Win light; otherwise, D2, 3,12 is tested. If the sum is 2,3,or 12,
the network goes to state S3 and turns on the Lose light; otherwise, the signal Sp becomes
1 and the sum is stored in the Point register. It then enters S4 and waits for the player to
ROLL the dice again. In S3, after the ROLL button is released, if Eq = 1, the sum equals
the Point and state S2 is entered to indicate a Win. If D7 = 1, the Sum is 7 and S3 is entered
to indicate a Lose. Otherwise, control returns to S4 so that the player can roll again. When
in S2 or S3, the game is reset to S0 when the reset button is pressed.
Fig 1.15 SM chart for Dice game – Please refer to the annexure -1
A B St M K A+ B+ Load Sh Ad Done
So 0 0 0 - - 0 0 0 0 0 0
0 0 1 - - 0 1 1 0 0 0
0 1 - 0 0 0 1 0 1 0 0
S1
0 1 - 0 1 1 1 0 1 0 0
0 1 - 1 - 1 0 0 0 1 0
1 0 - - 0 0 1 0 1 0 0
S2
1 0 - - 1 1 1 0 1 0 0
S3 1 1 - - - 0 0 0 0 0 1
The PLA has 5 inputs and 6 outputs. Each row in the table corresponds to one of the link
paths in the SM chart. Since So has two exit paths the table has two rows for present state
So. The first row corresponds to the St = 0 exit path. So the next state and output are 0. In
the second row, St = 1, so the next state is a don’t care in the corresponding rows. The
outputs for each row can be filled in by tracing the corresponding link paths on the SM
chart. For example, the link path from S1 to S2 passes through conditional output Ad, so
Ad = 1 in this row. Since S2 has a Moore output Sh, Sh = 1 in both of the rows for which
AB = 10. By inspection of the PLA table, the logic equations for the multiplier control are:
St Load
Sp
P Ad
M Done
L
K D Q
A
D Q
Clock
Fig. 1.19 PLA realization of Multiplier control
Dr. K S Gurumurthy, UVCE, Blore Page 18 19/04/2005
1.10 Linked State Machines
When a sequential machine becomes large and complex, it is desirable to divide the
machine up into several smaller machines that are linked together. Each of the smaller
machines is easier to design and implement. Also, one of the submachines may be ‘called’
in several different places by the main machine. This is analogous to dividing a large
software program into procedures that are called by the main program.
Figure 1.20 shows the SM charts for two serially linked state machines. The machine
(Machine ‘A’) executes a sequence of some states until it is ready to call the submachine
(machine ‘B’). When state SA is reached, the output signal ZA activates machine B.
Machine B then leaves its idle state and executes a sequence of other states. When it is
finished, it outputs ZB before returning to the idle state. When machine A receives ZB, it
continues to execute other states. These two machines are assumed to have a common
clock.
SOME IDLE
STATES
0
ZA
1
SA/ZA OTHER
STATES
0 ZB
OTHER SB/ZB
STATES
iv) PLA size can be reduced by transforming the SM chart into a form in which only one
input is tested in each state.
v) However this generally increases the number of states and slows down the operation of
the system.
vi) For complex systems, we can split the control unit into several sections by using linked
state machines.
References:
1. Charles H ROTH, Jr.: Digital Systems Design Using VHDL; Thomson,
Books/Cole, 2004
2. Richard S. Sandige: Modern Digital Design; McGRAW- HILL International
Editions; 1990
3. J. Bhaskar: VHDL Primer; Pearson Education Asia; III Edition.