Design and Implement of QPSK Modem Based on FPGA

Wenmiao Song
Dept. of Electronic & Communication Engineering North China Electric Power University Baoding, China wenmiaosong@tom.com
AbstractThis paper presents a method to designs QPSK modulator and demodulator of a spread spectrum system which use field programmable device. The method uses the tool of Quartus of American Altera Co. The whole system is divided into several small models based on top-down design method, and using VHDL hardware description language to design each model. The direct digital synthesis (DDS) principle is briefly presented and used to design orthogonal cosine signal module. In demodulator, we use the low pass FIR filtering to filter high frequency component. The QPSK module is ultimately implemented on the FPGA device. The whole system has been simulated in the Quartus II7.2 simulation environment and successfully downloaded to the chip of the Cyclone II EP2C5F256C6. The operating results and the theoretical results are consistent, so its verified the correctness of this design. The results showed that the proposed method can greatly improve the developing efficiency, shorten developing period and reduce costs. Keywords-QPSK; DDS; Quartus; FIR

Qiongqiong Yao
Dept. of Electronic & Communication Engineering North China Electric Power University Baoding, China yqq606@qq.com Technology after Direct Frequency Synthesis and Indirect Frequency Synthesis, and breaks through the theory of the former two methods of Frequency Synthesis. Reference [1] pointed that the technique of DDS is gaining popularity as a method of generating sinusoidal signals and modulated signals in digital systems. II. A. MODEL AND METHOD

I.

INTRODUCTION

An SDR Software Defined Radio is a radio in which the properties of carrier frequency, signal bandwidth, modulation, and network access are defined by software. Todays SDR, in contrast, is a general-purpose device in which the same radio tuner and processors are used to implement many waveforms at many frequencies. Its idea is to get the software as close to the antenna as is feasible. Ultimately, we're turning hardware problems into software problems. The advantage of this approach is that the equipment is more versatile and cost-effective. This paper design and implement QPSK modulator and demodulator based on SDR ideology. QPSK modulation ordinarily use modem chips, or ASIC to implement, but those chips usually dont have sufficient Programming skills and its functionality can not easily be changed or improved in the product development process. Therefore, those chips are not suitable the situation where the parameters changed frequently. The communication system based on FPGA is easy to implement the pipeline architecture and simple to upgrade. This is a very practical approach to implement the QPSK modulator and demodulator. DDS is a new technology of Frequency Synthesis. It develops the third generation of Frequency Synthesis

The Model of DDS In the simplest case a Direct Digital Synthesis is constructed by a ROM with many samples of a sine wave stored in it (sine look-up table, LUT) and it was introduced in [2]-[3]. Figure.1 shows the block diagram of a DDS system. The DDS produces sinusoidal signals at a given frequency by digital integration of a higher clock frequency. The Phase Accumulator stage accepts the so called Frequency Setting Word (FSW) which determines the phase step. Once set, this digital word determines the sine wave frequency to be produced. The phase accumulator then continuously produces in the output proper binary words indicating the instantaneous phase to the table look-up function. In other words the phase accumulator is used to "calculate" the successive addresses of the sine look-up table which generates a digital sine-wave output. In this way the samples are swept in a controlled manner i.e. with a step depending on the Frequency Setting Word. The DDS translates the resulting phase to a sinusoidal waveform via the look-up table, and converts the digital representation of the sine-wave to analog form using a Digital-to-Analog Converter followed by a low pass filter (LPF).

Figure 1.

Block Diagram of a DDS System

The digital part of the DDS, i.e. the phase accumulator and the LUT, is usually called a Numerically Controlled

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Oscillator (NCO).The frequency of the output signal for a Mbit system is determined by the following equation:

fo =

Where K is the FSW, M is the number of bits that the phase accumulator can handle and fclk is the generator clock frequency in HZ. B. The model of QPSK A QPSK signal is generated by two BPSK signal and it was introduced in [4]. To distinguish the two signals, we use f c t ) , two orthogonal carrier signals. One is given by cos(2 and the other is given by sin(2 f c t ) . The two carrier signals remain orthogonal in the area of a period. By using cos(2 f c t ) and sin(2 f c t ) , we can represent QPSK signals by: 1 1 s (t ) = d I (t ) cos(2 f c t ) + d Q (t ) sin(2 f c t ) (2) 2 2 At the receiver, the received signal is down-converted to the baseband by multiplying it by the carrier frequency. Then in both I and Q channels, the down-converted signal is filtered by FIR filter. The signals are then adjudged, and the transmitted digital is recovered. QPSK basically uses the configuration shown in Figure.2 with several blocks, specialized for QPSK.

K f clk 2M

(1)

realized, if it is combined with SOPC Builder. This method has been introduced in [5]. This QPSK modem design is a basic design that uses a simplified channel model. It implements an encoder, a decoder, and uses modulation, filtering, and decision circuit. It does not implement any synchronization. We use models design the entire system, and then integrate them within the synthesis tool, like the Quartus II development environment. In the present, we design DDS and fir filter to implement QPSK modem and the resulting blocks were integrated in Quartus II system. A. The DDS model based on FPGA According to the basic principles of DDS, DDS model is built in the Quartus software by using FPGA development tools. The orthogonal signals generator application model based on DDS technology is built by Quartus II software. The configuration of DDS subsystem is shown in Figure.3, which is the DDS model based on FPGA. There are three inputs, such as a 32-bit frequency control words (Freq word), a 16-bit phase control words (Phase word) and a 10-bit amplitude control words (Amp), there are two outputs of 10bit Sin_put and Cos_put, there are two Parallel Adder Subtractors, phase accumulator and phase modulators, and a LUT for the sine ROM look-up table is also adopted in the DDS subsystem.

Figure 3. The DDS Subsystem Based on FPGA

Figure 2.

(a) Transmitter and (b) Receiver of the QPSK Transmission Scheme

B. The model design of QPSK modem Based on the principle of QPSK modulator-demodulator, the architecture is built with some basic modules in Quartus II and it can be seen in Figure.4

III.

SYSTEM DESIGN AND IMPLEMENT BASED ON FPGA

In our design, we use model-based design tools with the libraries of Quartus II 7.2. The Math Work industry-leading system-level was simulated with the Alter Quartus II 7.2 development software. Quartus II is a complete development platform. It includes input design, synthesis, simulation, timing analysis and download to verify that can meet the need of a variety of design. Quartus II design tool supports VHDL, Verilog design flow. Quartus II, MATLAB and DSP-Builder can be combined with FPGA-based DSP system development which is the hardware implementation to EDA tool. The SOPC system development can be

Figure 4. The Architecture of QPSK Modem

The QPSK modem implements QPSK modulation. Fristly, the model of zhuan implement a mapping circuit

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which makes the baseband signal to I and Q channels. Then both I and Q component was modulated by multiplying the carrier signals what are engendered from DDS model. The I_demodulator and Q_demodulator implement the demodulation of each channel, and its architecture can be seen in Figure 5.

sinusoid of 10KHz implemented using the DDS. From Figure 7 we can see that the demodulator result is in agreement with data_in pulse signal. So the architecture of QPSK modem can implement the function that we want.

Figure 6

The Outputs of DDS

Figure 5. The Architecture of QPSK Demodulator

The demodulator multiplies the received signal with the same carrier frequency as in the transmitter. The carrier frequency is generated by the model of DDS. The QPSK modem filters the I and Q components with a matching RRC filter, which is implemented with a FIR function using the model of 16_fir. In this paper, we design the 16_fir as a lowpass filter of order 16, the sampling frequency Fs is 1MHz and the cutoff frequency Fc is 15KHz. The filters input is 16-bit wide. We use the FDATool (Filter Design & Analysis Tool) in Matlab to ascertain parameters. The coefficients for each order exporting from Matable are 5979131803 3137 4692 6199 7387 8040 8040 7387 6199 4692 3137 1803 913 597 . Enter the coefficients to corresponding ROM in turn. We use the model of comp0 to implement the decision circuit. An integrator retrieves the transmitted symbols, which are then demapped by the model of chuan. The QPSK modem design does not implement synchronization, which is should added by yourselves in any real receive. C. Simulation results and analysis We adopt the Quartus II to carry out the algorithms in system level designing. The RTL level simulation is performed by the Quartus II sofeware where we can verify the modulation and demodulation process and the result was correct. Figure 6 shows the simulation result of DDS in Quartus II7.2 The DDS model has an 1MHZ clock and the frequency control words is 42949673, so we can get two orthogonal carrier signals whose frequency are 10KHz. Figure 7 shows the simulation result of QPSK modem in Quartus II7.2. The QPSK modem and FIR filter has an 1MHz clock, and the modulation is carried out with a

Figure 7

The Results of QPSK Modem

The FPGA implementation and test is achieved using Quartus II and the Cyclone II EP2C5F256C6 DSP development board. The method can greatly improve the developing efficiency, shorten developing period and reduce costs. The QPSK medom achieved by this method has been applied to a spread spectrum communication system project successfully. And this design based on FPGA will be widely used because it is simple and efficient. ACKNOWLEDGMENT The paper is supported by the foundation of PHD OF NCEPU.NO:200812004. REFERENCES
[1] M. L. Welborn, Direct Waveform Synthesis for Software Radios, IEEE Wireless Communications and Networking Conference WCNC. 1999, vol. 1, pp. 211-215, September 1999. C. S. Koukourlis, J. E .Plevridis, J. N. Sahalos, A New Digital Implementation of the RDS in the FM Stereo, IEEE Trans. Broadcast, vol. 42, pp. 323-327, December 1996. Wenmiao Song, Jingying Zhang, Qiongqiong Yao, Design And Implement Of BPSK Modulator And Demodulator Based On Moder DSP Technology, IEEE International Symposium. pp. 1135-1137, 2009. Hiroshi Harada, Ramjee Prasad, Simulation and Software Radio for Mobile Communications, Artech House Publishers Bk&CD-Rom edition. pp. 90-93,2002. http://www.altera.com/support/design-support-resources/spt-indexguide.html

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