A

Compal confidential

Schematics Document
Mobile Merom uFCPGA with Satna Rosa Platform
3

2007-01-08
REV:0.1

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Cover Sheet

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

E

of

40

Compal confidential
File Name : LA-3732P
ZZZ1

Spartan 1.0 (Merom +Crestline+ICH8)

PCB
1

Mobile Yonah/Merom
uFCPGA-478 CPU
Socket P

Fan Control
page 4

Thermal Sensor
ADM1032AR

page 4,5,6

Clock Generator
ICS9LPRS355

page 4

page 15

FSB
H_A#(3..31)

533/667/800MHz

H_D#(0..63)

CRT/TV-OUT
page 16

DDR2 -400/533/667

NB Crestline

LVDS Conn

DDR2-SO-DIMM X2
BANK 0, 1, 2, 3

page 13,14

Dual Channel
page 7,8,9,10,11,12

page 17
2

DMI
USB2.0

USB Conn

page 27

PCI BUS
PCI-E BUS

page 18,19,20,21

page 23

page 28

SB ICH8

MODEM AMOM
CX20548

Audio Conexant
CX20549-12

page 25

page 24

Realtac
RTL8100CL

LED

AC-LINK/Azalia

AMP & Audio Jack

TPA6017A2 page 26

SATA

SATA HDD Connector

page 22

RTC CKT.

RJ45/11 CONN

Mini-Card
WLAN

page 19

PATA Master

page 22

page 23

IDE ODD Connector

page 22

LPC BUS

ENE KB926

Power On/Off CKT.

Int.KBD

Touch Pad CONN.

DC/DC Interface CKT.

SPI ROM
25LF080A
page 29

page 30

page 28

SPI

page 28

page 30

page 31

2006/02/13

Issued Date

Page 32,33,34,35,36,37,38

Compal Secret Data

Security Classification

Power Circuit DC/DC

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
B

Title

Compal Electronics, Inc.

Block Diagram

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

E

of

40

Voltage Rails
+5VS
+3VS

power
plane
+B
D

+5VALW
+3VALW

+1.5VS
+1.8V

+1.25VS
+0.9V

State

+VCCP
+CPU_CORE

S0

S1

S3
S5 S4/AC

S5 S4/ Battery only

S5 S4/AC & Battery

don't exist

Symbol Note :
: means Digital Ground

: means Analog Ground

@ : means just reserve , no build
DEBUG@ : means just reserve for debug.

External PCI Devices

DEVICE

IDSEL #

L AN

AD22

REQ/GNT #
0

PIRQ
A

SMBUS Control Table

I2C / SMBUS ADDRESSING

SOURCE

DEVICE

HEX

ADDRESS

DDR SO-DIMM 0

A0

10100000

DDR SO-DIMM 1

A4

10100100

CLOCK GENERATOR (EXT.)

D2

11010010

INVERTER

BATT

THERMAL
SERIAL
SENSOR
EEPROM
(CPU)
ADM1032

SODIMM

CLK CHIP

MINI CARD

LCD

X
X

V
X

V
X

X
V

X
X

X
X

X
X

X
X

ICH8

Crestline

SMB_EC_CK1
SMB_EC_DA1

KB925

SMB_EC_CK2
SMB_EC_DA2

KB925

SMB_CK_CLK1
SMB_CK_DAT1
LCD_CLK
LCD_DAT

BOM: 43XXXXXX
Jump-Short:

PJP?
Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Notes List

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

of

40

XDP Connector

+3VS

layout note: Change R7 to 649 ohm if using XTP to ITP adapter

R1
XDP_DBRESET#_R

2 @ 1K_0402_5%

+VCCP

JP1
XDP_BPM#5
XDP_BPM#4
D

XDP_BPM#3
XDP_BPM#2
XDP_BPM#1
XDP_BPM#0

H_A#[3..16]

JP2A

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<7>
H_REQ#0
<7>
H_REQ#1
<7>
H_REQ#2
<7>
H_REQ#3
<7>
H_REQ#4
<7> H_A#[17..35]
C

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1

H_A20M#
H_FERR#
H_IGNNE#

A6
A5
C4

H_STPCLK#
H_INTR
H_NMI
H_SMI#

<19> H_STPCLK#
<19> H_INTR
<19>
H_NMI
<19>
H_SMI#

STPCLK#
LINT0
LINT1
SMI#

M4
N5
T2
V3
B2
C3
D2
D22
D3
F6

RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]

H_DEFER#
H_DRD Y#
H_DBSY#

F1

H_BR0#

IERR#
INIT#

D20
B3

H_IERR#
H_INIT#

LOCK#

H4

H_LOCK#

RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#

C1
F3
F4
G3
G2

H_RESET#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#

HIT#
HITM#

G6
E4

H_HIT#
H_HITM#

CONTROL

BR0#

A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#

D5
C6
B4
A3

H5
F21
E1

DEFER#
DRDY#
DBSY#

REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#

A20M#
FERR#
IGNNE#

H_ADS#
H_BNR#
H_BPRI#

BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#

AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20

XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
XDP_DBRESET#

H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
H_BR0#
H_INIT#

<7>

+VCCP

H_PROCHOT#

THERMAL
PROCHOT#
THERMDA
THERMDC
THERMTRIP#

D21
A24
B25

C1
C2

0.1U_0402_16V4Z
1
2

2
XDP_TCK

H_RESET# <7>
H_RS#0 <7>
H_RS#1 <7>
H_RS#2 <7>
H_TRDY# <7>

0.1U_0402_16V4Z

GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
@

H_THERMDA_R1 R14
H_THERMDC_R1 R15

BCLK[0]
BCLK[1]

CLK_CPU_BCLK
CLK_CPU_BCLK#

R2

54.9_0402_1%

R3

54.9_0402_1%

XDP_TDO

R4

54.9_0402_1%

XDP_BPM#5

R5

54.9_0402_1%

XDP_HOOK1

R6

2 @ 54.9_0402_1%

XDP_TRST#

R7

51_0402_1%

XDP_TCK

R8

54.9_0402_1%

CLK_CPU_XDP
CLK_CPU_XDP#

CLK_CPU_XDP <15>
CLK_CPU_XDP# <15>
1K_0402_1%
+VCCP
H_RESET#_R
1 R9
2 H_RESET#
XDP_DBRESET#_R 2
1 XDP_DBRESET#
200_0402_1%
XDP_TDO
R11
XDP_TRST#
XDP_TDI
XDP_TMS
XDP_PRE
1 R12
2 0_0402_5%

SAMTE_BSH-030-01-L-D-A

Place R9 within 200ps (~1") to CPU

C

Thermal Sensor ADM1032ARMZ

+3VS

C3
0.1U_0402_16V4Z
XDP_DBRESET# <20>
2
1
68_0402_5%

1
U1

H_PROCHOT# <37>
+VCCP

VDD

SCLK

SMB_EC_CK2

H_THERMDA

D+

SDATA

2 0_0402_5%
2 0_0402_5%

H_THERMDA
H_THERMDC

SMB_EC_DA2

H_THERMDC

D-

ALERT#

THERM#

GND

THERM#

2200P_0402_50V7K

H_THERMTRIP# <7,19>

R16
1

ADM1032ARMZ-2REEL_MSOP8

10K_0402_5%
A22
A21

XDP_TDI
XDP_TMS

H_HIT# <7>
H_HITM# <7>

+3VS

H CLK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60

GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17

C4

H_THERMTRIP#

C7

+VCCP

<19>

H_LOCK# <7>

H_PWRGOOD_R
XDP_HOOK1

<5> H_PWRGOOD_R

R10
56_0402_5%
2
1

R13

ICH

<19> H_A20M#
<19> H_FERR#
<19> H_IGNNE#

H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADSTB#1

H1
E2
G5

ADS#
BNR#
BPRI#

ADDR GROUP 1

<7> H_ADSTB#1

K3
H2
K2
J3
L1

A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#

XDP/ITP SIGNALS

<7> H_ADSTB#0

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

ADDR GROUP 0

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0

Address:100_1100

CLK_CPU_BCLK <15>
CLK_CPU_BCLK# <15>
SMB_EC_DA2
SMB_EC_CK2

<30> SMB_EC_DA2
<30> SMB_EC_CK2

H_THERMDA, H_THERMDC routing together,

Trace width / Spacing = 10 / 10 mil
RESERVED

<7>

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59

For Merom, R14 and R15 are 0ohm

For Penryn, R14 and R15 are 100ohm.

PWM Fan Control circuit

+5VS

SP02000D000 S W-CONN ACES 85204-02001 2P P1.25

ACES_85204-02001_2P

Merom Ball-out Rev 1a

CONN@

0306_Reserve.

R17

D1

0_0402_5%
2

RB751V_SOD323

C5
4.7U_0805_10V4Z

1
2
3
4

C6
0.1U_0402_16V4Z

@ R405
1

JP3

SP07000FP00 S SOCKET TYCO 2-1871873-2 478P H3 CPU

SP07000FD00 S SOCKET FOXCONN PZ4782A-274M-41 478P H3

+VCCP

1
2
G1
G2

ACES_85204-02001
CONN@

+3VS

FAN

FAN_PWM
THERM#

1
D Q1

U2

@ D26

INB

RLZ5.1B_LL34

INA

TC7SH00FU_SSOP5

SI3456BDV-T1-E3_TSOP6

<20>

OCP#

3
1 OCP#
@ Q2
MMBT3904_SOT23

<30>

H_PROCHOT#

1
2
5
6

2 2

@ 56_0402_5%

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Merom(1/3)-AGTL+/XDP

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

+VCC_CORE

C8

1
1

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6

B22
B23
C21

BSEL[0]
BSEL[1]
BSEL[2]

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

<15> CPU_BSEL0
<15> CPU_BSEL1
<15> CPU_BSEL2

COMP[0]
COMP[1]
COMP[2]
COMP[3]

R26
U26
AA1
Y1

COMP0
COMP1
COMP2
COMP3

DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#

E5
B5
D24
D6
D7
AE6

H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PW RGOOD
H_CPUSLP#
H_PSI#

MISC

Merom Ball-out Rev 1a

CONN@

CPU_BSEL2

CPU_BSEL1

CPU_BSEL0

166

200

H_DPRSTP# <7,19,37>
H_DPSLP# <19>
H_DPWR# <7>
H_PWRGOOD <19>
H_CPUSLP# <7>
H_PSI#
<37>

R26
2
1H_PWRGOOD_R
1K_0402_5%

layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL

H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>

H_PWRGOOD_R <4>

Resistor placed within

0.5" of CPU pin.Trace
should be at least 25
mils away from any other
toggling signal.
COMP[0,2] trace width is
18 mils. COMP[1,3] trace
width is 4 mils.

VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]

VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

VCCA[01]
VCCA[02]

B26
C26

VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]

AD6
AF5
AE5
AF4
AE3
AF3
AE2

VCCSENSE

AF7

VCCSENSE

VCCSENSE <37>

VSSSENSE

AE7

VSSSENSE

VSSSENSE <37>

Merom Ball-out Rev 1a

CONN@

+VCCP
R18
2
2
R19

0_0402_5%
1
1
0_0402_5%

1
C7

+
2

CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6

330U_4V_M

<37>
<37>
<37>
<37>
<37>
<37>
<37>

+1.5VS

0.01U_0402_16V7K

R20
R21

H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DINV#3

A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

C9

AD26
C23
D25
C24
AF26
AF1
A26

<7> H_DSTBN#1
<7> H_DSTBP#1
<7>
H_DINV#1

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_D#[48..63] <7>

R25
27.4_0402_1%
2
1

V_CPU_GTLREF
TEST1
2 @ 1K_0402_5%
TEST2
2 @ 1K_0402_5%
TEST3
T1
@ 0.1U_0402_16V4Z
TEST4
2
TEST5
T2
TEST6
T3

D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#

JP2C

R24
54.9_0402_1%
2
1

D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#

H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DINV#2

R23
27.4_0402_1%
2
1

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

DATA GRP 2

H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DINV#1

<7> H_DSTBN#0
<7> H_DSTBP#0
<7>
H_DINV#0
<7> H_D#[16..31]

DATA GRP 1

D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#

DATA GRP 0

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

+VCC_CORE

H_D#[32..47] <7>

JP2B
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DINV#0

R22
54.9_0402_1%
2
1

H_D#[0..15]

DATA GRP 3

<7>

10U_0805_6.3V6M
C10

Near pin B26

B

Length match within 25 mils.

The trace width/space/other is
20/7/25.

+VCCP

R27
1K_0402_1%
2

+VCC_CORE
R28
100_0402_1%
2

VCCSENSE

R30
100_0402_1%
1
2

VSSSENSE

V_CPU_GTLREF

R29
2K_0402_1%

Close to CPU pin AD26

within 500mils.

Close to CPU pin

within 500mils.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Merom(2/3)-AGTL+/PWR

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)
D

C11
10U_0805_6.3V6M

C12
10U_0805_6.3V6M

C13
10U_0805_6.3V6M

C14
10U_0805_6.3V6M

C15
10U_0805_6.3V6M

C16
10U_0805_6.3V6M

C17
10U_0805_6.3V6M

C18
10U_0805_6.3V6M
D

JP2D

A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]

VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

Merom Ball-out Rev 1a

CONN@
.

P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

+VCC_CORE

1
Place these capacitors on L8
(North side,Secondary Layer)

C19
10U_0805_6.3V6M

C20
10U_0805_6.3V6M

C21
10U_0805_6.3V6M

C22
10U_0805_6.3V6M

C23
10U_0805_6.3V6M

C24
10U_0805_6.3V6M

C25
10U_0805_6.3V6M

C26
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C27
10U_0805_6.3V6M

C28
10U_0805_6.3V6M

C29
10U_0805_6.3V6M

C30
10U_0805_6.3V6M

C31
10U_0805_6.3V6M

C32
10U_0805_6.3V6M

C33
10U_0805_6.3V6M

C34
10U_0805_6.3V6M

+VCC_CORE

1
Place these capacitors on L8
(Sorth side,Secondary Layer)

C35
10U_0805_6.3V6M

C36
10U_0805_6.3V6M

C37
10U_0805_6.3V6M

C38
10U_0805_6.3V6M

C39
10U_0805_6.3V6M

C40
10U_0805_6.3V6M

C41
10U_0805_6.3V6M

C42
C

10U_0805_6.3V6M

Mid Frequence Decoupling

ESR <= 1.5m ohm

Capacitor > 1980uF

Near CPU CORE regulator

+VCC_CORE
330U_D2E_2.5VM_R7

1000U 2.5V M H80 LESR8M

B

1
C45
330U_D2E_2.5VM_R7

C46

@ C47

1
C48

C49

330U_D2E_2.5VM_R7

330U_D2E_2.5VM_R7

0214_Change type from DIP to SMD.

0301_Remount C46.

0301_Delete C49.
Place these inside
socket cavity on L8
(North side
Secondary)

+VCCP

C50
0.1U_0402_16V4Z

C51
0.1U_0402_16V4Z

C52
0.1U_0402_16V4Z

C53
0.1U_0402_16V4Z

C54
0.1U_0402_16V4Z

C55
0.1U_0402_16V4Z

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Merom(3/3)-GND&Bypass

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

H_VREF

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4

M14
E13
A11
H13
B12

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_RS#_0
H_RS#_1
H_RS#_2

E12
D7
D8

H_RS#0
H_RS#1
H_RS#2

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

<5>
<5>
<5>
<5>

H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3

<5>
<5>
<5>
<5>

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

<4>
<4>
<4>
<4>
<4>

H_RS#0
H_RS#1
H_RS#2

<4>
<4>
<4>

SM_CS#_0
SM_CS#_1
SM_CS#_2
SM_CS#_3

BG20
BK16
BG16
BE13

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

SM_ODT_0
SM_ODT_1
SM_ODT_2
SM_ODT_3

BH18
BJ15
BJ14
BE16

M_ODT0
M_ODT1
M_ODT2
M_ODT3

SM_RCOMP
SM_RCOMP#

BL15
BK14

SMRCOMP
SMRCOMP#

SM_RCOMP_VOH
SM_RCOMP_VOL

BK31
BL31

SMRCOMP_VOH
SMRCOMP_VOL

SM_VREF_0
SM_VREF_1

AR49
AW4

10K_0402_5%
R37
PM_EXTTS#1

10K_0402_5%
CLKREQ#_B

R38
2 <>

T4
T5
T6
T7
T8
T9
T10
T11
T12

CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13

T13

CFG16

T44
T14
T15

CFG18
CFG19
CFG20

<20> PM_BMBUSY#
<5,19,37> H_DPRSTP#
<13> PM_EXTTS#0
<14> PM_EXTTS#1
<20,30> PM_PWROK
<18,22> PLT_RST#
<4,19> H_THERMTRIP#
<20,37> DPRSLPVR

P27
N27
N24
C21
C23
F23
N23
G23
J20
C20
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
L35

PM_BMBUSY#
G41
H_DPRSTP#
L39
PM_EXTTS#0
L36
PM_EXTTS#1
J36
PM_PWROK
AW49
PLT_RST#
AV20
H_THERMTRIP#
N20
DPRSLPVR
G36

BJ51
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
E1
A5
C51
B50
A50
A49
BK2

+1.8V

CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20

PM_BM_BUSY#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16

DDR

MUXING

K44
K45

CLK_MCH_3GPLL
CLK_MCH_3GPLL#

DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3

AN47
AJ38
AN42
AN46

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3

AM47
AJ39
AN41
AN45

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3

AJ46
AJ41
AM40
AM44

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3

AJ47
AJ42
AM39
AM43

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VR_EN

CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF

CLK_MCH_DREFCLK <15>
CLK_MCH_DREFCLK# <15>
MCH_SSCDREFCLK <15>
MCH_SSCDREFCLK# <15>
CLK_MCH_3GPLL <15>
CLK_MCH_3GPLL# <15>

DMI_TXN0
DMI_TXN1
DMI_TXN2
DMI_TXN3

<20>
<20>
<20>
<20>

DMI_TXP0
DMI_TXP1
DMI_TXP2
DMI_TXP3

<20>
<20>
<20>
<20>

DMI_RXN0
DMI_RXN1
DMI_RXN2
DMI_RXN3

<20>
<20>
<20>
<20>

DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_RXP3

<20>
<20>
<20>
<20>

CL_CLK0
CL_DATA0
M_PWROK
CL_RST#
CL_VREF

AM49
AK50
AT43
AN49
AM50

CL_CLK0 <20>
CL_DATA0 <20>
M_PWROK <20,30>
CL_RST# <20>
CL_VREF
0.1U_0402_16V4Z 1

SDVO_CTRL_CLK
SDVO_CTRL_DATA
CLK_REQ#
ICH_SYNC#

H35
K36
G39
G40

TEST_1
TEST_2

A37
R32

2
CLKREQ#_B
MCH_ICH_SYNC#

2006/03/10

CLKREQ#_B <15>
MCH_ICH_SYNC# <20>

R48

Compal Secret Data

Deciphered Date

R41
1K_0402_1%

R42
392_0402_1%

C60

2
2

+1.25VM_AXD

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Near B3 pin

+1.8V
20_0402_1%
1
1
20_0402_1%

T16
T17
T18
T19
T20

E35
A39
C38
B39
E36

R47

2006/02/13

<13>
<13>
<14>
<14>

@ R46
1K_0402_1%

Issued Date

<13>
<13>
<14>
<14>

V_DDR_MCH_REF

PEG_CLK
PEG_CLK#

CRESTLINE_1p0

Security Classification

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#

R35

20K_0402_5%
2

<13>
<13>
<14>
<14>

R34

CLK_MCH_DREFCLK
CLK_MCH_DREFCLK#
MCH_SSCDREFCLK
MCH_SSCDREFCLK#

10K_0402_5%

MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2

<13>
<13>
<14>
<14>

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

M_ODT0
M_ODT1
M_ODT2
M_ODT3

B42
C42
H48
H47

<15> MCH_CLKSEL0
<15> MCH_CLKSEL1
<15> MCH_CLKSEL2

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#

CLK

2
1
2

C59

C58

R36
PM_EXTTS#0

V_DDR_MCH_REF
C61
0.1U_0402_16V4Z

<13,14,35> V_DDR_MCH_REF

0.1U_0402_16V4Z
C63

1
R45

221_0603_1%

2
1
R51
2

100_0402_1%

C62

1
R44

1K_0402_1%

2
1
R49
2

2K_0402_1%

R50
24.9_0402_1%
2
1
5

1K_0402_1%

RSVD20
RSVD21
RSVD22
RSVD23
RSVD24
RSVD25
RSVD26
RSVD27
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD40
RSVD41
RSVD42
RSVD43
RSVD44
RSVD45

NC

within 100 mils from NB

R33

@ R43
1K_0402_1%

+VCCP

+3VS

<5>
<5>
<5>
<5>

+VCCP

DDR_CKE0_DIMMA
DDR_CKE1_DIMMA
DDR_CKE2_DIMMB
DDR_CKE3_DIMMB

DMI

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

Layout Note:
V_DDR_MCH_REF
trace width and
spacing is 20/20.

H_SWNG

BE29
AY32
BD39
BG37

1
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <15>
CLK_MCH_BCLK# <15>
H_DPWR# <5>
H_DRDY# <4>
H_HIT#
<4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>

Route H_SCOMP and H_SCOMP# with trace width, spacing and

impedance (55 ohm) same as FSB data traces

H_RCOMP

H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
BF23
BG23
BC23
BD24
BJ29
BE24
BH39
AW20
BK20
C48
D47
B44
C44
A35
B37
B36
B34
C34

<13> DDR_A_MA14
<14> DDR_B_MA14

CRESTLINE_1p0

0.1U_0402_16V4Z
H_VREF

0.01U_0402_16V7K

SMRCOMP_VOL

layout note:

SM_CKE_0
SM_CKE_1
SM_CKE_3
SM_CKE_4

R32
3.01K_0402_1%
NA lead free

H_AVREF
H_DVREF

Layout Note:
H_RCOMP / H_VREF / H_SWNG
trace width and spacing is 10/20

L7
K2
AC2
AJ10

H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3

C57

H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3

2.2U_0805_16V4Z
C56

M7
K3
AD2
AH11

M_CLK_DDR#0
M_CLK_DDR#1
M_CLK_DDR#2
M_CLK_DDR#3

PM

B9
A9

H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3

AW30
BA23
AW25
AW23

<13>
<13>
<14>
<14>

H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3

SM_CK#_0
SM_CK#_1
SM_CK#_3
SM_CK#_4

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

H_CPURST#
H_CPUSLP#

K5
L2
AD13
AE13

1K_0402_1%

M_CLK_DDR0
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR3

B6
E5

H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3

SMRCOMP_VOH

R31

AV29
BB23
BA25
AV23

H_RESET#
H_CPUSLP#

H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRD Y#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

+1.8V

SM_CK_0
SM_CK_1
SM_CK_3
SM_CK_4

H_SCOMP
H_SCOMP#

G12
H17
G20
C8
E8
F12
D6
C10
AM5
AM7
H8
K7
E4
C6
G10
B7

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14

Title

0_0402_5%
A

H_SWING
H_RCOMP

W1
W2

H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#

P36
P37
R35
N35
AR12
AR13
AM12
AN13
J12
AR37
AM36
AL36
AM37
D20

B3
C2

H_SCOMP
H_SCOMP#

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35

GRAPHICS VID

R40
54.9_0402_1%
2
1
H_RESET#
H_CPUSLP#

H_SWNG
H_RCOMP

J13
B11
C11
M11
C15
F16
L13
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
B15
E17
C18
A19
B19
N19

CFG

R39
54.9_0402_1%
2
1

+VCCP

H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35

ME

H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63

For Crestline: 20ohm

For Calero: 80.6ohm

RSVD

E2
G2
G7
M6
H7
H3
G4
F3
N8
H2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
AE5
AJ3
AH2
AH13

2.2U_0805_16V4Z

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

U3B

0.01U_0402_16V7K

U3A

H_D#[0..63]

<4>
<5>

H_A#[3..35] <4>

HOST

<5>

MISC

Compal Electronics, Inc.

CRESTLINE(1/6)-AGTL+/DMI/DDR2

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

<14> DDR_B_D[0..63]

DDR_A_BS0
DDR_A_BS1
DDR_A_BS2

SA_CAS#

BL17

DDR_A_CAS#

SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7

AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7

AT46
BE48
BB43
BC37
BB16
BH6
BB2
AP3
AT47
BD47
BC41
BA37
BA16
BH7
BC1
AP2

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13

BJ19
BD20
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BC19
BE28
BG30
BJ16

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13

SA_RAS#
SA_RCVEN#

BE18
AY20

DDR_A_RAS#
SA_RCVEN#

SA_WE#

BA19

DDR_A_WE#

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

DDR_A_BS0 <13>
DDR_A_BS1 <13>
DDR_A_BS2 <13>
DDR_A_CAS# <13>
DDR_A_DM[0..7] <13>

DDR_A_DQS[0..7] <13>

DDR_A_DQS#[0..7] <13>

DDR_A_MA[0..13] <13>

DDR_A_RAS# <13>
T22
DDR_A_WE# <13>

AP49
AR51
AW50
AW51
AN51
AN50
AV50
AV49
BA50
BB50
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AY2
AY3
AU2
AT2

CRESTLINE_1p0

SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63

SB_BS_0
SB_BS_1
SB_BS_2

BB19
BK19
BF29

MEMORY

SA_BS_0
SA_BS_1
SA_BS_2

MEMORY

SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63

SYSTEM

AR43
AW44
BA45
AY46
AR41
AR45
AT42
AW47
BB45
BF48
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT9
AN9
AM9
AN11

DDR

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

U3E

SYSTEM

U3D

DDR

<13> DDR_A_D[0..63]

AY17
BG18
BG36

DDR_B_BS0
DDR_B_BS1
DDR_B_BS2

SB_CAS#

BE17

DDR_B_CAS#

SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7

AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2

DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7

SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7

AT50
BD50
BK46
BK39
BJ12
BL7
BE2
AV2
AU50
BC50
BL45
BK38
BK12
BK7
BF2
AV3

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7
DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13

BC18
BG28
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
BG17
BE37
BA39
BG13

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13

SB_RAS#
SB_RCVEN#

AV16
AY18

DDR_B_RAS#
SB_RCVEN#

SB_WE#

BC17

DDR_B_WE#

DDR_B_BS0 <14>
DDR_B_BS1 <14>
DDR_B_BS2 <14>
DDR_B_CAS# <14>
DDR_B_DM[0..7] <14>

DDR_B_DQS[0..7] <14>

DDR_B_DQS#[0..7] <14>

DDR_B_MA[0..13] <14>

DDR_B_RAS# <14>
T21
DDR_B_WE# <14>

CRESTLINE_1p0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRESTLINE((2/6)-DDR2 A/B CH

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

Strap Pin Table

010 = FSB 800MHz
CFG[2:0] FSB Freq select

011 = FSB 667MHz

Others = Reserved

BKLT_CTRL
<17>

For Crestline:2.4kohm
For Calero: 1.5Kohm

ENABLT
R53 1
R54 1
LCD_CLK
LCD_DATA
ENAVDD

ENABLT
+3VS

<17> LCD_CLK
<17> LCD_DATA
<17>
ENAVDD
2
R55

LVDSACLVDSAC+
LVDSBCLVDSBC+

<17>
<17>
<17>

LVDSA0LVDSA1LVDSA2-

<17>
<17>
<17>

LVDSA0+
LVDSA1+
LVDSA2+

<17>
<17>
<17>

LVDSB0LVDSB1LVDSB2-

<17>
<17>
<17>

LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK

LVDSA0LVDSA1LVDSA2-

G51
E51
F49

LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2

LVDSA0+
LVDSA1+
LVDSA2+

G50
E50
F48

LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2

LVDSB0LVDSB1LVDSB2-

G44
B47
B45

LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2

LVDSB0+
LVDSB1+
LVDSB2+

E44
A47
A45

LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2

TV_COMPS
TV_LUMA
TV_CRMA

TV_COMPS
TV_LUMA
TV_CRMA

2.2K_0402_5%
1
2

CRT_B

<16>

CRT_G

<16>

CRT_R

CRT_B
CRT_G
CRT_R

3VDDCCL
3VDDCDA
CRT_HSYNC

<16> CRT_VSYNC

CRT_VSYNC

F27
J27
L27

TVA_RTN
TVB_RTN
TVC_RTN

M35
P33

TV_DCONSEL_0
TV_DCONSEL_1

H32
G32
K29
J29
F29
E29

CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_RED
CRT_RED#

K33
G35
F33
C32
E33

CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
CRT_VSYNC

<16>
3VDDCCL
<16> 3VDDCDA
<16> CRT_HSYNC

TVA_DAC
TVB_DAC
TVC_DAC

1.3K_0402_1%

R57

VGA

<16>

E27
G27
K27

PEG_COMPI
PEG_COMPO

TV

LVDSB0+
LVDSB1+
LVDSB2+

R56

+3VS

LVDSACLVDSAC+
LVDSBCLVDSBC+

L41
L43
N41
N40
D46
C45
D44
E42

1
2.4K_0402_1%

<17>
<17>
<17>
<17>

<16>
<16>
<16>

L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN

LVDS

J40
H39
E39
E40
C37
D35
K40

2 10K_0402_5%
2 10K_0402_5%

0 = DMI x 2

CFG5 (DMI select)

U3C

GRAPHICS

0312_Add test point.

PCI-EXPRESS

N43
M43

PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15

J51
L51
N47
T45
T50
U40
Y44
Y40
AB51
W49
AD44
AD40
AG46
AH49
AG45
AG41

PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

J50
L50
M47
U44
T49
T41
W45
W41
AB50
Y48
AC45
AC41
AH47
AG49
AH45
AG42

PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15

N45
U39
U47
N51
R50
T42
Y43
W46
W38
AD39
AC46
AC49
AC42
AH39
AE49
AH44

PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15

M45
T38
T46
N50
R51
U43
W42
Y47
Y39
AC38
AD47
AC50
AD43
AG39
AE50
AH43

PEGCOMP

R52
24.9_0402_1%
1
2

1 = DMI x 4

+VCCP

CFG6

PEGCOMP trace width

and spacing is 20/25 mils.

Reserved

CFG7 (CPU Strap)

0 = Reserved
1 = Mobile CPU

CFG8 (Low power PCIE)

0 = Normal mode
1 = Low Power mode

0 = Reverse Lane

CFG9
(PCIE Graphics Lane Reversal)
CFG[11:10]

1 = Normal Operation

Reserved
00
01
10
11

CFG[13:12] (XOR/ALLZ)

CFG[15:14]

= Reserved
= XOR Mode Enabled
= All Z Mode Enabled
= Normal Operation (Default)

*
C

Reserved

CFG16 (FSB Dynamic ODT)

0 = Disabled
1 = Enabled

CFG[18:17]

Reserved
0 = No SDVO Device Present

SDVO_CTRLDATA

1 = SDVO Device Present

CFG19 (DMI Lane Reversal)

0 = Normal Operation
(Lane number in Order)

1 = Reverse Lane
CFG20 (PCIE/SDVO concurrent)

0 = Only PCIE or SDVO is operational.

1 = PCIE/SDVO are operating simu.

CFG[17:3] have internal pull up

CFG[19:18] have internal pull down

CRESTLINE_1p0

For Crestline:1.3kohm
For Calero: 255ohm

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRESTLINE((3/6)-VGA/LVDS/TV

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

of

40

VCCSYNC

+3VS

330U_4V_M

2
1U_0603_10V4Z

+1.5VS_TVDAC

50mAM32
25mAL29
5mA

VCCD_CRT
VCCD_TVDAC

N28

+1.5VS_QDAC

VCCD_QDAC

250mA

+1.25VM_HPLL

AN2

AXD
AXF

VCC_RXR_DMI_1
VCC_RXR_DMI_2
VTTLF1
VTTLF2
VTTLF3

C72

AD51 1200mA +VCC_PEG

W50
W51
V49
V50

2
1
MBK2012121YZF_0805

+1.25VS

10U_FLC-453232-100K_0.25A_10%
C97
0.1U_0402_16V4Z

+VCCP

+1.25VM_MPLL
R73

2
1
0_0805_5%

+1.25VS

R72

A7
F2
AH1

10U_0805_10V4Z

+VCC_PEG

20mils

C98

0.1U_0402_16V4Z

AH50 250mA
AH51

CRESTLINE_1p0

1
+

C105

1450mA

VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5

2
1
MBK2012121YZF_0805

10U_0805_10V4Z

C112

+3VS_HV

100mA

+1.25VS

R70

R69

+1.8V_TXLVDS

0.47U_0603_10V7K
C110

+3VS
BLM18PG181SN1D_0603
2
1
R74

+1.25VM_HPLL
+1.25VS_DPLLA

0.1U_0402_16V4Z

C111
0.022U_0402_16V7K

VCCD_LVDS_1
VCCD_LVDS_2

0.47U_0603_10V7K
C109

+3VS_TVDACC

VCCD_PEG_PLL

J41
H42

100mA

0.47U_0603_10V7K
C108

150mA
+1.8V_LVDS

U48

+1.5VS
R67
1
2
0_0805_5%

+1.8V_SM_CK

C104
220U_6.3V_M

+1.25VS_PEGPLL

VCCD_HPLL

100mA

+1.5VS_TVDAC

10U_0805_10V4Z

75mA

0215_Change package from 0402 to 0603.

C40
B40

C96

40mA

+3VS_TVDACC

VCC_HV_1
VCC_HV_2

C95

40mA

+3VS_TVDACB

VCCA_TVA_DAC_1
VCCA_TVA_DAC_2
VCCA_TVB_DAC_1
VCCA_TVB_DAC_2
VCCA_TVC_DAC_1
VCCA_TVC_DAC_2

VCC_TX_LVDS

A43

120mA

C94
220U_6.3V_M

C25
B25
C27
B27
B28
A28

BK24
BK23
BJ24
BJ23

+1.25VS_DMI

C103

VCCA_SM_CK_1
VCCA_SM_CK_2

40mA
+3VS_TVDACA

VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4

+1.25VS
L1
BLM18PG121SN1D_0603
2
1

0.1U_0402_16V4Z

C102

0.1U_0402_16V4Z

C101

1U_0603_10V4Z

BC29
BB29

C77

VTT
PLL

VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
VCCA_SM_10
VCCA_SM_11
VCCA_SM_NCTF_1
VCCA_SM_NCTF_2

100mA
10U_0805_10V4Z

C100

C99

1U_0603_10V4Z

2
1
0_0603_5%

4.7U_0805_10V4Z

C93

VTTLF

10U_0805_10V4Z

+1.25VM_A_SM_CK

SM CK

D TV/CRT

R71

C92

LVDS

220U_6.3V_M

C91

+1.25VS_PEGPLL

100mA
AJ50

+1.25VS

+V1.25VS_AXF

VCC_DMI

HV

POWER

B23
B21
A21

+1.8V
R64
1
2
0_0805_5%

0.1U_0402_16V4Z

1
C90 +

350mA
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3

C88

1
2
0_0805_5%

+1.25VS

AT22
AT21
AT19
AT18
AT17
AR17
AR16

950mA

VCC_AXD_NCTF

C87

VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5

AR29

C86

+1.25VM_A_SM
R68

VCCA_PEG_PLL

AW18
AV19
AU19
AU18
AU17

R65
1
2
0_0805_5%

R63
0_0603_5%

C89
0.022U_0402_16V7K

U51

AT23
AU28
AU24
AT29
AT25
AT30

10U_0805_10V4Z

+1.25VS_PEGPLL 20 mils

VCC_AXD_1
VCC_AXD_2
VCC_AXD_3
VCC_AXD_4
VCC_AXD_5
VCC_AXD_6

PEG

VSSA_PEG_BG

+1.25VM_AXD

200mA

DMI

K49

0.1U_0402_16V4Z

C85

A PEG

0.1U_0402_16V4Z

A SM

VCCA_PEG_BG

5mA

+1.8V_SM_CK

+1.25VS

10U_0805_10V4Z

K50

+3VS_PEG_BG
R66
2
1
0_0603_5%

+3VS

C84

VSSA_LVDS

C83

VCCA_LVDS

B41

1U_0603_10V4Z

A41

A CK

1000P_0402_50V7K
1
C82

+1.8V_TXLVDS

A LVDS

10mA

C76

VCCA_MPLL

CRT

VCCA_HPLL

AM2

150mA

R61
0_0603_5%

C80

AL2

+1.25VM_MPLL

0.1U_0402_16V4Z

+1.25VM_HPLL

C70

C79

C69

VCCA_DPLLB

50mA

+1.25VS_DMI

C78

VCCA_DPLLA

H49

80mA

10U_0805_10V4Z

B49

+1.25VS_DPLLB

10U_FLC-453232-100K_0.25A_10%

10U_0805_10V4Z

+1.25VS_DPLLA

80mA

0.1U_0402_16V4Z

1
C74

C73
0.022U_0402_16V7K

+1.25VS

C68

VSSA_DAC_BG

0.1U_0402_16V4Z
C81

B32

2
2

C67

VCCA_DAC_BG

2.2U_0805_16V4Z

A30

+3VS_DAC_BG

+3VS
BLM18PG181SN1D_0603
2
1
R62

1
C71

4.7U_0805_10V4Z

+3VS_DAC_CRT

U13
U12
U11
U9
U8
U7
U5
U3
U2
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
R3
R2
R1

4.7U_0805_10V4Z

VCCA_CRT_DAC_1
VCCA_CRT_DAC_2

5mA

VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22

0.47U_0603_10V7K

VCCSYNC

A33
B33

80mA

1U_0603_10V4Z

U3H

J32

+1.25VS

+V1.25VS_AXF

R60

10U_0805_10V4Z

+1.25VS_DPLLB

+3VS_DAC_CRT
D

+VCCP

850mA

C75

1
C64

10U_0805_10V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

10mA

R58
2
1
0_0603_5%

0.1U_0402_16V4Z

1
C66

C65
0.022U_0402_16V7K

+3VS
BLM18PG181SN1D_0603
2
1
R59

TV

+3VS_DAC_BG

C106
0.1U_0402_16V4Z

C107
10U_0805_10V4Z

+VCCP_D

D2
+VCCP

R75
2
1
10_0402_5%
CH751H-40PT_SOD323-2

R76
2
1
0_0402_5%

+3VS_HV

+3VS
+1.5VS_QDAC
+3VS_TVDACA

2
1
100_0603_1%
1
C114

0.1U_0402_16V4Z

+1.5VS
R77

C113
0.022U_0402_16V7K

C116

0.1U_0402_16V4Z

C115
0.022U_0402_16V7K

+3VS
BLM18PG181SN1D_0603
2
1
R78

+1.8V_TXLVDS
R79

2
1
0_0603_5%
C118
1000P_0402_50V7K

+1.8V

C117
10U_0805_10V4Z

0208_Change C117 value from 220uF to 10uF.

+1.8V_LVDS
A

+3VS_TVDACB

2
1
0_0603_5%
1

C120
1U_0603_10V4Z

R81
C119
10U_0805_10V4Z

C122

0.1U_0402_16V4Z

C121
0.022U_0402_16V7K

+3VS
BLM18PG181SN1D_0603
2
1
R80

+1.8V

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRESTLINE(4/6)-PWR

Size Document Number

Custom LA-3732P
Date:

Re v
0.2

Wednesday, March 14, 2007

Sheet
1

10

of

40

+VCCP
+VCCP

U3G

VCC_AXG=7700mA

U3F

VCC_AXM_1
VCC_AXM_2
VCC_AXM_3
VCC_AXM_4
VCC_AXM_5
VCC_AXM_6
VCC_AXM_7

AT33
AT31
AK29
AK24
AK23
AJ26
AJ23

VCC_AXM=970mA

VCC AXM
VCC AXM NCTF

VCC_AXM_NCTF_1
VCC_AXM_NCTF_2
VCC_AXM_NCTF_3
VCC_AXM_NCTF_4
VCC_AXM_NCTF_5
VCC_AXM_NCTF_6
VCC_AXM_NCTF_7
VCC_AXM_NCTF_8
VCC_AXM_NCTF_9
VCC_AXM_NCTF_10
VCC_AXM_NCTF_11
VCC_AXM_NCTF_12
VCC_AXM_NCTF_13
VCC_AXM_NCTF_14
VCC_AXM_NCTF_15
VCC_AXM_NCTF_16
VCC_AXM_NCTF_17
VCC_AXM_NCTF_18
VCC_AXM_NCTF_19

+VCCP

VCC_AXG=7700mA
+VCCP
10U_0805_10V4Z

0.1U_0402_16V4Z

1
C138

C137

C139

1
C140

1U_0603_10V4Z

1
C141

2
10U_0805_10V4Z

330U_4V_M

CRESTLINE_1p0

1 C123

C124

C125
D

2
4.7U_0805_10V4Z

0.22U_0603_10V7K

C153 1U_0603_10V4Z

C152 1U_0603_10V4Z

C151 0.47U_0603_10V7K

AW45 VCCSM_LF1
BC39 VCCSM_LF2
BE39 VCCSM_LF3
BD17 VCCSM_LF4
BD4 VCCSM_LF5
AW8 VCCSM_LF6
AT6 VCCSM_LF7
1

C150 0.22U_0603_10V7K

VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7

0.1U_0402_16V4Z

C149 0.22U_0603_10V7K

VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34

T17
T18
T19
T21
T22
T23
T25
U15
U16
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
V26
V28
V29
Y31

C148 0.1U_0402_16V4Z

R20
T14
W13
W14
Y12
AA20
AA23
AA26
AA28
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
AH24
AH26
AD31
AJ20
AN14

VCC_AXG_NCTF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC_AXG_NCTF_61
VCC_AXG_NCTF_62
VCC_AXG_NCTF_63
VCC_AXG_NCTF_64
VCC_AXG_NCTF_65
VCC_AXG_NCTF_66
VCC_AXG_NCTF_67
VCC_AXG_NCTF_68
VCC_AXG_NCTF_69
VCC_AXG_NCTF_70
VCC_AXG_NCTF_71
VCC_AXG_NCTF_72
VCC_AXG_NCTF_73
VCC_AXG_NCTF_74
VCC_AXG_NCTF_75
VCC_AXG_NCTF_76
VCC_AXG_NCTF_77
VCC_AXG_NCTF_78
VCC_AXG_NCTF_79
VCC_AXG_NCTF_80
VCC_AXG_NCTF_81
VCC_AXG_NCTF_82
VCC_AXG_NCTF_83

C147 0.1U_0402_16V4Z

VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC_SM_36

VCC GFX NCTF

AU32
AU33
AU35
AV33
AW33
AW35
AY35
BA32
BA33
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
BJ34
BK32
BK33
BK34
BK35
BL33
AU30

VCC SM

C134

A3
B2
C1
BL1
BL51
A51

VCC_13

VCC GFX

1
C131
330U_4V_M

0.01U_0402_16V7K
C133

C146
0.1U_0402_16V4Z

C136

C145
0.1U_0402_16V4Z

C144
0.1U_0402_16V4Z

C143
0.22U_0402_10V4Z

C142
0.22U_0402_10V4Z

10U_0805_10V4Z
C135

10U_0805_10V4Z

AL24
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33

+1.8V
10U_0805_10V4Z
C132

VSS_SCB1
VSS_SCB2
VSS_SCB3
VSS_SCB4
VSS_SCB5
VSS_SCB6

R30

POWER
3720mA

POWER

VCC_AXM=970mA

R82
1
2
0_0603_5%

+VCCP

T27
T37
U24
U28
V31
V35
AA19
AB17
AB35
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
AR19
AR28

10U_0805_10V4Z

VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21

VSS SCB

VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
VCC_NCTF_45
VCC_NCTF_46
VCC_NCTF_47
VCC_NCTF_48
VCC_NCTF_49
VCC_NCTF_50

VCC NCTF

C130

0.1U_0402_16V4Z
C129

0.22U_0603_10V7K
C128

0.22U_0402_10V4Z
C127

10U_0805_10V4Z

C126
220U_6.3V_M

AB33
AB36
AB37
AC33
AC35
AC36
AD35
AD36
AF33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
V37

VSS NCTF

VCC=1260mA

VCC_1
VCC_2
VCC_3
VCC_5
VCC_4
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12

VCC SM LF

+VCCP
D

AT35
AT34
AH28
AC32
AC31
AK32
AJ31
AJ28
AH32
AH31
AH29
AF32

VCC CORE

VCC=1260mA

CRESTLINE_1p0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRESTLINE((5/6)-PWR/GND

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

11

of

40

U3I
A13
A15
A17
A24
AA21
AA24
AA29
AB20
AB23
AB26
AB28
AB31
AC10
AC13
AC3
AC39
AC43
AC47
AD1
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99

VSS

VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198

AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
BL47
C12
C16
C19
C28
C29
C33
C36
C41

U3J
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39

VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243

K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3

VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
VSS_253
VSS_254
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
VSS_274
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286

VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305

W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28

VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313

AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50

VSS

CRESTLINE_1p0

CRESTLINE_1p0
A

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

CRESTLINE((6/6)-PWR/GND

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

12

of

40

+1.8V

+1.8V
V_DDR_MCH_REF

<8> DDR_A_DQS#[0..7]

DDR_A_D2
DDR_A_D3

DDR_A_D8
DDR_A_D14

Layout Note:
Place near JP34

DDR_A_DQS#1
DDR_A_DQS1
DDR_A_D9
DDR_A_D15

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

V_DDR_MCH_REF <7,14,35>

DDR_A_D6
DDR_A_D0
DDR_A_DM0
DDR_A_D5
DDR_A_D7

C155

DDR_A_DQS#0
DDR_A_DQS0

<7,8> DDR_A_MA[0..14]

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_A_D4
DDR_A_D1

<8> DDR_A_DQS[0..7]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

C154

<8> DDR_A_DM[0..7]

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

2.2U_0805_16V4Z

JP4

<8> DDR_A_D[0..63]

DDR_A_D13
DDR_A_D12
DDR_A_DM1
M_CLK_DDR0
M_CLK_DDR#0

M_CLK_DDR0 <7>
M_CLK_DDR#0 <7>

DDR_A_D11
DDR_A_D10

+1.8V

DDR_A_DQS#2
DDR_A_DQS2

C156
330U_4V_M

DDR_A_D18
DDR_A_D19

DDR_A_D29
DDR_A_D24
DDR_A_DM3
DDR_A_D26
DDR_A_D27

DDR_CKE0_DIMMA

<7> DDR_CKE0_DIMMA

DDR_A_BS2

<8> DDR_A_BS2

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
DDR_A_MA10
DDR_A_BS0
DDR_A_WE#

<8> DDR_A_BS0
<8> DDR_A_WE#

+0.9V

DDR_A_CAS#
DDR_CS1_DIMMA#

<8> DDR_A_CAS#
<7> DDR_CS1_DIMMA#

M_ODT1

M_ODT1

DDR_A_D37
DDR_A_D36

DDR_A_DQS#4
DDR_A_DQS4

C178

C177

C176

C175

C174

C173

C172

C171

C170

C169

C168

C167

C166

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

<7>

DDR_A_D35
DDR_A_D32
DDR_A_D40
DDR_A_D44

DDR_A_DM5
DDR_A_D41
DDR_A_D46
DDR_A_D49
DDR_A_D48
+0.9V

4
3

4
3

RP3 56_0404_4P2R_5% RP4

1
4
4
2
3
3

56_0404_4P2R_5%
1 DDR_A_MA7
2 DDR_A_MA6

RP5 56_0404_4P2R_5% RP6

DDR_A_RAS#
1
4
4
DDR_CS0_DIMMA# 2
3
3

56_0404_4P2R_5%
1 DDR_A_MA12
2 DDR_A_MA9

DDR_A_MA1
DDR_A_BS0

RP7 56_0404_4P2R_5% RP8

1
4
4
2
3
3

56_0404_4P2R_5%
1 DDR_A_MA4
2 DDR_A_MA2

DDR_A_WE#
DDR_A_CAS#

RP9 56_0404_4P2R_5% RP10 56_0404_4P2R_5%

1
4
4
1 DDR_A_MA0
2
3
3
2 DDR_A_BS1

DDR_A_MA8
DDR_A_MA5

Layout Note:
Pla ce these resistor
closely JP34,all
trace length Max=1.5"

56_0404_4P2R_5%
1 DDR_CKE0_DIMMA
2 DDR_A_BS2

DDR_A_DQS#6
DDR_A_DQS6
DDR_A_D54
DDR_A_D50
DDR_A_D61
DDR_A_D60
DDR_A_DM7
DDR_A_D59
DDR_A_D58

+3VS

RP11 56_0404_4P2R_5% RP12 56_0404_4P2R_5%

DDR_CS1_DIMMA# 2
3
4
1 M_ODT0
M_ODT1
1
4
3
2 DDR_A_MA13
56_0404_4P2R_5% RP13 56_0404_4P2R_5%
4
1 DDR_CKE1_DIMMA
1
2
3
2 DDR_A_MA14

DDR_A_MA11
R85

CLK_SMBDATA
CLK_SMBCLK

<14,15> CLK_SMBDATA
<14,15> CLK_SMBCLK

C180

2006/02/13

Issued Date

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
204

FOX_ASOA426-M4R-TR
CONN@

SO-DIMM A

DDR_A_D20
DDR_A_D21

DDR_A_D23
DDR_A_D22
DDR_A_D28
DDR_A_D25
DDR_A_DQS#3
DDR_A_DQS3
DDR_A_D31
DDR_A_D30
DDR_CKE1_DIMMA

DDR_CKE1_DIMMA <7>

DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4
DDR_A_MA2
DDR_A_MA0
DDR_A_BS1
DDR_A_RAS#
DDR_CS0_DIMMA#
M_ODT0
DDR_A_MA13

DDR_A_BS1 <8>
DDR_A_RAS# <8>
DDR_CS0_DIMMA# <7>
M_ODT0

<7>

DDR_A_D39
DDR_A_D38
DDR_A_DM4
DDR_A_D34
DDR_A_D33
DDR_A_D45
DDR_A_D43
B

DDR_A_DQS#5
DDR_A_DQS5
DDR_A_D47
DDR_A_D42
DDR_A_D52
DDR_A_D53
M_CLK_DDR1
M_CLK_DDR#1

M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>

DDR_A_DM6
DDR_A_D51
DDR_A_D55
DDR_A_D57
DDR_A_D56
DDR_A_DQS#7
DDR_A_DQS7
DDR_A_D62
DDR_A_D63

SP07F001720 S SOCKET FOXCONN AS0A426-N4RN-7F DR2R H4

FOX_AS0A426-M4R-TR_200P

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PM_EXTTS#0 <7>

DDR_A_DM2

Compal Secret Data

Security Classification

56_0402_5%

C179
2

0.1U_0402_16V4Z

RP2

2.2U_0805_16V4Z

RP1
DDR_A_MA3
1
DDR_A_MA10
2

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
GND

R84
10K_0402_5%
2
1

C165

C164

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C163

0.1U_0402_16V4Z

C162

C161

0.1U_0402_16V4Z

C160

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C159

2.2U_0805_16V4Z

C158

2.2U_0805_16V4Z

C157

2.2U_0805_16V4Z

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

R83
10K_0402_5%
2
1

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
203

DDR_A_D16
DDR_A_D17
1

Title

Compal Electronics, Inc.

DDRII-SODIMM SLOT1

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

13

of

40

+1.8V

<8> DDR_B_DQS#[0..7]

+1.8V

<8> DDR_B_D[0..63]

V_DDR_MCH_REF

<8> DDR_B_DM[0..7]

DDR_B_D10
DDR_B_D11

+1.8V

DDR_B_D17
DDR_B_D20

C191

C190

0.1U_0402_16V4Z

C189

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C188

0.1U_0402_16V4Z

C187

C186

2.2U_0805_16V4Z

2.2U_0805_16V4Z

C185

2.2U_0805_16V4Z

C184

C183

2.2U_0805_16V4Z

2.2U_0805_16V4Z

DDR_B_DQS#2
DDR_B_DQS2

DDR_B_D18
DDR_B_D19
DDR_B_D28
DDR_B_D25
DDR_B_DM3
DDR_B_D30
DDR_B_D31

DDR_CKE2_DIMMB

<7> DDR_CKE2_DIMMB

Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS

DDR_B_BS2

<8> DDR_B_BS2

DDR_B_MA12
DDR_B_MA9
DDR_B_MA8
DDR_B_MA5
DDR_B_MA3
DDR_B_MA1

+0.9V

DDR_B_CAS#
DDR_CS3_DIMMB#

<8> DDR_B_CAS#
<7> DDR_CS3_DIMMB#
1

<7>

M_ODT3

M_ODT3

DDR_B_D32
DDR_B_D33

2
C204

C203

C202

C201

C200

C199

C198

C197

C196

C195

C194

C193

C192

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

DDR_B_MA10
DDR_B_BS0
DDR_B_WE#

<8> DDR_B_BS0
<8> DDR_B_WE#

DDR_B_DQS#4
DDR_B_DQS4
DDR_B_D34
DDR_B_D35

DDR_B_D40
DDR_B_D41
DDR_B_DM5
DDR_B_D42
DDR_B_D43

RP14
1
2

DDR_B_BS0
DDR_B_MA10

RP16 56_0404_4P2R_5% RP17 56_0404_4P2R_5%

DDR_B_MA14
1
4
4
1
DDR_B_MA11
2
3
3
2

DDR_B_MA0
DDR_B_BS1

RP18 56_0404_4P2R_5% RP19 56_0404_4P2R_5%

DDR_B_MA5
1
4
4
1
DDR_B_MA8
2
3
3
2

4
3

4
3

RP15 56_0404_4P2R_5%
DDR_B_MA9
1
DDR_B_MA12
2

Layout Note:
Pla ce these resistor
closely JP10,all
trace length Max=1.5"

DDR_B_D51
DDR_B_D50
DDR_B_D56
DDR_B_D61
DDR_B_DM7
DDR_B_D59
DDR_B_D58

RP20 56_0404_4P2R_5% RP21 56_0404_4P2R_5%

DDR_B_RAS#
DDR_B_MA7
1
4
4
1
DDR_CS2_DIMMB# 2
DDR_B_MA6
3
3
2

56_0402_5%

2.2U_0805_16V4Z

1
2

C206
C205

2006/02/13

Issued Date

M_CLK_DDR3
M_CLK_DDR#3

DDR_B_D21
DDR_B_D16

PM_EXTTS#1 <7>

DDR_B_DM2
DDR_B_D22
DDR_B_D23
DDR_B_D26
DDR_B_D24
DDR_B_DQS#3
DDR_B_DQS3
DDR_B_D29
DDR_B_D27

DDR_CKE3_DIMMB

DDR_CKE3_DIMMB <7>

DDR_B_MA14
DDR_B_MA11
DDR_B_MA7
DDR_B_MA6
DDR_B_MA4
DDR_B_MA2
DDR_B_MA0
DDR_B_BS1
DDR_B_RAS#
DDR_CS2_DIMMB#

DDR_B_BS1 <8>
DDR_B_RAS# <8>
DDR_CS2_DIMMB# <7>

M_ODT2
DDR_B_MA13

M_ODT2

DDR_B_DM4
DDR_B_D39
DDR_B_D38
DDR_B_D44
DDR_B_D45

DDR_B_DQS#5
DDR_B_DQS5
DDR_B_D46
DDR_B_D47
DDR_B_D52
DDR_B_D53
M_CLK_DDR2
M_CLK_DDR#2

M_CLK_DDR2 <7>
M_CLK_DDR#2 <7>

DDR_B_DM6
DDR_B_D54
DDR_B_D55
DDR_B_D60
DDR_B_D57
DDR_B_DQS#7
DDR_B_DQS7
DDR_B_D62
DDR_B_D63

FOX_AS0A426-N8RN-7F
CONN@

SO-DIMM B

SP07000BZ00 S SOCKET FOXCON AS0A426-N8RN-7F H8 DDR2R

FOX_AS0A426-N8RN-7F_200P

2006/03/10

Deciphered Date

<7>

DDR_B_D36
DDR_B_D37

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>

DDR_B_D14
DDR_B_D15

R86
1

+3VS

10K_0402_5%
A

Compal Secret Data

Security Classification

56_0404_4P2R_5%

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202

VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
GND

DDR_B_DM1

R87

DDR_CKE3_DIMMB
R88

DDR_B_BS2
DDR_CKE2_DIMMB

VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
GND

10K_0402_5%

RP22 56_0404_4P2R_5% RP23 56_0404_4P2R_5%

DDR_B_MA4
1
4
4
1
DDR_B_MA2
2
3
3
2
RP24
56_0404_4P2R_5% RP25 56_0404_4P2R_5%
DDR_CS3_DIMMB# 2
M_ODT2
3
4
1
M_ODT3
DDR_B_MA13
1
4
3
2
56_0404_4P2R_5% RP26
4
1
2
3

CLK_SMBDATA
CLK_SMBCLK

<13,15> CLK_SMBDATA
<13,15> CLK_SMBCLK
+3VS

DDR_B_CAS#
DDR_B_WE#
A

DDR_B_DQS#6
DDR_B_DQS6

0.1U_0402_16V4Z

+0.9V

DDR_B_MA1
DDR_B_MA3

DDR_B_D48
DDR_B_D49

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201

DDR_B_D12
DDR_B_D13

DDR_B_DQS#1
DDR_B_DQS1

DDR_B_D6
DDR_B_D7

DDR_B_D8
DDR_B_D9

DDR_B_DM0

C182

DDR_B_D2
DDR_B_D3

Layout Note:
Place near JP10

DDR_B_D5
DDR_B_D4

C181

DDR_B_DQS#0
DDR_B_DQS0
D

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS

0.1U_0402_16V4Z

DDR_B_D0
DDR_B_D1

<7,8> DDR_B_MA[0..14]

VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS

2.2U_0805_16V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

<8> DDR_B_DQS[0..7]

V_DDR_MCH_REF <7,13,35>

JP5

Title

Compal Electronics, Inc.

DDRII-SODIMM SLOT2

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

14

of

40

FSLB

FSLA

CLKSEL2

CLKSEL1

CLKSEL0

CPU
MHz

SRC
MHz

PCI
MHz

133

100

33.3

200

100

33.3

166

100

+3VS

2
1

FBMA-L11-201209-221LMA30T_0805

C207
10U_0805_10V4Z

33.3

C208
0.1U_0402_16V4Z

1
C209
680P_0402_50V7K

C210
0.1U_0402_16V4Z

+1.25VS

1
C211
680P_0402_50V7K

C212

C213
R90

0.1U_0402_16V4Z

Place close to U4

FSB Frequency Selet:

R91

0.1U_0402_16V4Z
2.2K_0402_5%

<20,22> ICH_SMBDATA

2.2K_0402_5%

Q3
3 2N7002_SOT23-3

CLK_SMBDATA

+1.25VS_CK505

Stuff

R1107

R1135

R1083

*(Default)

No Stuff

R1074

R1086

R1098

2
1

FBMA-L11-201209-221LMA30T_0805

R1086

R1139

R1135

No Stuff

R1083

R1107

R1128

R1113

R1098

R1135

R1139

R1074

R1128
R1139

10U_0805_10V4Z
1
1
C217

C216

0.1U_0402_16V4Z
1
C219
C218

C215

R1139

C214

2
10U_0805_10V4Z

R1135

2
680P_0402_50V7K

SB, MINI PCI

2
2
680P_0402_50V7K

+3VS

Q4
3 2N7002_SOT23-3

<20,22> ICH_SMBCLK

Stuff

R1113

0.1U_0402_16V4Z
1

667MHz

800MHz

0308_Change R89 and R92 form 0 ohm to bead, C209, C211, C216, C218 from 0.1uF to 680pF.
+3VS_CK505

Stuff
No Stuff

R1083

R1086

R1098

R1074

R1107

R1113

R1128

+1.25VS_CK505
R93

56_0402_5%
CLRP1
NO SHORT PADS

CPU_BSEL0

+VCCP

CLRP4,CLRP5 for 667/800 FSB select

SHORT CLRP5, NO SHORT CLRP4 -- CPU option
SHORT CLRP4, NO SHORT CLRP5 -- FSB 667

CLRP2
NO SHORT PADS

VDD_PCI
VDD48
VDDPLL3
VDDREF

39
55

VDDSRC
VDDCPU

12
20
26

VDD96_IO
VDDPLL3_IO
VDDSRC_IO

36
49

VDDSRC_IO
VDDCPU_IO

MCH_CLKSEL0 <7>

R98
1K_0402_5%

U4
2
9
16
61

0301_Change R105 from 22 ohm to 0 ohm.

0312_Change R106, 107, 109 from 22 to 33 ohm.

<5>

R97
2.2K_0402_5%
FSA 2
1

R102

475_0402_1%1

2 R103

475_0402_1%1

2 R104

0_0402_5%

2 R105

<23> CLK_PCI_LAN

33_0402_5% 1

2 R106

PCI_LANCLK 5

<30> CLK_PCI_EC

33_0402_5% 1

2 R107

27_SEL

PCI4/27_Select

<18> CLK_PCI_ICH

33_0402_5% 1

2 R109

ITP_EN

PCIF5/ITP_EN

<20> CLKSATAREQ#

@ 1K_0402_5%

CLKREQ#_B

<7>

<22,29,30> CLK_DEBUG_PORT

+VCCP

R111

PCI0/CR#_A

PCI_CLK1

PCI1/CR#_B

PCI2_TME

PCI2/TME

CPU_BSEL1

1
R115
0_0402_5%

MCH_CLKSEL1 <7>

Routing the trace at

least 10mil

R114
1K_0402_5%

C230
18P_0402_50V8J
@ R116

CLK_XTAL_IN

14.31818MHZ_16P
CLK_XTAL_OUT
2

<5>

60

X1

59

X2

C231
18P_0402_50V8J

0_0402_5%
<20> CLK_48M_ICH

33_0402_1% 1

R117

33_0402_1% 1

R120

33_0402_1% 1

2 @ R400

+VCCP
<20> CLK_14M_ICH
R121

<5>

CPU_BSEL2

1
R126
0_0402_5%

<30> CLK_14M_DEBUG

@ 1K_0402_5%

FSA

10

USB_48MHZ/FSLA

FSB

57

FSLB/TEST MODE

FSC

62

0_0402_5%

PCI_STOP#
CPU_STOP#

38
37

CLK_SMBCLK
CLK_SMBDATA

CLK_SMBCLK <13,14>
CLK_SMBDATA <13,14>
H_STP_PCI# <20>
H_STP_CPU# <20>

CPU0
CPU0#

54
53

R_CPU_BCLK
R_CPU_BCLK#

R94
1
1
R95

CPU1_F
CPU1#_F

51
50

R_MCH_BCLK
R_MCH_BCLK#

R96
1
1
R99

SRC8/ITP
SRC8#/ITP#

47
46

SRC10#
SRC10

35
34

SRC11/CR#_H
SRC11#/CR#_G

33
32

SRC9
SRC9#

30
31

SRC7/CR#_F
SRC7#/CR#_E

44
43

R_CLKREQ#_G

SRC6
SRC6#

41
40

R112
R_CLK_PCIE_MCard 1
R_CLK_PCIE_MCard# 1
R113

2
2

SRC4
SRC4#

27
28

R_MCH_3GPLL
R_MCH_3GPLL#

R118
1
1
R119

2
2

0_0402_5%
0_0402_5%

2
2

0_0402_5%
0_0402_5%

R_CPU_XDP R100
1
R_CPU_XDP#
1
R101

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

2
2

R108
2

0_0402_5%
0_0402_5%

VDDSRC_IO

SRC3/CR#_C
SRC3#/CR#_D

24
25

R_PCIE_ICH
R_PCIE_ICH#

42

GNDSRC

SRC2/SATA
SRC2#/SATA#

21
22

R_PCIE_SATA
R_PCIE_SATA#

R127
1
1
R128

2
2

0_0402_5%
0_0402_5%

GNDPCI

11

GND48

SRC1/SE1/27MHz_NonSS
SRC1#/SE2/27MHz_SS

17
18

SSCDREFCLK
R130
SSCDREFCLK#
R131

1
1

2
2

0_0402_5%
0_0402_5%

15

GND
SRC0/DOT96
SRC0/DOT96#

13
14

R132
R_MCH_DREFCLK
1
R_MCH_DREFCLK# 1
R133

2
2

0_0402_5%
0_0402_5%

CK_PWRGD/PD#

56

1
@ R137

ICS9LPRS355_TSSOP64

1
@ R367
1
R344

GND
GNDCPU

For 27_SEL, 0 = Enable DOT96 & SRC1,

23

GNDSRC

29

GNDSRC

58

GNDREF

1 = Overclocking of CPU and SRC NOT allowed

* Internal Pull-Up Resistor

** Internal Pull-Down Resistor

CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>

CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
CLK_CPU_XDP <4>
CLK_CPU_XDP# <4>

C220

C221

C222

C225

C227

C229

1 CLK_48M_ICH
@ 5P_0402_50V8C
1 CLK_14M_ICH
@ 4.7P_0402_50V8C
1 CLK_PCI_ICH
@ 4.7P_0402_50V8C
1 CLK_PCI_EC
@ 4.7P_0402_50V8C
1 CLK_PCI_LAN
@ 4.7P_0402_50V8C
1 CLK_DEBUG_PORT
@ 5P_0402_50V8C

475_0402_1%
1
MINI_CLKREQ# <22>
R110 10K_0402_5%
1
2
+3VS

45

52

PCI2_TME

2
2

R122
1
1
R123

19

For PCI2_EN, 0 = Overclocking of CPU and SRC Allowed

0_0402_5%
0_0402_5%

For Layout request:

1. Change MINI_CLKREQ# from pin 32 to pin 43.
2. Change CLK_PCIE_MCARD from SRC9 to SRC6.

REF0/FSLC/TEST_SEL

For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#

1= Enable SRC0 & 27MHz

2
2

CLK_PCIE_MCARD <22>
CLK_PCIE_MCARD# <22>

CLK_MCH_3GPLL <7>
CLK_MCH_3GPLL# <7>

CLK_PCIE_ICH <20>
CLK_PCIE_ICH# <20>

CLK_PCIE_SATA <19>
CLK_PCIE_SATA# <19>

MCH_SSCDREFCLK <7>
MCH_SSCDREFCLK# <7>

CLK_MCH_DREFCLK <7>
CLK_MCH_DREFCLK# <7>

0_0402_5%

VGATE

<20,37>

0_0402_5%

CLK_ENABLE <30>

0_0402_5%

CK_PWRGD <20>

2
1

R139
10K_0402_5%

Compal Secret Data

Security Classification

R140
10K_0402_5%
@

2006/02/13

Issued Date

27_SEL

R138
10K_0402_5%
@

R136
10K_0402_5%

R135
10K_0402_5%
@

ITP_EN

+3VS

+3VS

R134
10K_0402_5%

64
63

MCH_CLKSEL2 <7>

R125
1K_0402_5%

@ R129

+3VS

SCLK
SDATA

+1.25VS_CK505

48

FSC

R124
10K_0402_5%
2
1

NC

PCI3

Y1
@ 1K_0402_5%
FSB

CLK_SMBCLK

CPU Driven

2
G

R92

2
G

+3VS_CK505

R89
+3VS

FSLC

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.

Clock generator

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

15

of

40

EMI

+R_CRT_VCC , +CRTVDD (40mils)

+5VS

EMI

+R_CRT_VCC
F1
1
1

RB411D_SOT23

+CRTVDD

NZQA5V6AXV5T1_SOT533-5

CRT CONNECTOR

C232
0.1U_0402_16V4Z

2
2
1

CRT_VSYNC_R

74AHCT1G125GW_SOT353-5

2
G
2

@ D3

CLOSE TO JP3
DC060001M00 D-CONN 15P D-SUB_F C10510-11505-L
DC060002300 D-CONN 15P VGA_F 070546FR015S235ZR SUYIN

2
G

1
R149

2
0_0402_5%

3VDDCDA <9>

2
0_0402_5%

3VDDCCL <9>

R148

Q6
3V_DDCCL
3 2N7002_SOT23-3

R147

R145 4.7K_0402_5%

220P_0402_50V8J

C240
10P_0402_50V8J

U6
Y

16
17

ALLTO_C10510-115A5-L
Q5
3 2N7002_SOT23-3 3V_DDCDA

R150

2
2.2K_0402_5%
+3VS

C243

3
1

5
P
A

CRT_VSYNCRFL
1
2
L6
FBM-L11-160808-800LMT_0603

CRTVSYNC
2
0_0402_5%

CRT_HSYNCRFL
1
2
L5
FBM-L11-160808-800LMT_0603

74AHCT1G125GW_SOT353-5

OE#

R151
<9> CRT_VSYNC

+CRTVDD
1

CRT_HSYNC_R

C238
22P_0402_50V8J

220P_0402_50V8J

C242

CRTL_B
C237
22P_0402_50V8J

U5
Y

CRTL_G

R144 4.7K_0402_5%

EMI

C241 10P_0402_50V8J

P
2

CR THSYNC
2
0_0402_5%

0.1U_0402_16V4Z
R146
<9> CRT_HSYNC

OE#

C239
1
2

CONN@ JP6
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

CRTL_R

C236
22P_0402_50V8J

EMI

+5VS

C235
10P_0402_50V8J

CRT_B

R143
75_0402_5%
1
2

CRT_B
C234
10P_0402_50V8J

<9>

CRT_G

R142
75_0402_5%
1
2

CRT_G

C233
10P_0402_50V8J

<9>

L2
MBK2012800YZF
1
2
L3
MBK2012800YZF
1
2
L4
MBK2012800YZF
1
2

CRT_R

R141
75_0402_5%
1
2

CRT_R

1.1A_6VDC_FUSE

EMI
<9>

+CRTVDD
D7

Place close to JP6

D6
@ DAN217_SC59

D5
DAN217_SC59

D4
DAN217_SC59

CRTL_B
CRTL_G
CRTL_R

2.2K_0402_5%

TV-Out Connector
S-Video

2
0_0402_5%

TVLUMA

R153
<9>

TV_CRMA

<9>

TV_COMPS

2
0_0402_5%

TVCRMA

R154

C246
270P_0402_50V7K

C245
270P_0402_50V7K

C244
270P_0402_50V7K

R157
75_0402_5%
2
1

R156
75_0402_5%
2
1

TVCOMPS

R155
75_0402_5%
2
1

2
0_0402_5%

L7
MBC1608121YZF_0603
1
2

LUMA_CL

L8
MBC1608121YZF_0603
1
2

CRMA_CL

L9
MBC1608121YZF_0603
1
2

COMPS_CL

JP7

R158
1

1
2
3
4
5
6
7

C249
330P_0402_50V7K

C248
330P_0402_50V7K

TV_LUMA

C247
330P_0402_50V7K

EMI
R152
<9>

1
2
3
4
5
6
7

GND
GND

8
9

SUYIN_030107FR007G317ZR
CONN@
DC230001300 CONN SUYIN 030107FR007G317ZR 7P S_VIDEO
SUYIN_030107FR007G317ZR_7P

TVGND

0_0805_5%

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

CRT & TVout Connector

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

E

16

of

40

LVDS CONN
D

B+

+LCDVDD

INVPWR_B+
@
L10

2 0_0805_5%

C250

L11
1
2
FBMA-L11-201209-221LMA30T_0805

0.1U_0402_16V4Z

C251
0.1U_0402_16V4Z

0308_Reserve L10 and install L11.

JP8

C254

C253
1

<9>
<9>

LVDSB0+
LVDSB0-

<9>
<9>

LVDSB1+
LVDSB1-

<9>
<9>

LVDSB2+
LVDSB2-

LVDSBC+
LVDSBCLVDSB0+
LVDSB0LVDSB1+
LVDSB1LVDSB2+
LVDSB2-

LVDSA2+
LVDSA2-

LVDSA2+ <9>
LVDSA2- <9>

LVDSA1+
LVDSA1-

LVDSA1+ <9>
LVDSA1- <9>

LVDSA0+
LVDSA0-

+3VS

LVDSA0+ <9>
LVDSA0- <9>

LVDSAC+
LVDSAC-

LVDSAC+ <9>
LVDSAC- <9>

INVTPWM
DISPLAYOFF#
DAC_BRIG
LCD_CLK
LCD_DAT

ACES_88242-4001
CONN@

LVDS connector

R159
2.2K_0402_5%

INV_PWM <30>
DAC_BRIG <30>
LCD_CLK <9>
LCD_DATA <9>

C255
680P_0402_50V7K

LVDSBC+
LVDSBC-

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42

<9>
<9>

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
2
1

C252

+3VS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GND

LCD_CLK
LCD_DATA

R160
2.2K_0402_5%
C

+LCDVDD

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41

INVPWR_B+

C256
680P_0402_50V7K

SP02000EA00 S W-CONN ACES 88242-4001 40P P1

ACES_88242-4001_40P

0308_Install all cap for EMI request.

0308_Install all cap for EMI request.

+LCDVDD
B

+LCDVDD

+3VS

Q7

+5VALW

+3VS
2
S

SI2301BDS-T1-E3_SOT23-3
3

R162

R161

<30>

BKOFF#

D9

C260
0.1U_0402_16V4Z

Q9
2N7002_SOT23-3

C259
0.047U_0402_16V7K

C257
4.7U_0805_10V4Z

C258

ENABLT

2
CH751H-40PT_SOD323-2

R164
4.7U_0805_10V4Z

100K_0402_5%

R308
100K_0402_5%

2
G
1

1
2
47K_0402_5%

R298

<9>

ENAVDD

DISPLAYOFF#

2
CH751H-40PT_SOD323-2

2
G
S

<9>

D8

2
1

D
Q8
2N7002_SOT23-3

4.7K_0402_5%

2
G

R163
47K_0402_5%

100_0402_5%

Avoid Panel display garbage after power on.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

LCD CONN.

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

17

of

40

PCI_GNT0#
1

+3VS

PCI_DEVSEL#

@ R165
1K_0402_5%

PCI_STOP#
PCI_TRDY#

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

<23> PCI_AD[0..31]

U7B

PCI_FRAME#
PCI_PLOCK#
PCI _IRDY#
PCI_SERR#
PCI_PERR#

+3VS

2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
1
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%
2
8.2K_0402_5%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQF#

D20
E19
D19
A20
D17
A21
A19
C19
A18
B16
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
D6
A3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

F9
B5
C5
A10

PIRQA#
PIRQB#
PIRQC#
PIRQD#

PCI_PIRQG#
PCI_PIRQH#

<23> PCI_PIRQA#

PCI_REQ0#
PCI_REQ1#

PCI

REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55

A4
D7
E18
C18
B19
F18
A11
C10

PCI_REQ0#
PCI_GNT0#
PCI_REQ1#

C/BE0#
C/BE1#
C/BE2#
C/BE3#

C17
E15
F16
E17

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#

C8
D9
G6
D16
A7
B7
F10
C16
C9
A17

PCI _IRDY#
PCI_PAR
PCI_PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#

PLTRST#
PCICLK
PME#

AG24
B10
G7

PCI_PLTRST#
CLK_PCI_ICH
PCI_PME#

PCI_REQ0# <23>
PCI_GNT0# <23>

PCI_REQ2#
PCI_REQ3#
PCI_GNT3#

T23
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

<23>
<23>
<23>
<23>

PCI_IRDY# <23>
R174
PCI_PAR <23>
PCI_RST#
2
1
0_0402_5%
PCI_DEVSEL# <23>
PCI_PERR# <23>
PCI_SERR# <23>
PCI_STOP# <23>
PCI_TRDY# <23>
PCI_FRAME# <23>

R178
PLT_RST#
2
1
0_0402_5%
CLK_PCI_ICH <15>
PCI_PME# <23,30>

Place closely pin B10

Interrupt I/F
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5

F8
G11
F12
B3

PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#

PCI_RST# <23,29,30>

PLT_RST# <7,22>

Boot BIOS Strap

CLK_PCI_ICH

PCI_GNT0#

R186

SPI_CS#1

Boot BIOS Location

ICH8M REV 1.0

PCI_REQ2#

@ 10_0402_5%
1

1
R175
1
R176
1
R177
1
R179
1
R180
1
R181
1
R182
2
R183
1
R184
1
R185
1
R187
1
R188

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

1
R166
1
R167
1
R168
1
R169
1
R170
1
R171
1
R172
1
R173

PCI_REQ3#
C261

@ 8.2P_0402_50V

SPI

PCI

LPC

A16 swap override Strap

*Low= A16 swap override Enble
PCI_GNT3# High= Default

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH8(1/4)-PCI/INT

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

18

of

40

+RTCVCC

ICH8M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)

1M_0402_5%
2 SM_INTRUDER#

R193
1

330K_0402_1%
2 ICH_INTVRMEN

R191
1

+3VS
R190

@ R192
0_0402_5%

ICH_INTVRMEN

GATEA20

Low = Internal VR Disabled

High = Internal VR Enabled(Default)

@ R195
0_0402_5%

10K_0402_5%
R194

330K_0402_1%
2 LAN100_SLP

R189
1

KB_RST#

ICH8M LAN100 SLP Strap

(Internal VR for VccLAN1.05 and VccCL1.05)

10K_0402_5%
D

ICH_LAN100_SLP

Low = Internal VR Disabled

High = Internal VR Enabled(Default)

+VCCP
R196
H_FERR#

AF23

RTCRST#

C264
1U_0603_10V4Z

CLRP3
SHORT PADS

INTRUDER#

ICH_INTVRMEN AF25
LAN100_SLP
AD21

INTVRMEN
LAN100_SLP

0205_Remove R401.

OUT

IN

Y2

NC

GLAN_CLK

D22

LAN_RSTSYNC

C21
B21
C22

LAN_RXD0
LAN_RXD1
LAN_RXD2

D21
E20
C20

LAN_TXD0
LAN_TXD1
LAN_TXD2

AH21

NC

32.768KHZ_12.5P_1TJS125BJ2A251

B24

0205_Change Crystal type.

+1.5VS

R202 1

2 24.9_0402_1%

<24> ACZ_BITCLK
<24> ACZ_SYNC

R203 33_0402_5% 1
R205 33_0402_5% 1

<24,30> ACZ_RST#

R206 33_0402_5% 1

GLAN_COMP

<28> SATA_LED#
<22> SATA_RXN0_C
<22> SATA_RXP0_C
<22> SATA_TXN0
<22> SATA_TXP0

R208 33_0402_5% 1

2
2

AJ16
AJ15

HDA_BIT_CLK
HDA_SYNC

HDARST#

AE14

HDA_RST#

ACZ_SDIN0

AJ17
AH17
AH15
AD13

HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3

AE13

HDA_SDOUT

AE10
AG14

HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34

AF10

SATALED#

AF6
AF5
AH5
AH6

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

AG3
AG4
AJ4
AJ3

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

AF2
AF1
AE4
AE3

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

AB7
AC6

SATA_CLKN
SATA_CLKP

AG1
AG2

SATARBIAS#
SATARBIAS

HDA_SDOUT

SATA_LED#
SATA_RXN0_C
3900P_0402_50V7K
SATA_RXP0_C
SATA_TXN0
C265 1
2
SATA_TXP0
C266 1
2

SATA_TXN0_C
SATA_TXP0_C

3900P_0402_50V7K

<15> CLK_PCIE_SATA#
<15> CLK_PCIE_SATA

GLAN_COMPI
GLAN_COMPO

HDA_BITCLK
HDA_SYNC

<24> ACZ_SDIN0

<24> ACZ_SDOUT

D25
C25

GLAN_DOCK#/GPIO13

CLK_PCIE_SATA#
CLK_PCIE_SATA
R211
1

24.9_0402_1%

E5
F5
G8
F6

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

FWH4/LFRAME#

C4

LPC_FRAME#

LDRQ0#
LDRQ1#/GPIO23

G9
E6

LPC_DRQ0#
T25 PAD

LPC_FRAME# <22,29,30>

A20GATE
A20M#

AF13
AG26

GATEA20
H_A20M#

DPRSTP#
DPSLP#

AF26
AE26

H_DPRSTP_R#

FERR#

AD24

H_DPSLP#
H_FERR#

CPUPWRGD/GPIO49

AG29

H_PW RGOOD

IGNNE#

AF27

H_IGNNE#

INIT#
INTR
RCIN#

AE24
AC20
AH14

H_INIT#
H_INTR
KB_RST#

NMI
SMI#

AD23
AG28

H_NMI
H_SMI#

IHDA

C263
15P_0402_50V8J

SM_INTRUDER# AD22

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

H_DPRSTP#

56_0402_5%
@ R198
2
1

H_DPSLP#

56_0402_5%
@ R200
2
1
56_0402_5%

LPC_DRQ#0 <30>
GATEA20 <30>
H_A20M# <4>
2
R201

H_DPRSTP#
1
0_0402_5%

H_DPRSTP# <5,7,37>

H_DPSLP# <5>
H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>

within 2" from R1557

H_INIT# <4>
H_INTR <4>
KB_RST# <30>

+VCCP
C

ICH_RTCRST#

RTC
LPC

20K_0402_5%

LAN / GLAN
CPU

RTCX1
RTCX2

IDE

AG25
AF24

SATA

+RTCVCC
1

ICH_RTCX1
ICH_RTCX2
R199

10M_0402_5%
C262
15P_0402_50V8J

LPC_AD[0..3] <22,29,30>

U7A

ICH_RTCX2

H_NMI <4>
H_SMI# <4>

STPCLK#

AA24

H_STPCLK#

THRMTRIP#

AE27

THRMTRIP_ICH#

TP8

AA23

R204
56_0402_5%

H_STPCLK# <4>
1

R207

24_0402_1%

ICH_RTCX1
R197
1

H_THERMTRIP# <4,7>

IDE_HDD[0..15] <22>

DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15

V1
U2
V3
T1
V4
T5
AB2
T6
T3
R2
T4
V6
V5
U1
V2
U6

IDE_HDD0
IDE_HDD1
IDE_HDD2
IDE_HDD3
IDE_HDD4
IDE_HDD5
IDE_HDD6
IDE_HDD7
IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15

DA0
DA1
DA2

AA4
AA1
AB3

IDE_HDA0
IDE_HDA1
IDE_HDA2

DCS1#
DCS3#

Y6
Y5

IDE_HDCS1#
IDE_HDCS3#

DIOR#
DIOW#
DDACK#
IDEIRQ
IORDY
DDREQ

W4
W3
Y2
Y3
Y1
W5

IDE_HDIOR#
IDE_HDIOW#
IDE_HDACK#
IDE_HIRQ
IDE_ HIORDY
IDE_HDREQ

placed within 2" from ICH8M

+3VS

IDE_HDA0 <22>
IDE_HDA1 <22>
IDE_HDA2 <22>

IDE_ HIORDY
IDE_HIRQ

R209 1
R210 1

2 4.7K_0402_5%
2 8.2K_0402_5%
B

IDE_HDCS1# <22>
IDE_HDCS3# <22>
IDE_HDIOR# <22>
IDE_HDIOW# <22>
IDE_HDACK# <22>
IDE_HIRQ <22>
IDE_HIORDY <22>
IDE_HDREQ <22>

0226_Change RTC battery and connector.

ICH8M REV 1.0

Within 500 mils

BATT1

45@ CR2032 RTC BATTERY

+RTCVCC

+3VL

BATT1.1
D10
R212 W=20mils
2
R213
1
2
1
W=20mils
W=20mils
3
1
2
W=20mils
0_0402_5%
1K_0402_5%
DAN202U_SC70
2
A

2006/02/13

Issued Date

C267
1U_0603_10V4Z

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

1
2
G1
G2
A

ACES_85204-02001
CONN@

Compal Secret Data

Security Classification

JBATT1
1
2
3
4

Title

Compal Electronics, Inc.

ICH8(2/4)_LAN,HD,IDE,LPC

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

19

of

40

+3VALW

@ R231
R232
@ R235
R394
+3VS

@ R236
@ R237

GPIO39
2
10K_0402_5%

GPIO18
2
8.2K_0402_5%

1
1
1

GPIO38
2
10K_0402_5%

<15> H_STP_PCI#
<15> H_STP_CPU#

R229

1
0_0402_5%

PAD T29

GPIO20
2
8.2K_0402_5%

<4>

CLKRUN#
2
8.2K_0402_5%

2
10K_0402_5%

MCH_ICH_SYNC#
2
10K_0402_5%

SIRQ
2
10K_0402_5%

PAD T31

R239
R241
R242
R244

<15> CLKSATAREQ#

CLKSATAREQ#
2
10K_0402_5%

IDE_RESET#
2
8.2K_0402_5%

2
8.2K_0402_5%

<22> IDE_RESET#
<24>

SB_SPKR

<7> MCH_ICH_SYNC#

PM_BMBUSY#

2
@ R246

SUS_STAT#/LPCPD#
SYS_RESET#

PM_BMBUSY#

AG12

BMBUSY#/GPIO0

EC_LID_OUT#

AG22

SMBALERT#/GPIO11

H_STP_PCI#
R_STP_CPU#

AE20
AG18

STP_PCI#/GPIO15
STP_CPU#/GPIO25

CLKRUN#

AH11

CLKRUN#/GPIO32
WAKE#
SERIRQ
THRM#

VGATE

AJ20

VRMPWRGD

SST_CTL

AJ22

TP7

OCP#

OCP#

<30> EC_SMI#
<30> EC_SCI#

OCP#

SUS_STAT#
F4
XDP_DBRESET# AD15

ICH_PCIE_WAKE#AE17
SIRQ
AF12
THERM_SCI#
AC13

<22> ICH_PCIE_WAKE#
<30>
SIRQ
<30> THERM_SCI#
2
1
R395 100K_0402_5%
<15,37> VGATE

GPIO22
2
8.2K_0402_5%

AJ8
AJ9
AH9
EC_SMI#
AE16
EC_SCI#
AC19
AG8
GPIO18 AH12
GPIO20 AE11
GPIO22 AG10
GPIO27 AH25
AD16
CLKSATAREQ# AG13
GPIO38 AF9
GPIO39 AJ11
IDE_RESET# AD10
SB_SPKR

AD9

MCH_ICH_SYNC#AJ13
ICH_RSVD
1
1K_0402_5%

AJ21

CLK14
CLK48

TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
GPIO8
GPIO12
TACH0/GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SPKR
MCH_SYNC#
TP3
ICH8M REV 1.0

CLK_14M_ICH
CLK_48M_ICH

AG9
G5

SUSCLK

ICH_SUSCLK

SLP_S3#
SLP_S4#
SLP_S5#

AG23
AF21
AD18

SLP_S3#
SLP_S4#
SLP_S5#

S4_STATE#/GPIO26

AH27

S4_STATE#

PWROK

AE23

PM_PWROK

DPRSLPVR/GPIO16

AJ14

DPRSLPVR

BATLOW#

AE21

ICH_LOW_BAT#

PWRBTN#

C2

PWRBTN_OUT#

LAN_RST#

AH20

RSMRST#

AG27
E1

2 SB_SPKR
@ 10K_0402_5%

1
@ 10_0402_5%

C268
@ 4.7P_0402_50V8C

C269
D

@ 4.7P_0402_50V8C

SLP_S3#
SLP_S4#
SLP_S5#

<30>
<30>
<30>

T28 PAD
PM_PWROK <7,30>
DPRSLPVR <7,37>
1
@ R398

0205 Change to connect to GND.

2
100K_0402_5%

PWRBTN_OUT# <30>

R233 1
2
0_0402_5%
EC_RSMRST#
1
2 R234
100_0402_5%
CK_PW RGD
CK_PWRGD <15>

E3

M_PWROK

AJ25

PM_SLP_M#

CL_CLK0
CL_CLK1

F23
AE18

CL_CLK0

CL_DATA0
CL_DATA1

F22
AF19

CL_DATA0

CL_VREF0
CL_VREF1

D24
AH23

CL_VREF0_ICH
CL_VREF1_ICH

CL_RST#

AJ23

MEM_LED/GPIO24
ME_EC_ALERT/GPIO10
EC_ME_ALERT/GPIO14
WOL_EN/GPIO9

AJ27
AJ24
AF22
AG19

EC_RSMRST# <30>

M_PWROK <7,30>
T30 PAD
R238 3.24K_0402_1%
1
2
+3VS

CL_CLK0 <7>
CL_DATA0 <7>

CL_RST# <7>
WL_ON#

WL_ON#
1
2
R24510K_0402_5%

<22>

C270

R240
453_0402_1%

0.1U_0402_16V4Z

+3VALW

R243
1

3.24K_0402_1%
2
+3VALW

C271

R247
453_0402_1%

R396
2

100K_0402_5%
2

1
R248

EC_RMRST#

low-->default
+3VS

R220

@ 10_0402_5%

T27 PAD

SLP_M#

CLPWROK

CLK_14M_ICH <15>
CLK_48M_ICH <15>

D3

CK_PWRGD

PAD
PAD
PAD
PAD

RI#

T45
T46
T47
T48

R230

AF17

AJ12
AJ10
AF11
AG11

R228

I CH_RI#

SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37

+3VS

<30> EC_LID_OUT#

SMBCLK
SMBDATA
LINKALERT#
SMLINK0
SMLINK1

@ R227
<7> PM_BMBUSY#
10K_0402_5%

AJ26
AD19
AG21
AC17
AE19

0.1U_0402_16V4Z

@ R226
10K_0402_5%

ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ME_EC_CLK1
ME_EC_DATA1

2
1ME_EC_CLK1
10K_0402_5%

PAD T26
<4> XDP_DBRESET#

R225

+3VS
2

2
1ME_EC_DATA1
10K_0402_5%

R219
U7C

R224

CLK_14M_ICH

2.2K_0402_5%

SATA
GPIO

2 XDP_DBRESET#
1K_0402_5%

2.2K_0402_5%
<15,22> ICH_SMBCLK
<15,22> ICH_SMBDATA

SMB

2 I CH_RI#
10K_0402_5%

2 ICH_PCIE_WAKE#
1K_0402_5%

R217

Clocks

R223

R216

SYS
GPIO

R221

1 ICH_LOW_BAT#
8.2K_0402_5%

Power MGT

R218

Place closely pin AG9

CLK_48M_ICH

MISC
GPIO
Controller Link

R215

2 LINKALERT#
10K_0402_5%

R214

+3VALW

Place closely pin G5

High -->No boot

U7D
PCIE_RXN1
PCIE_RXP1
PCIE_TXN1
PCIE_TXP1

PCIE_RXN1
PCIE_RXP1
1 C272 PCIE_C_TXN1
1 C273 PCIE_C_TXP1

0.1U_0402_16V4Z 2
0.1U_0402_16V4Z 2

+3VALW

1
1
1
1
1
1
1

2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

+3VALW
2

@ R250
10K_0402_5%
1

USB_OC#3
R392
USB_OC#4
R385
USB_OC#5
R386
USB_OC#6
R387
USB_OC#7
R388
USB_OC#8
R389
USB_OC#9
R390
USB_OC#2
R391

<27> USB_OC#0
<27> USB_OC#2

USB_OC#0

1
2
R380 10K_0402_5%
1
2 USB_OC#1
R381 0_0402_5%

P27
P26
N29
N28

PERN1
PERP1
PETN1
PETP1

M27
M26
L29
L28

PERN2
PERP2
PETN2
PETP2

K27
K26
J29
J28

PERN3
PERP3
PETN3
PETP3

H27
H26
G29
G28

PERN4
PERP4
PETN4
PETP4

F27
F26
E29
E28

PERN5
PERP5
PETN5
PETP5

D27
D26
C29
C28

PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP

PAD T40
PAD T41
PAD T42

SPICLK C23
SPI_CS0# B23
SPI_CS1# E22

PAD T43

SPI_MOSI D23
SPI_MISO F21

USB_OC#0
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#4
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#8
USB_OC#9

AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18

DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP

V27
V26
U29
U28

DMI_RXN0
DMI_RXP0
DMI_TXN0
DMI_TXP0

DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP

Y27
Y26
W29
W28

DMI_RXN1
DMI_RXP1
DMI_TXN1
DMI_TXP1

DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP

AB26
AB25
AA29
AA28

DMI_RXN2
DMI_RXP2
DMI_TXN2
DMI_TXP2

DMI_RXN2 <7>
DMI_RXP2 <7>
DMI_TXN2 <7>
DMI_TXP2 <7>

DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

AD27
AD26
AC29
AC28

DMI_RXN3
DMI_RXP3
DMI_TXN3
DMI_TXP3

DMI_RXN3 <7>
DMI_RXP3 <7>
DMI_TXN3 <7>
DMI_TXP3 <7>

DMI_CLKN
DMI_CLKP

T26
T25

CLK_PCIE_ICH#
CLK_PCIE_ICH

DMI_ZCOMP
DMI_IRCOMP

Y23
Y24

PCI-Express
Direct Media Interface

<22>
<22>
<22>
<22>

SPI_CLK
SPI_CS0#
SPI_CS1#

SPI

WLAN

SPI_MOSI
SPI_MISO
OC0#
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#
OC9#

USB

DMI_RXN0 <7>
DMI_RXP0 <7>
DMI_TXN0 <7>
DMI_TXP0 <7>
DMI_RXN1 <7>
DMI_RXP1 <7>
DMI_TXN1 <7>
DMI_TXP1 <7>

DMI_IRCOMP

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P

G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2

USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

USBRBIAS#
USBRBIAS

F2
F3

USBRBIAS

CLK_PCIE_ICH# <15>
CLK_PCIE_ICH <15>
R249 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2

Within 500 mils

+1.5VS
<27>
<27>
<27>
<27>
<27>
<27>

To USB/B.
To USB/B.
To MB.

USB20_N4 <27>
USB20_P4 <27>

To Card reader/B.

0228_Connect USB4 to Card reader/B.

1
R251

2
22.6_0402_1%

ICH8M REV 1.0

Within 500 mils

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

ICH8(3/4)_PM,USB,GPIO

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

1

20

of

40

U7E

+VCCP

1170mA

+3VS

C279

C280

C281

10U_0805_10V4Z

2.2U_0805_16V4Z

D11

R254
CH751H-40PT_SOD323-2

20 mils

100_0402_5%

ICH_V5REF_RUN
1

C284
0.1U_0402_16V4Z

R256

C297

10U_0805_10V4Z

C296

C298
1U_0603_10V4Z

AC1
AC2
AC3
AC4
AC5

VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
VCC1_5_A[09]
VCC1_5_A[10]

VCC1_5_A=1120mA
+1.5VS
B

C300
1U_0603_10V4Z

VCC1_5_A[11]
VCC1_5_A[12]

AA5
AA6

VCC1_5_A[13]
VCC1_5_A[14]

G12
G17
H7

VCC1_5_A[15]
VCC1_5_A[16]
VCC1_5_A[17]

C305
0.1U_0402_16V4Z

F1
L6
L7
M6
M7

VCC1_5_A[20]
VCC1_5_A[21]
VCC1_5_A[22]
VCC1_5_A[23]
VCC1_5_A[24]

W23

VCC1_5_A[25]

VCC1_5_A=1120mA
+1.5VS
T36
T37

+3VS

VCC_LAN1_05_INT_ICH_1 F17
VCC_LAN1_05_INT_ICH_2 G18

VCCLAN1_05[1]
VCCLAN1_05[2]

12mA
1

R257
1
+1.5VS

10U_0805_10V4Z

CHB1608U301_0603
27mA
ICH_VCCGLANPLL
2
@ R258
74mA
2ICH_VCCGLAN1_5
1
1 +1.5VS 1
CHB1608U301_0603
1
C308
C309
@ C310
2
2
4.7U_0805_10V4Z
1mA
2
1
2ICH_VCCGLAN3_3
+3VS
@ R2590_0402_5%

VCCLAN3_3[1]
VCCLAN3_3[2]

A24

VCCGLANPLL

A26
A27
B26
B27
B28

VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
VCCGLAN1_5[5]

B25

VCCGLAN3_3

GLAN POWER

2.2U_0805_16V4Z

C307
0.1U_0402_16V4Z

F19
G20

0.1U_0402_16V4Z +3VS
(SATA)
1
+3VS

AC8
AD8
AE8
AF8

VCC3_3[07]
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]

AA3
U7
V7
W1
W6
W7
Y7

VCC3_3[14]
VCC3_3[15]
VCC3_3[16]
VCC3_3[17]
VCC3_3[18]
VCC3_3[19]
VCC3_3[20]
VCC3_3[21]
VCC3_3[22]
VCC3_3[23]
VCC3_3[24]

A8
B15
B18
B4
B9
C15
D13
D5
E10
E7
F11

VCC3_3=310mA
0.1U_0402_16V4Z
1

C292

+3VS

VCC3_3=310mA
1

24mA

VCCHDA

AC12

VCCSUSHDA

AD11

VCCSUS1_05[1]
VCCSUS1_05[2]

J6
AF20

0.1U_0402_16V4Z

4mA

VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
VCCSUS3_3[05]
VCCSUS3_3[06]

AC18
AC21
AC22
AG20
AH28

VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]

P6
P7
C1
N7
P1
P2
P3
P4
P5
R1
R3
R5
R6

VCCCL3_3[1]
VCCCL3_3[2]

F20
G21

C299
2

2
+3VALW

VCCSUS3_3=141mA

+3VALW

VCCSUS3_3=141mA
1

G22 VCCCL1_05_ICH
A22

+3VALW

C301

VCCCL1_5

+3VS
1

0.1U_0402_16V4Z
1

T32
T33
AC16 VCCSUS1_5_ICH_1
T34
VCCSUS1_5_ICH_2
J7
T35
C3 0.1U_0402_16V4Z

VCCCL1_05

+3VS

(DMI)

C289

VCC3_3=310mA

C303

VCCUSBPLL

USB CORE

C304
0.1U_0402_16V4Z

D1

0.1U_0402_16V4Z +3VS
1

VCC3_3=310mA

C302

10mA

+VCCP

VCC3_3=310mA

VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]

VCCSUS1_5[2]

VCC1_5_A[18]
VCC1_5_A[19]

VCC1_5_A=1120mA

+1.5VS

VCC3_3[02]

AD2

VCCSUS1_5[1]

AC7
AD7
+1.5VS

AF29

0.1U_0402_16V4Z

AC10
AC9

VCC3_3[01]

14mA

C295

VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]

AC23
AC24

C294

VCCSATAPLL

VCC_DMI[1]
VCC_DMI[2]

C293
0.1U_0402_16V4Z

AJ6
AE7
AF7
AG7
AH7
AJ7

VCC1_5_A=1120mA
+1.5VS

+1.25VS

0.1U_0402_16V4Z
0.1U_0402_16V4Z

1U_0603_10V4Z

ICH_VCCSATAPLL

ATX

CHB1608U301_0603

ARX

+1.5VS

50mA

2
10U_0805_10V4Z

C288

0.1U_0402_16V4Z

2
0.01U_0402_16V7K

40mA

V_CPU_IO[1]
V_CPU_IO[2]

CHB1608U301_0603
2
+1.5VS

1
C283

0.1U_0402_16V4Z
C287

C291

1
C282

C286

20 mils
1

R29
AE28
AE29

R253
1

ICH_VCCDMIPLL

26mA

VCCDMIPLL

0.1U_0402_16V4Z

0.1U_0402_16V4Z

ICH_V5REF_SUS

4.7U_0805_10V4Z

CH751H-40PT_SOD323-2

C277

C285

D12

R255
C

VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]

VCCA3GP

+5VALW +3VALW

10_0402_5%

V5REF_SUS

C276

10U_0805_10V4Z

G4
AA25
AA26
AA27
AB27
AB28
AB29
D28
D29
E25
E26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
U25
V23
V24
V25
W25
Y25

C278
220U_6.3V_M

+5VS

40 mils

ICH_V5REF_SUS
10U_0805_10V4ZICH_VCC1_5 770mA

CORE

+1.5VS

CHB1608U301_0603
2
1

VCCP_CORE

R252
1

A13
B13
C13
C14
D14
E14
F14
G14
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18

C290

V5REF[1]
V5REF[2]

VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
VCC1_05[27]
VCC1_05[28]

C306

VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]

4.7U_0805_10V4Z

VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]

K7
L1
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AB6
AD5
U4
W24

VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]

A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29

ICH8M REV 1.0

T38

1U_0603_10V4Z 1

12mA

+3VS

2 @

ICH8M REV 1.0

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

A23
A5
AA2
AA7
A25
AB1
AB24
AC11
AC14
AC25
AC26
AC27
AD17
AD20
AD28
AD29
AD3
AD4
AD6
AE1
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
J27
J4
J5
K23
K28
K29
K3
K6

C311

VCCRTC

A16
T7

3mA
D

0.1U_0402_16V4Z

U7F
AD25

6mA
ICH_V5REF_RUN

IDE

PCI

20 mils

VCCPSUS

VCCPUSB

C275
0.1U_0402_16V4Z

C274
0.1U_0402_16V4Z

+RTCVCC

Title

Compal Electronics, Inc.

ICH8(4/4)_POWER&GND

Size Document Number

Custom LA-3732P
Date:

Rev
0.2

Wednesday, March 14, 2007

Sheet
1

21

of

40

+5VS

Placea caps. near ODD CONN.

HDD Connector

CD-ROM Connector

C319

C320
0.1U_0402_16V4Z

C317
10U_0805_10V4Z

2
0.1U_0402_16V4Z

2
2
0.1U_0402_16V4Z

Pleace near HD CONN (JP23)

0.1U_0402_16V4Z
1
@ C323

@ C324

1
1

+
@ C325

2
2
2
2
1000P_0402_50V7K 1U_0603_10V4Z

SATA_TXP0 <19>
SATA_TXN0 <19>

1 C316 SATA_RXN0_C
1 C321 SATA_RXP0_C

<7,18> PLT_RST#

SATA_RXN0_C <19>
SATA_RXP0_C <19>

Near CONN side.

V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
V12

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

GND
GND

23
24

+3VS_HDD

+5VS
+5VS

IDE_HDIOW#
IDE_ HIORDY
IDE_HIRQ
IDE_HDA1
IDE_HDA0
IDE_HDCS1#
IDE_ACT#

<19> IDE_HDIOW#
<19> IDE_HIORDY
<19> IDE_HIRQ
<19> IDE_HDA1
<19> IDE_HDA0
<19> IDE_HDCS1#
2
1
R264 10K_0402_5%
+5VS

SEC_CSEL

54

IDE_HDD8
IDE_HDD9
IDE_HDD10
IDE_HDD11
IDE_HDD12
IDE_HDD13
IDE_HDD14
IDE_HDD15
IDE_HDREQ
IDE_HDIOR#
IDE_HDACK#
PDIAG# R262 1
IDE_HDA2
IDE_HDCS3#

C315
10U_0805_10V4Z
1

IDE_HDREQ <19>
IDE_HDIOR# <19>
IDE_HDACK# <19>
100K_0402_5%
2
IDE_HDA2 <19>
IDE_HDCS3# <19>

+5VS

+5VS

+3VS_HDD
C322
330U_V_2.5VK_R9

+3VS
@ R2630_0805_5%
2
1

SATA_TXP0
SATA_TXN0
0.01U_0402_16V7K
SATA_RXN0
2
SATA_RXP0
2
0.01U_0402_16V7K

1
C314

C318
2

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

10U_0805_10V4Z

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

C313

<20> IDE_RESET#

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50

1U_0603_10V4Z

1
2
3
4
5
6
7

JP10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49

0.1U_0402_16V4Z

GND
A+
AGND
BB+
GND

@ R260 0_0402_5%
1
2
R261
33_0402_5%
1
2
IDE_HDD7
IDE_HDD6
IDE_HDD5
IDE_HDD4
IDE_HDD3
IDE_HDD2
IDE_HDD1
IDE_HDD0

C312

0213_Change Connector type.

IDE_HDD[0..15] <19>
JP9
+5VS

Pleace near HD CONN

R265
470_0402_5%

53

SUYIN_800194MR050S102ZU
CONN@
DC030001P00 WAFER OCTEK CDR-50JD1 50P P0.822P SATA
OCTEK_CDR-50JD1_50P

CONN@
SUYIN_127043FR022G204ZL_NR
DC010003M00 HOUSING SUYIN 127043FR022G204ZL 22P SATA
SUYIN_127043FR022G204ZL_22P_NR

Mini-Express Card---WLAN
+3VS_MINI

C326 1
0.01U_0402_16V7K

C327
0.1U_0402_16V4Z

C328

+1.5VS_MINI

C329
0.01U_0402_16V7K

4.7U_0805_10V4Z 2

C330
0.1U_0402_16V4Z

+3VALW

C331
4.7U_0805_10V4Z

C332
@ 0.1U_0402_16V4Z

+1.5VS_MINI

+3VS_MINI

+3VS
+1.5VS

JP11
ICH_PCIE_WAKE#

<20> ICH_PCIE_WAKE#
<15> MINI_CLKREQ#
<15> CLK_PCIE_MCARD#
<15> CLK_PCIE_MCARD

1
2 MINI_CLKREQ#_MC
R266
0_0402_5%
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
PLT_RST#

<15,29,30> CLK_DEBUG_PORT
<20> PCIE_RXN1
<20> PCIE_RXP1
<20> PCIE_TXN1
<20> PCIE_TXP1

PCIE_RXN1
PCIE_RXP1

1
2
R272
DEBUG@ 0_0402_5%
R273 0_0402_5%
PCIE_C_RXN1
1
2
PCIE_C_RXP1
1
2
R274
0_0402_5%

PCIE_TXN1
PCIE_TXP1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

53

GND1

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

GND2

54

1
R267
R268
R269
R270
R271

L12
FBMA-L11-201209-102LMA10T
1
2
2
L13
FBMA-L11-201209-102LMA10T
DEBUG@
0_0402_5%
1
2
1
2 DEBUG@ 0_0402_5%
1
2 DEBUG@ 0_0402_5%
1
2 DEBUG@ 0_0402_5%
1
2 DEBUG@ 0_0402_5%

WL_ON#
PLT_RST#

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME# <19,29,30>

LPC_AD[0..3] <19,29,30>
WL_ON#

<20>

+3VALW
ICH_SMBCLK <15,20>
ICH_SMBDATA <15,20>

WL_LED#

WL_LED# <28>

FOX_AS0B226-S40N-7F~D

Mini Card STANDOFF

H19
HOLEA

SP01000P700 S H-CONN ACES 88914-5204 52P P0.8

H20
HOLEA

Issued Date

2006/02/13

2007/08/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

EC029000100 MINICARD_STANDOFF_8

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

HDD/ODD/Mini Card CONN.

Size

Document Number

Rev
0.2

LA-3732P
Date:

Wednesday, March 14, 2007

G

Sheet

22
H

of

40

+3VALW
JP12
R275
300_0603_5%
1
2

ACTIVITY#

11

Yellow LED+

12

Yellow LED-

RX2-

RX2+

RX1-

TX2-

TX2+

MDO1+

RX1+

MDO0-

TX1-

MDO0+

TX1+

MDO1-

PCI_AD[0..31]

<18> PCI_AD[0..31]

R276
3.6K_0402_5%
1
2
U8

1
R285

<18> PCI_PERR#
<18> PCI_SERR#
<18> PCI_REQ0#
<18> PCI_GNT0#
B

<18> PCI_PIRQA#
<18,30> PCI_PME#
<18,29,30> PCI_RST#
<15> CLK_PCI_LAN

C/BE#0
C/BE#1
C/BE#2
C/BE#3

LAN_IDSEL
100_0402_5%
PCI_PAR
PCI_FRAME#
PCI _IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#

46

IDSEL

76
61
63
67
68
69

PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

PCI_PERR#
PCI_SERR#

70
75

PERR#
SERR#

PCI_REQ0#
PCI_GNT0#

30
29

REQ#
GNT#

25

INTA#

PCI_PME#

31

PME#

PCI_RST#

27

CLK_PCI_LAN 28
65
1
2
R289
10K_0402_5%

1
2

@ R292
10_0402_5%

@ C356
10P_0402_50V8J

2
A

21
38
51
66
81
91
101
119

C333

1
2
5
6

0.1U_0402_16V4Z
LINK_100#

+3VALW
2
ACTIVITY# 1
2
C334 680P_0402_50V7K
LINK_100# 1
2
C335 680P_0402_50V7K

TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1-

For EMI,
locate close
to LAN chip

R277
300_0603_5%
1
2

Green LED-

Green LED+

NC/M66EN

88

NC/AVDDH
NC/HV

10
120

NC/HSDAC+
NC/HG
NC/LG2
NC/LV2

11
123
124
126

2 1K_0402_5%
2 15K_0402_5%
2 5.6K_0603_1%

1
1
1

TIP

13

RI NG

14

RJ11_1
RJ11_2

9
13

NC/GND
NC/GND
NC/GND
NC/GND
NC/GND
NC/GND

22
48
62
73
112
118

U10
TXD+/MDI0+
TXD-/MDI0-

C337 27P_0402_50V8J
1
2

C339
0.1U_0402_16V4Z
1
2
RXIN+/MDI1+
RXIN-/MDI1-

+3VS

8
7
6

TDTD+
CT

3
2
1

CT
RDRD+

TXTX+
CT
CT
RXRX+

9
10
11

MDO0+
MDO0MCT0

14
15
16

MCT1
MDO1+
MDO1-

R280
75_0402_5%
2
1

C340
1U_0603_10V4Z
1
2
Q10
CTRL25

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33

26
41
56
71
84
94
107

2
1
R284
75_0402_5%

TXD+/MDI0+
2SB1188T100R_SC62-3
V2.5_LAN
+3VA_LAN

C342 4.7U_0805_10V4Z
1
2

1
C343
0.1U_0402_16V4Z

1
C344
0.1U_0402_16V4Z

1
C345
0.1U_0402_16V4Z

R288
2
1
0_0603_5%

1
C346
0.1U_0402_16V4Z

+3VALW

RXIN+/MDI1+

3
7
20
16

2
32
54
78
99

NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18
NC/VDD18

1
C349
0.1U_0402_16V4Z

R286
49.9_0402_1%
2
1

C341
0.01U_0402_16V7K
2
1

2
1
R287
49.9_0402_1%

close to magnetic

C347
0.1U_0402_16V4Z

RXIN-/MDI1-

VDD25/VDD18
VDD25/VDD18
VDD25/VDD18
VDD25/VDD18

1000P_1206_2KV7K

close to chip

8
125

AVDD33/AVDDL
AVDD33/AVDDL
AVDD33/AVDDL
NC/AVDDL

C338
RJ45_GND 2

+3VALW

RTT3/CRTL18

GND/VSS
GND/VSS
GND/VSS

RJ11

CONN@ JM34F2-M5125-7F

TXD-/MDI0-

CLK
CLKRUN#

16

NS0013_16P

NC/VSS
NC/VSS

RST#

GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST
GND/VSSPST

R281
R282
R283

15

SGND2

JM34F2*-N5125-7F
JM34F2A-M5125-7F

LWAKE
ISOLATE#
RTSET
NC/SMBCLK
NC/SMBDATA

105
23
127
72
74

LAN_X1
LAN_X2

SGND1

RJ45 / LED

Y3
25MHZ_20P_1BG25000CK1A

121
122

AVDD25/HSDAC-

R290
49.9_0402_1%
2
1

C348
0.01U_0402_16V7K
2
1

2
1
R291
49.9_0402_1%

1
C350
0.1U_0402_16V4Z

C351
0.1U_0402_16V4Z

0310_Dammy by safty request.

Footprint can not match part number.
V2.5_LAN

1
C352
0.1U_0402_16V4Z

V_12P
1
C359

12

1
C353
0.1U_0402_16V4Z

1
C354
0.1U_0402_16V4Z

SP020008Y00 S W-CONN ACES 88266-02001 2P P1.25

ACES_88266-02001_2P

C355
0.1U_0402_16V4Z

JP13
RI NG
TIP

24
45
64
110
116

RTL8100CL_LQFP128

R293
0_0402_5%
1
2

C357
V2.5_LAN

1
2

1
2

3
4

G1
G2

RJ11

C358
@

ACES_88266-02001
CONN@

0.1U_0402_16V4Z

Compal Secret Data

2006/02/13

Issued Date

2007/08/29

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

220P_1808_3KV
@ 220P_1808_3KV

Security Classification

10

+3VALW

C336 27P_0402_50V8J
1
2

14
15
18
19

X1
X2

CTRL25

GND
GND
GND
GND

GND
NC
NC
VCC

ACTIVITY#_R1
AT93C46-10SU-2.7_SO8
2
R278 0_0603_5%
LINK_100#_R1
2
R279 0_0603_5%

2
35
52
80
100

DO
DI
SK
CS

5
6
7
8

92
77
60
44

4
17
128

CLK_PCI_LAN

NC/MDI2+
NC/MDI2NC/MDI3+
NC/MDI3-

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_PIRQA#

117
115
114
113

4
3
2
1

PCI_AD17

<18>
PCI_PAR
<18> PCI_FRAME#
<18> PCI_IRDY#
<18> PCI_TRDY#
<18> PCI_DEVSEL#
<18> PCI_STOP#

LED0
LED1
LED2
NC/LED3

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

EEDO
AUX/EEDI
EESK
EECS

108
109
111
106

TXD+/MDI0+
TXD-/MDI0RXIN+/MDI1+
RXIN-/MDI1-

LAN I/F

<18>
<18>
<18>
<18>

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

U9

Power

104
103
102
98
97
96
95
93
90
89
87
86
85
83
82
79
59
58
57
55
53
50
49
47
43
42
40
39
37
36
34
33

PCI I/F

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

+3VA_LAN

Title

Compal Electronics, Inc.

LAN-8100CL

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

23

of

40

AUDIO CODEC

CODEC POWER

0308_Change R294 and R295 from 0 ohm to bead, C363 from 10uF to 680pF, C365 and C368 from 0.1uF to 680p

0212_Change to +5VALW.
For Layout:
Place decoupling caps near the
power pins of SmartAMC
device.

<20>

SB_SPKR

EAPD

+3VDD_CODEC
RCOSC
1
237K_0402_1%

11

PCBEEP

48

SPDIF

47

EAPD

1
2
16

NC_1
NC_2
NC_16

41

RCOSC

42
46

2
R311

C361
0.1U_0402_16V4Z
1

DIBN

T39

APE8805A-33Y5P_SOT23-5
C362
0.1U_0402_16V4Z
SUSP#.

35
36

LINE_OUTL
LINE_OUTR

PORT-A_BIAS_L
PORT-A_BIAS_R
PORT-A_L
PORT-A_R

33
34
38
39

HP_OUTL
HP_OUTR

PORT-B_BIAS_L
PORT-B_BIAS_R
PORT-B_L
PORT-B_R

14
15
23
24

CD_L
CD_GND
CD_R

17
18
19

SENSE

13

VREF_HI
VREF_LO
VC_REFA

26
27
28

LINEOUT_L
LINEOUT_R

+CODEC_REFF_INR
MIC_INL
C371 1
2 10U_0805_10V4Z
MIC_INR
C372 1
2 10U_0805_10V4Z

DIGITAL

LINE_OUTL <26>
LINE_OUTR <26>

MIC_IN_R <26>

+CODEC_REFF_EXTR

R303
2.2K_0402_5%

HP_OUTL <26>
HP_OUTR <26>

+CODEC_REFF_EXTL
+CODEC_REFF_EXTR
MIC_EXTL
C375 1
2 10U_0805_10V4Z
MIC_EXTR
C376 1
2 10U_0805_10V4Z
1
R307
1
R309
SENSE
1
For Vista R310
1
R337

2
20K_0402_1%
2
5.1K_0402_1%
2
5.1K_0402_1%
2
10K_0402_1%

+CODEC_REFF_EXTL

DIB_N

MIC_BIAS_L
MIC_BIAS_R
MIC_L
MIC_R

DIBP

R305 0_0402_5%
1
2 D IBN_C 43

AVDD_20
AVDD_31
AVDDHP

BIT_CLK
SYNC
SDI
SDO

R301 0_0402_5%
1
2 DIBP_C 44

C373
1U_0603_10V4Z
MONO_IN1
1
2 MONO_INR
@ R306
1 5.1K_0402_5%
2

R304
2.2K_0402_5%
2

R302
0_0402_5%
SB_SPKR
1
2

RESET#

5
9
7
4

0216_Change value.

<25>

0208_Change SLP_S3# to

BP

(3.33V)
250mA

R296
2.2K_0402_5%

MIC_EXT_L <26>
MIC_EXT_R <26>
+3VAMP_CODEC

HP_DET# <26>

EXTMIC_DET# <26>

VREF_HI
VREF_LO
VC_REFA

AVSS_12
AVSS_25
AVSS_32
AVSSHP

+VDDA_CODEC

SHDN#

OUT

29
30
21
22

12
25
32
40

C374
33P_0402_50V8K

<25>

<30,31,33,35,36> SUSP#

+3VAMP_CODEC
R295
2
1
MBV2012301YZF_0805
1
1

+VDDA_CODEC

U11

1
1
2
C360 0.1U_0402_16V4Z VIN
2 GND

20
31
37

8
45

VDDIO
1
1

33_0402_5%
2

DIB_P

R300
47_0402_5%

R299
1

<19> ACZ_SYNC
<19> ACZ_SDIN0
<19> ACZ_SDOUT

10

VSSIO_42
VSSIO_46

<19,30> ACZ_RST#
<19> ACZ_BITCLK

+5VALW

W=40Mil

+CODEC_REFF_INR
U12

ACZ_RST#

C369
0.1U_0402_16V4Z

DVSS

DVDD
DVDDM

C366
0.1U_0402_16V4Z

C364
1U_0603_10V4Z

C363
680P_0402_50V7K

2
1
MBV2012301YZF_0805

C365
680P_0402_50V7K

R294
+3VS

C368
680P_0402_50V7K

+3VDD_CODEC
C367
@ 0.1U_0402_16V4Z

C370
1U_0603_10V4Z

In order for the modem wake on ring feature to function,

the CODEC must be powered by a rail that is not
removed when the system is in standby.

CX20549-12Z_LQFP48_9X9

C378 C377 1U_0603_10V4Z

1U_0603_10V4Z

ANALOG

C379
0.1U_0402_16V4Z
1
2
C380
0.1U_0402_16V4Z
1
2
C381
0.1U_0402_16V4Z
1
2
C382
0_0402_5%
1
2
C383
0.1U_0402_16V4Z
1
2
R312
0_1206_5%
1
2
R313
0_1206_5%
1
2

HP_DET#

MIC_DET

0(LOW)

0(LOW)
NC

0(LOW)
GNDA

NC

<26>

0(LOW)

NC
GND

LINEOUT

NC

PORT-A
<Earphone OUT>

MIC

EQ

OFF

ON

ON

Disable

OFF

ON

OFF

Disable

ON

OFF

ON

Enable

ON

OFF

OFF

Enable

GNDA

0312_Mount C379~383, R313.

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/03/10

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMOM_codec

Size Document Number

Custom LA-3732P
Date:

Rev
0.2
Sheet

Wednesday, March 14, 2007

E

24

of

40

5335R13-005

RAC1_RING
MU1
CX20548

RING_1

MFB2

MMBD3004S
MBR1

MR3

12

TAC

6.81M

RAC1

AGND_LSD

TEST
MR1

DIBN

EIC

2
1

ML1
@ Optional

6.81M
MBR2
MMBD3004S

11

EIC

MC11

@ MJ1

5335R13-005

TIP_1

0.1uF
cap_0402_01uf

MC8
470 pF
MC10

PWR+

15

MC7
@ Omit

MC9
470 pF

Note: MC8 and MC9 can be optionally

populated here or behind the RJ-11
connector.

AGND_LSD
GND

DIB_P
DIB_N

AVdd
MC5
0.1uF
cap_0402_01uf

MC12
150pF
MT1
CAP_0402_150PF
2

@ MJ4
DIBN_HS
DIBP_HS

2
1

MC6
47P_0402_50V8J
CAP_0402_47PF

1
4
MODEM-SMAR

MR2

AVDD

RXI

RXI

MC3
0.1uF
cap_0402_01uf

GND

RX1_1

MC1

BRIDGE_CC

0.047uF
100.0V

237K
MR9
MR5
MR6
MR10
280
280
280
280
RES_1206_280RES_1206_280
RES_1206_280 RES_1206_280
BRIDGE_CC2

AGND_LSD
DIBP

14

DIBP

EIO

MR13

10

100_0402_5%

MQ1
MMBTA42

RES_0402_100

MC13

QBASE
150pF
CAP_0402_150PF

EIF
DVdd

GND

DVDD

MC4
0.1uF
cap_0402_01uf

TXO

TXF

TXF

MQ2
MMBTA42

13

EP

MR4
110
5%

Description

MQ3
MMBTA42

MQ4
MMBTA42

MR11
3.01
res_0402_301

MR12
3.01
res_0402_301

MR7
9.1
res_1206_91

AGND_LSD

MC2
0.1uF
cap_0402_01uf

Revision History

8
7

MR8
56
5%
@ RES_0603_56

VC_LSD

GND

REV

TXO

GPIO

AGND_LSD

EIF

17

1
2

VC

@ MJ5
B

@ MJ3

0.01uF
cap_0603_001uf

R810 and C810 must be placed near pin 6 (RXI)

and there should be no vias on the(RXI)net.

PWR

2
1

MFB1

AGND_LSD

<24>
<24>

@ MJ2

2
1

TAC1_TIP

16

TAC1
res_0805_681m

DIBN

MRV1

RAC

Date

Initial Release

April 26, 2005

No changes to schematic. PCB updated to -003.

Updated footprints and corrected via spacing errors.

August 18, 2005

Changed MC8 and MC9 pads.

PCB updated to -005.

Added MR11 and MR12.

Added MR13.

4.01

AVL update only.

No schematic changes.

PCB updated to -007.

PCB updated to -009.

AGND_LSD

November 3, 2005

November 18, 2005

Compal Secret Data

Security Classification
Issued Date

January 3, 2006

2006/02/13

Deciphered Date

2007/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

April 20, 2006

Title

Compal Electronics, Inc.

AMOM-CX20548

Size

Document Number

R ev
0.2

LA-3732P
Date:

W ednesday, March 14, 2007

Sheet
1

25

of

40

+5VAMP

R314
0_1206_5%
1
2

0.1U_0402_16V4Z

+5VS

10 dB

ROUT+

18

SPKR+

ROUT-

14

SPKR-

LOUT+

SPKL+

LOUT-

SPKL-

RIN-

GAIN1

LINE_C_OUTR 17

GAIN0

RIN+

@ R316
100K_0402_5%

2 0.47U_0603_10V7K

R315
100K_0402_5%

VDD
PVDD1
PVDD2
C393 1

<24> LINE_OUTR

2 0.47U_0603_10V7K

16
15
6

+5VS

@ R318
100K_0402_5%

C390
47P_0402_50V8J

C389
47P_0402_50V8J

0.1U_0402_16V4Z

C391 1

1
2
3
4

C386

U13

JP15

SPKL+
SPKLSPKR+
SPKR-

C385

SPEAKER

SP02000D000 S W-CONN ACES 85204-04001 4P P1.25

C388
47P_0402_50V8J

C384
10U_0805_10V4Z

C387
47P_0402_50V8J

E&T_3801-04
CONN@

1
1

@ C394 47P_0402_50V8J
2
1

R319
100K_0402_5%

1
2
3
4

MIC INT In-R

LINE_C_OUTL

LIN-

19

NC

12

BYPASS

10

1
2
G1
G2
ACES_85204-02001
CONN@

MIC EXT In
Keep 10 mil width

SHUTDOWN

EXTMIC_DET#

<24> EXTMIC_DET#

CONN@
SUYIN_010030FR006G105ZR

GND5
GND1
GND2
GND3
GND4

<30> EC_MUTE#

EC_MUTE#

LIN+

1
2
3
4

C397
0.47U_0603_10V7K

6
5

@ C398 47P_0402_50V8J
2
1

21
20
13
11
1

P3017THF D0 TSSOP 20P

0310_Change to ENE AMP.

<24>

MIC_EXT_L

<24>

MIC_EXT_R

MIC_EXT_L
MIC_EXT_R

R321
2

0_0603_5%
1

2
R322

1
0_0603_5%

4
MICEXT_L

MICEXT_R

2
1
JP16

2
1
@ C399 47P_0402_50V8J

B+

2 0.47U_0603_10V7K

MICIN_R

2
1
R320 0_0603_5%

MIC_IN_R

C396 1

<24> LINE_OUTL

2 0.47U_0603_10V7K

JP28
C395 1

<24>

B+

R323

330K_0402_5%
D

EC_MUTE#

Q12
2N7002_SOT23-3

2
G

@ D13
SM05_SOT23

R324

330K_0402_5%

HeadPhone Out/Line Out

HP_OUT_R

Q14
HP_OUTR+
3 2N7002_SOT23-3

HP_OUTL+

Q15
HP_OUTL+
3 2N7002_SOT23-3

HP_OUT_L

0_0603_5%
1

2
R326

1
0_0603_5%

4
PR

PL

2
1
3

JP17

2
1
@C404 47P_0402_50V8J

R328
1K_0402_5%

R327
1K_0402_5%

2
G

C403

2 100U_6.3V_M

R325
2

<24> HP_OUTL

6
5

@ C401 47P_0402_50V8J
2
1

HP_OUTR+
HP_OUTL

CONN@
SUYIN_010030FR006G105ZR

HP_DET#

<24> HP_DET#

Q13
2N7002_SOT23-3

2
G

C402
2 100U_6.3V_M

2
G

<24> HP_OUTR

HP_OUTR

cap. high 5.7mm

@ D14
SM05_SOT23

0302_Change Audio Jack.

Q16
2
G
2N7002_SOT23-3
D

Q17
2
2N7002_SOT23-3
G

Compal Secret Data

Security Classification
2006/02/13

Issued Date

Deciphered Date

2007/08/29

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

AMP & Audio Jack

Size

Document Number

Rev
0.2

LA-3732P
Date:

Wednesday, March 14, 2007

Sheet
E

26

of

40

0228_Add JP29 for USB card reader.

JP29
1
3
5
7
9
11

<20> USB20_P4
<20> USB20_N4

USB Port
+5VALW
+USB_VCCA
U14

SYSON#

GND
IN
IN
EN#

OUT
OUT
OUT
FLG

8
7
6
5

2
4
6
8
10
12

+3VS

ACES_88020-12101
CONN@

13
14
15
16
17
18

1
2
3
4

2
4
6
8
10
12
GND
GND
GND
GND
GND
GND

+5VALW
+5VS

1
3
5
7
9
11

USB_OC#2

USB_OC#2 <20>

G528P1UF_SO8

+USB_VCCA
C406
220U_6.3V_M

0308_Change connector type.

1
+

C407

+5VALW

C408
C

1000P_0402_50V7K
JP18
JP19

0.1U_0402_16V4Z

USB20_N2
USB20_P2
2

<20>
<20>

@D15
PSOT24C_SOT23-3

1
2
3
4
5
6
7
8

1
2
3
4
GND
GND
GND
GND

<20>
<20>

SUYIN_020133MB004S580ZL-C
CONN@

1
2
3
4
5
6
7
8
9
10

USB20_N0
USB20_P0

<20>
USB20_N1
<20>
USB20_P1
<20>
USB_OC#0
<31,35> SYSON#

SYSON#

11
12

DC233000U00 CONN SUYIN 020173MR004S558ZL 4P USB

SUYIN_020173MR004S558ZL_4P

1
2
3
4
5
6
7
8
9
10

GND1
GND2
ACES_87213-1000G
CONN@

SP02000DX00 S W-CONN ACES 87213-1000G 10P P1.0

ACES_87213-1000G_10P

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

USB CONN.

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

27

of

40

POWER LED(Left 1)
BLUE

M/BtoS/B

+5VALW

D16
ON/OFFBTN_LED# 1

0301_Change Voltage from 3V to 5V.

+5VALW

1
2
3
4
5
6
7
8
9
10
11
12

ON/OFFBTN#
WL_BTN#
ON/OFFBTN_LED#
WL_LED#
LID_SW#

<30> LID_SW#

+3VALW

D18
<30>

HDD LED(Left 3)
+5VS

BLUE

ON/OFF <30>

51ON#

51ON#

2 2

AMBER

+5VS

BLUE

+5VS

D21
Blue

R336
10K_0402_5%
2

<29,30> CAPS_LED#

LTST-C195TBKFKT_BLUE/ORG

1
2
G1
G2

Orange

JP21
1
2
3
4

EC_ON

EC_ON

R335
200_0402_5%
4 2

G
3

R334
820_0402_5%

M/B to SB(Caps Lock LED)

2 C409
1000P_0402_50V7K

+5VS

R332
4.7K_0402_5%

<30>

2
470_0402_5%

Wireless ON/OFF LED(Left 4)

1

+3VALW

0208_Change Voltage from 3V to 5V.

0216_Delete D19.
C

<34>

Q18
DTC124EK_SC59

R333

<19> SATA_LED#

LTST-C191TBKT-5A_BLUE_0603~D
ON/OFF

2
470_0402_5%

D20

3
DAN202U_SC70

LTST-C191TBKT-5A_BLUE_0603~D

SP01000H400 S H-CONN ACES 85201-1005N 10P P1.0

ACES_85201-1005N_10P

2
1

ON/OFFBTN#

R331

BAT_LED#

+5VALW

BLUE

ACES_85201-1005N
CONN@

4.7K_0402_5%

Battery Charge LED(Left 2)

1
2
3
4
5
6
7
8
9
10
GND
GND

R330

D17

470_0402_5%
JP20

Power ON/OFF

LTST-C191TBKT-5A_BLUE_0603~D

+5VS

<29,30> NUM_LED#
<30> WL_BTN#
<29,30> ON/OFFBTN_LED#

R329

Q19
WL_LED#_LIGHT
2
2N7002_SOT23-3
G

ACES_85204-02001
CONN@
3

S
SP02000D000 S W-CONN ACES 85204-02001 2P P1.25
ACES_85204-02001_2P

1
WL_LED#

<22> WL_LED#

On (WL_ON#=L)-> Blue
Off (WL_ON#=H)-> Amber

Q20
2N7002_SOT23-3

2
G

0208_Change R329, R331, R333 to 470 ohm, R334 and R339 to 820 ohm, R335 and R338 to 200 ohm.

TP_DATA
TP_CLK

TP_BTN# <30>

1
2
3
4
G1
G2

On (TP_LED#=L)-> Blue
Off (TP_LED#=H)-> Amber
D

TP_LED#
Q22
2
2N7002_SOT23-3
G

TP_LED#

0.1U_0402_16V4Z

1
2
3
4
5
6

TP_CLK <30>
TP_DATA <30>

ACES_85201-0405N
CONN@
@C413
100P_0402_50V8J

JP22

SN100000F00 S TACT SW SMT1-05-A SPST HCH H1.5 4P

SW_SMT1-05-A_4P

<30>

TP_BTN#

5
6

Orange

Blue
1

TP_LED#_LIGHT

Q21
2N7002_SOT23-3
2
G

LTST-C195TBKFKT_BLUE/ORG

R384
10K_0402_5%

EMI request

1
@ C412

SW1
SMT1-05-A_4P

D23

R341
10K_0402_5%
2

2
4

2
2

AMBER

BLUE

R340
10K_0402_5%

R339
820_0402_5%

+5V

Q33
SI2301BDS-T1-E3_SOT23-3

D24
PSOT24C_SOT23-3
@

R338
200_0402_5%

+5VS

+5VALW

+5V

+5V

T/P Board

TP ON/OFF

SYSON

<30,31,35> SYSON

TouchPAD ON/OFF LED

+5VS

D21, D25, D23 Footprint can not match part number.

0208_Delete reserve component (D25SW2) for 14.1".

Q34
2N7002_SOT23-3

2
G

@C414
100P_0402_50V8J

SP01000H300 S H-CONN ACES 85201-0405N 4P P1.0

ACES_85201-0405N_4P

0226_Change package from 0603 to 0402.

A

Compal Secret Data

Security Classification
2006/02/13

Issued Date

Deciphered Date

2006/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

LED/SW

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

28

of

40

+3VALW
1

+3VALW

1
R342
100K_0402_5%

U16
8
7
6
5

<30,38> SMB_EC_CK1
<30,38> SMB_EC_DA1

C415
0.1U_0402_16V4Z

VCC
WP
SCL
SDA

A0
A1
A2
GND

1
2
3
4

LPC Debug Port

1

AT24C16AN-10SI-2.7_SO8

Change from +3VL to +3VS. 6/9

Removed +3VS. 6/13

R343
100K_0402_5%

B+

JP23
<15,22,30> CLK_DEBUG_PORT

SPI ROM

<19,22,30> LPC_FRAME#
<18,23,30> PCI_RST#

+3VALW

<19,22,30>
<19,22,30>
<19,22,30>
<19,22,30>

U17
20mils
C416
0.1U_0402_16V4Z

2
<30>

FSEL#

<30>

SPI_CLK

<30>

FWR#

1
R345
1
R346
FWR# 1
R347

VCC

HOLD

SPI_FSEL#
2
0_0402_5%
SPI_CLK_R
2
0_0402_5%
SPI_FWR#
2
0_0402_5%

VSS

SPI_SO 1
2FR D#
D
Q 2
R348
0_0402_5%
CONN@ WIESON G6179 8P SPI
SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH
WIESO_G6179-100000_8P
5

FRD#

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
ON/OFFBTNLED#
CAPSLED#
NUMLED#
VCC1PWRGD
SPI_CLK_JP52
SPI_CS#_JP52
SPI_SI_JP52
SPI_SO_JP52
SPI_HOLD#_0

<30>

&U1

Connect pin3 & 23

together and pin 24
to GND in 6/29.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved
ACES_87216-2404_24P
@

45level
45@

SST25LF080B_SO8-200mil

+3VALW

SPI_CLK

@ R349
1

0_0402_5%
2

SPI_CLK_JP52

FSEL#

@ R350
1

0_0402_5%
2

SPI_CS#_JP52

FWR#

@ R351
1

0_0402_5%
2

@ R352
1

0_0402_5%
2

@ R353
1

0_0402_5%
2

HOLD#
FR D#

<28,30> ON/OFFBTN_LED#

<28,30> CAPS_LED#

@ R222
1

0_0402_5%
2

<28,30> NUM_LED#

@ R356
1

0_0402_5%
2

<30> VCC1_PWRGD

@ R357
1

0_0402_5%
2

@ R399

0_0402_5%

SPI_SO_JP52
ON/OFFBTNLED#
CAPSLED#
NUMLED#
VCC1PWRGD

Compal Secret Data

Security Classification
Issued Date

SPI_SI_JP52
SPI_HOLD#_0

2006/02/13

Deciphered Date

2006/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

BIOS ROM

Size

Document Number

Rev
0.2

LA-3732P
Date:

Wednesday, March 14, 2007

Sheet

29

of

40

+3VALW_EC

+3VALW_EC
1

Ra

M/B_ID

@ R358
1

GATEA20
1
KB_RST#
2
SIRQ
3
LPC_LFRAME# 4
LPC_LAD3
5
LPC_LAD2
7
LPC_LAD1
8
LPC_LAD0
10

<19>
GATEA20
<19>
KB_RST#
<20>
SIRQ
<19,22,29> LPC_FRAME#
<19,22,29> LPC_AD3
<19,22,29> LPC_AD2
<19,22,29> LPC_AD1
<19,22,29> LPC_AD0

15P_0402_50V8J 33_0402_5%

CLK_PCI_EC
PCI_RST#
ECRST#
EC_SCI#

<15> CLK_PCI_EC
<18,23,29> PCI_RST#

2 R359
1
47K_0402_5%

+3VALW

<20>
1

C425
2

0.1U_0402_16V4Z

WL_BTN#

0214_Add Pull high resistor for LID_SW# and WL_BTN#.

SMB_EC_DA1
SMB_EC_CK1
SMB_EC_DA2
SMB_EC_CK2

<29,38>
<29,38>
<4>
<4>

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

<20>
SLP_S3#
<20>
SLP_S5#
<20>
EC_SMI#
<28> LID_SW#
<24,31,33,35,36> SUSP#
<20> PWRBTN_OUT#
<18,23> PCI_PME#

SUSP#

R402
100K_0402_5%

<28>

ON/OFF

SLP_S3#
SLP_S5#
EC_SMI#
LID_SW#
SUSP#
PWRBTN_OUT#
PCI_PME#

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

NUM_LED#

<28,29> NUM_LED#

EC DEBUG port

77
78
79
80

TP_BTN#
UTX
URX
ON/OFF

TP_BTN#

<28>

SMB_EC_CK1
SMB_EC_DA1
SMB_EC_CK2
SMB_EC_DA2

0.1U_0402_16V4Z

INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13

AD

PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D

DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F

83
84
85
86
87
88

EC_MUTE#
ACZ_RST#

EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11

GPI

OUT

@ 20M_0402_5%
R368

NC
IN 1
Y4 32.768KHZ_12.5P_1TJS125DJ2A073
C RY1
1
2

FOR LPC SIO DEBUG PORT

10P_0402_50V8J

IREF

V18R

124

<33>

EC_MUTE# <26>
ACZ_RST# <19,24>

TP_LED#
TP_CLK
TP_DATA

VCC

3.3V+/-5%

Ra

100K+/-5%

Board ID

Rb

V AD_BID min

V AD_BID typ

V AD_BID max

0V

0V

0V

8.2K+/-5%

0.216V

0.250V

0.289V

18K+/-5%

0.436V

0.503V

0.538V

33K+/-5%

0.712V

0.819V

0.875V

56K+/-5%

1.036V

1.185V

1.264V

100K+/-5%

1.453V

1.650V

1.759V

200K+/-5%

1.935V

2.200V

2.341V

NC

2.500V

3.300V

3.300V

TP_LED# <28>
TP_CLK <28>
TP_DATA <28>
CLK_ENABLE
1
10K_0402_5%

WL_BTN#

FRD#
FWR#
SPI_CLK
FSEL#

VCC1_PW RGD
FSTCHG
CAPS_LED#
BAT_LED#
ON/OFFBTN_LED#
SYSON
VR_ON
ACIN

THERM_SCI#

TP_CLK
2
1
10K_0402_5% R361
TP_DATA
2
1
10K_0402_5% R362

CLK_ENABLE <15>

WL_BTN# <28>

FR D#
FWR#
SPI_CLK
FSEL#

SLP_S4#

+5V

<29>
<29>
<29>
<29>

VCC1_PWRGD <29>
FSTCHG <33>
CAPS_LED# <28,29>
BAT_LED# <28>
ON/OFFBTN_LED# <28,29>
SYSON
<28,31,35>
VR_ON
<37>
ACIN
<33>
2
1
R393 10K_0402_5%
EC_RSMRST# <20>
EC_LID_OUT# <20>
EC_ON <28>
PM_PWROK <7,20>
BKOFF#
<17>
M_PWROK <7,20>

SLP_S4# <20>
THERM_SCI# <20>

KB926QFB0_LQFP128_14X14

For EMI
CP1
KSO14
KSO11
KSO10
KSO15

JP25
KSO15
KSO10
KSO11
KSO14
KSO13
KSO12
KSO3
KSO6
KSO8
KSO7
KSO4
KSO2
KSI0
KSO1
KSO5
KSI3
KSI2
KSO0
KSI5
KSI4
KSO9
KSI6
KSI7
KSI1

ECAGND

C427
+EC_AVCC

+3VS

R355
0_0402_5%

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

25
26

GND1
GND2

1
2
3
4

8
7
6
5

@ 100P_1206_8P4C_50V8
CP2
1
8
2
7
3
6
4
5

KSO6
KSO3
KSO12
KSO13

@ 100P_1206_8P4C_50V8
CP3
KSO2
KSO4
KSO7
KSO8

1
2
3
4

8
7
6
5

@ 100P_1206_8P4C_50V8
CP4
1
8
2
7
3
6
4
5

KSI3
KSO5
KSO1
KSI0

@ 100P_1206_8P4C_50V8

+5VS

DAC_BRIG <17>

EC_RSMRST#
100
101 R397 1 0_0402_5%
2
EC_ON
102
103
PM_PWROK
104
BKOFF#
105
M_PWROK
106
107
108
110
112
114
115
116
117
118

L14
0_0603_5%

CP5

ACES_85201-24051
CONN@

KSI4
KSI5
KSO0
KSI2

1
2
3
4

8
7
6
5

@ 100P_1206_8P4C_50V8
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ#0
PCI_RST#
CLK_DEBUG_PORT
SIRQ

ACES_85201-2005

CLK_14M_DEBUG <15>

SP01000FF00 85201-24051 24P P1.0

ACES_85201-24051_24P

L15

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

73
74
89
90
91
92
93
95
121
127

BATT_TEMP <38>
BATT_OVP <33>
ADP_I
<33>

IR EF

2
R360

2 ECAGND
0.01U_0402_16V7K

+3VALW_EC

@ JP24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

119
120
126
128

PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7

XCLK1
XCLK0

ACES_85205-0400

NC

97
98
99
109

<33>
1
C423

AGND

122
123

69

C RY2

10P_0402_50V8J
C426

+5VALW

11
24
35
94
113

URX
UTX

BATT_TEMP
BATT_OVP
ADP_IN
M/B_ID

DAC_BRIG

GND
GND
GND
GND
GND

1
1
2
3
4

ACOFF

68
70
71
72

1
2
3
4

INV_PWM <17>
FAN_PWM <4>

ACOFF

BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43

KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
PSCLK1/GPIO4A
KSI4/GPIO34
PSDAT1/GPIO4B
KSI5/GPIO35
PSCLK2/GPIO4C
PS2 Interface
KSI6/GPIO36
PSDAT2/GPIO4D
KSI7/GPIO37
TP_CLK/PSCLK3/GPIO4E
KSO0/GPIO20
TP_DATA/PSDAT3/GPIO4F
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
SDICS#/GPXOA00
KSO4/GPIO24
SDICLK/GPXOA01
KSO5/GPIO25 Int. K/B
SDIDO/GPXOA02
KSO6/GPIO26 Matrix
SDIDI/GPXID0
SPI Device Interface
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
SPIDI/RD#
KSO10/GPIO2A
SPIDO/WR#
SPI Flash ROM SPICLK/GPIO58
KSO11/GPIO2B
KSO12/GPIO2C
SPICS#
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
CIR_RX/GPIO40
KSO16/GPIO48
CIR_RLC_TX/GPIO41
KSO17/GPIO49
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
GPIO BATT_LOW_LED#/GPIO54
SCL1/GPIO44
SDA1/GPIO45
SUSP_LED#/GPIO55
SM Bus
SCL2/GPIO46
SYSON/GPIO56
SDA2/GPIO47
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A

INV_PWM
FAN_PWM

63
64
65
66
75
76

0205_Add Pull down R402 for SUSP#.

@ JP26

21
23
26
27

PWM Output

DA Output
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

R364
4.7K_0402_5%
4.7K_0402_5%
2

LID_SW#

R363

R365 R366
4.7K_0402_5%
4.7K_0402_5%
2

R404
10K_0402_5%

+5VALW
2

+3VS

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

1
R403
10K_0402_5%

GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC & MISC

JOPEN

+3VS

+3VALW

EC_SCI#

J1

12
13
37
20
38

Rb

@ C422

VCC
VCC
VCC
VCC
VCC
VCC

U18

@ C424
1
2

100K_0402_5%

R382
2
1
0_0805_5%

C421

+EC_AVCC

C420

+3VALW_EC

C419

2
2
1000P_0402_50V7K

@ R354

+3VALW

67

C418

1000P_0402_50V7K
1

AVCC

C417
2
2
0.1U_0402_16V4Z

0.1U_0402_16V4Z
1

9
22
33
96
111
125

0.1U_0402_16V4Z
1
1

1
C428

2
0_0603_5%

CP6
KSI1
KSI7

0.1U_0402_16V4Z
@ R383
10K_0402_5%
2
1
CLK_DEBUG_PORT <15,22,29>

LPC_DRQ#0 <19>

1
2
3
4

8
7
6
5

@ 100P_1206_8P4C_50V8

Compal Secret Data

Security Classification
Issued Date

2006/02/13

Deciphered Date

2006/07/26

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.

EC KB926/KB conn

Size

Document Number

Rev
0.2

LA-3732P
Date:

Wednesday, March 14, 2007

Sheet

30

of

40

+5VALW to +5VS Transfer

+5VALW

+3VALW to +3VS Transfer

+5VS

+3VALW

+3VS

B+
U19

C429

D
D
D
D

S
S
S
G

1
2
3
4

8
7
6
5

8
7
6
5

R369
1

AO4422_SO8
2 10U_0805_10V4Z

C431

C432

C430

330K_0402_5%

10U_0805_10V4Z

D
D
D
D

10U_0805_10V4Z

1
2
3
4

S
S
S
G

AO4422_SO8
2 10U_0805_10V4Z

U20

C433

C434

RUNON
1

RUNON
0.1U_0402_16V4Z

0.1U_0402_16V4Z

470_0402_5%
2

1
SUSP

R370

Q23
2N7002_SOT23-3

2
G

C435
0.01U_0402_16V7K

+5VALW

+5VALW
1

C436

100K_0402_5%

100K_0402_5%

+VCCP

0.1U_0402_16V4Z

R372

+VCC_CORE

R371

C437

Q24
2N7002_SOT23-3

2
G

SUSP

SUSP

SUSP# 2
G

<24,30,33,35,36> SUSP#

+VCCP
1

SYSON

<28,30,35> SYSON

<35>

SYSON#

<27,35> SYSON#

+1.5VS

0.1U_0402_16V4Z
Q25
2N7002_SOT23-3

H11
H12
H15
H16
H17
H18
H21
H23
HOLEA HOLEA HOLEC HOLEC HOLEC HOLEC HOLEC HOLEC

H27
HOLEA

Q32
2N7002_SOT23-3
3

H24
H25
H26
HOLEA HOLEA HOLEC

Q31 SUSP 2
2N7002_SOT23-3
G

2
1

Q30 SUSP 2
2N7002_SOT23-3
G
3

Q29 SUSP 2
2N7002_SOT23-3
G

Q28 SUSP 2
2N7002_SOT23-3
G
S

470_0402_5%

R379

470_0402_5%

R378

470_0402_5%

R377

470_0402_5%

R376

470_0402_5%

H1
H2
H3
H5
H6
H7
H8
H9
H10
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

+0.9V

R375

+VCCP

470_0402_5%

SYSON# 2
Q27
2N7002_SOT23-3
G
3

2
G

+1.25VS

R373

2
1

2
1

D
Q26 SUSP 2
2N7002_SOT23-3
G

SUSP

+1.5VS

R374
470_0402_5%

+1.8V

+3VS

+5VS

Discharge circuit

FM1

For Card reader/B stand off.

FM2

FM4

CF1
1

Compal Secret Data

Security Classification
2006/02/13

Issued Date

2006/07/26

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

CF2
1

CF3
1

CF4
1

CF5
1

CF6
1

CF7
1

CF8

Compal Electronics, Inc.

DC/DC Interface

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

E

31

of

40

VIN
PL1
HCB4532KF-800T90_1812
PCN1

ACES_88334-057N

100P_0402_50V8J PC2
1000P_0402_50V7K

PC4
1000P_0402_50V7K
2
1

PC1

PC3
100P_0402_50V8J
2
1

1
2
3
4
5

1
2
3
4
5

ADPIN

+3VALW
3

PQ38
TP0610K-T1-E3_SOT23

AC_LED <33>

PR157
100_0402_5%
1
2

Compal Secret Data

Security Classification
Issued Date

<Issued_Date>

Deciphered Date

<Deciphered_Date>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title
Size Document Number
Custom
Date:

DC CONN

Rev

LA-3732P

Wednesday, March 14, 2007

D

Sheet

32

of

40

P2
VIN
PQ1
FDS4435BZ_SO8

4
1

P4

<30>

P ACIN

ACOK

OUT

20

VREF

VH

19

ACIN XACOK

18

-INE1

RT

17

+INE1

-INE3

16

PACIN

PR25
10K_0402_1%
2
1

10

OUTC1 FB123

15

11

SEL

CTL

14

12

-INC1

+INC1

13

2
1

PC10
4.7U_1206_25V6K

1
3

1
2
3

PC9
4.7U_1206_25V6K
2
1

PD1
EC31QS04

FSTCHG

RB751V-40_SOD323-2
PD3
1
2

SUSP#

<24,30,31,35,36>

RB751V-40_SOD323-2

CV=12.6V (6/12 CELLS LI-ION)

CC=3.08A (6/12 CELLS LI-ION)

PR159
100K_0402_5%

BATT_DET <38>

2
G
S

1
PU4A
LM358ADT_SO8

PU4B
LM358ADT_SO8

8
7

D
PQ37
RHU002N06_SOT323-3

+5VALW

+3VALW

PR158
100K_0402_5%

PQ12
RHU002N06_SOT323-3

S
PQ13
DTC115EUA_SC70-3

+3VALW

PC30
0.01U_0402_25V7K

4
1

2
+

2
G

BATT

0.02_1206_1%

PC27
47P_0402_50V8J
1
2

PR32
PR31
499K_0402_1% 340K_0402_1%

2
8
1

PR33
47K_0402_1%

CS

PR35
10K_0402_5%
1
2

PR34
105K_0402_1%

ANODE

NC

+5VALW
PC29
0.01U_0402_25V7K

NC

RLZ4.3B_LL34

<30> BATT_OVP

PC25
10P_0402_50V8J
1
2

2
3

PR17

PC23
1500P_0402_50V7K
21
2

<34>

1.24VREF

CATHODE

+3VALW

PR20
47K_0402_1%
1
2

BATT
PU3

REF

PL3
16UH_SIL1045R-160_4.1A_30%
1
2

PD2

PR30
1
2
51K_0402_1%

FDS4435BZ_SO8

PC16
0.1U_0603_25V7K
1
2

PR26
33K_0402_1%
MB39A126 1

<30>

PC21
10U_1206_25V6M
2
1

ACOFF

21

DTC115EUA_SC70-3

PC20
10U_1206_25V6M
2
1

VCC

PQ7
RHU002N06_SOT323-3

-INE2

PQ10

PC13
0.22U_0603_16V7K
1
2
PC14
0.1U_0603_25V7K
1
2

CS

2
G
PQ9
S
RHU002N06_SOT323-3

PQ11

PR29
10K_0402_5%

PD4

22

LM393DG_SO8

P2

23

CS

3.2V

PC28
22P_0402_25V8K
2
1

GND

+INE2

PR10
100K_0402_5%
2
1
2
G

PC19
10U_1206_25V6M
2
1

1
2

ACIN

2
1K_0402_5%

LMV431ACM5X_SOT23-5

FSTCHG

OUTC2

PU2A

<30>

PR19
PC18
1K_0402_1% 2200P_0402_50V7K
MB39A1261
2
1
2

PR21
150K_0402_1%

2
8
-

PR22
10K_0402_1%

PC24
0.1U_0603_25V7K

<30>

65W: PR46=34.8K
90W: PR46=21.0K

PC22
1U_0603_6.3V6M

PR146

133K_0603_1%

PR23

2
1
PR28

10K_0603_0.1%

PC26
0.047U_0402_16V7K
2
1
3

+3VLP

VIN
IREF

VREF

PC17
0.22U_0603_16V7K

PR18
1
2
1M_0402_5%

PR160
47_1206_5%

PR27
2.15K_0402_1%
1
2

ADP_I_A

ACOFF#

<32> AC_LED

5
6
7
8

PR16
34.8K_0603_1%

1
PR15
10K_0402_1%
2
1
2

1
2

PC15
0.01U_0402_25V7K

P2

VIN

PR2
10K_0402_5%

P ACIN

PR1
100K_0402_1%

MB39A126

PC12
PR14
4700P_0402_25V7K 100K_0402_1%
1
2
2
1

1SS355_SOD323-2

VIN

PU1
MB39A126PFV-ER_SSOP24
1 -INC2 +INC2 24

PC8
2200P_0402_50V7K
2
1

2
PR12
10K_0402_1%
1
2

PR24
100K_0402_1%

CHG_B+

2
G

PD5
ACOFF#

PR9
10K_0402_5%

D
PQ8
RHU002N06_SOT323-3

1
2
3K_0402_5%

PC7
0.1U_0603_25V7K
2
1

PR13

1
PR11

CHG_B+

0_0402_5%

ADP_I

<30>

PR8
150K_0402_5%

PC11
0.22U_0603_16V7K
P ACIN

0.015_2512_1%

S PQ6
RHU002N06_SOT323-3

PR5
1
2
47K_0402_5%

PL2
SMB3025500YA_2P
1
2

PR7

PQ5
DTC115EUA_SC70-3

8
7
6
5

PR4
200K_0402_5%

2
G

BATT

PQ3
FDS4435BZ_SO8

3
2
1

PC6
1

0.1U_0603_16V7K

B+

DTA144EUA_SC70-3

2
1

4
PQ4

8
7
6
5

PR6
47K_0402_1%
1
2

3
2
1

PQ2
FDS4435BZ_SO8

3
2
1

PC5
47P_0402_50V8J
1
2

PR3
47K_0402_5%
2
1

8
7
6
5

Compal Secret Data

Security Classification
Issued Date

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

Charger

Size Document Number

Custom
Date:

W ednesday, March 14, 2007

D

R ev
Sheet

33

of

40

5
6
7
8

3
2
1
5
6
7
8

2
PR47
0_0402_5%

1
2
1
PR46
@499K_0402_1%

3
2
1

1
2
1
PR45
@499K_0402_1%

17
VCC

TON

V+

10U_LF919AS-100M-P3_4.5A_20%

+3VALWP
2

MAX8734AEEI+_QSOP28

+3VLP

PR57
0_0402_5%

1
+

VL

PC43
220U_6.3VM_R15

PC46
0.047U_0603_16V7K

BST_3.3V
DH_3.3V
DL_3.3V
LX_3.3V

PR55
2
1
499K_0603_1%

23

PC44
0.22U_0603_10V7K

MAINPWON <38>

PR56
300K_0402_5%
2
1

MAINPWON

13

20

REF

PL6

7
2

FB3
PGOOD

2VREF_1999
VL

28
26
24
27
22

SKIP#

BST3
DH3
DL3
LX3
OUT3

PQ36
AO4468_SO8

PR54
@3.57K_0402_1%

12

ILIM5

11

0_0402_5%
PR44

SHDN#
ON5
ON3

6
4
3

PR50
1
2
@0_0402_5%
1
2
PR52
@10K_0402_5%

PR43
0_0402_5%

PR58
0_0402_5%

2VREF_1999

ILIM3

DH_3.3V_B

PRO#

2
0_0402_5%

PR42
0_0402_5%

10

PR49

LX5
DL5
OUT5
FB5
N.C.

PQ16
AO4468_SO8

15
19
21
9
1

LDO3

LX_5V
DL_5V

GND

DH5

25

16

PC45
4.7U_0805_10V4Z

PR51
47K_0402_5%
2
1
2
1
PC42
0.1U_0603_25V7K

2VREF_1999

18

1
2
3
2
PR53
0_0402_5%

2
1
2
2

220U_6.3VM_R15

PR48
@10.2K_0402_1%

+5VALWP

BST5

DH_5V

PC35
0.1U_0603_16V7K

2VREF_1999

PU5
BST_5V 14

PC41 1

LD05

PC40
4.7U_0805_10V4Z

4
PL5
10U_LF919AS-100M-P3_4.5A_20%

VL

PC38
2
1
0.1U_0603_50V4Z

8
7
6
5

1
2
3

PR41
0_0402_5%

PC39
1U_0805_16V7K

B++

PR39
0_0402_5%
2

4DH_5V_B

B++

VL

PC37
4.7U_1206_25V6K

PQ15
AO4468_SO8

PQ35
AO4468_SO8

B++

PD6
CHP202UPT_SOT323-3

8
7
6
5

2
1
PC34
10U_1206_25V6M

2
1
PC33
2200P_0402_50V7K

B+
1

PC32
0.1U_0603_50V4Z
1
2

BST_3.3V_B

BST_5V_B

PC36
2200P_0402_50V7K

PC31
0.1U_0603_50V4Z
1
2

B++

FBM-L11-322513-151LMAT_1210

PR40
47_0402_5%

PL4

PQ17

PR59
100K_0402_5%

2
G
PQ19
RHU002N06_SOT323-3

+3VLP
2

<33>

2
PACIN
G
PQ18
RHU002N06_SOT323-3

PQ26
TP0610K-T1-E3_SOT23

2
G
S RHU002N06_SOT323-3
D

PR156
100K_0402_5%

PR154
100K_0402_5%

<28>

51ON#

Compal Secret Data

Security Classification
<Issued_Date>

Issued Date

Deciphered Date

<Deciphered_Date>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

3.3VALWP / 5VALWP

Size
Date:

Document Number
Wednesday, March 14, 2007

Rev
Sheet
E

34

of

40

PL7
FBMA-L11-322513-151LMA50T_1210
1.8V_B+
2
1

5
6
7
8
1

PC59
1U_0603_10V6K

1
2

1
2

PC58
@680P_0603_50V7K

1
DL
SC411MLTRT_MLPQ16_4X4

PC52
0.1U_0402_16V7K

10

+
PR68
@4.7_1206_5%

PGND

VSSA

NC

17

TP

ILIM
VDDP

PQ22
FDS6690AS_NL_SO8

LX_1.8V
PR69
1
2
16.9K_0402_1%

PC51
0.1U_0402_16V7K

11

15

13

5
6
7
8

NC

BST

12

LX

PC50
220U_6.3VM_R15

PGD

DH

FB

+1.8VP
1

PL8
3.3UH_SIL1045R-3R3PF_8.2A_30%
1
2

VCCA

PC56
0.1U_0402_16V7K

3
2
1

VOUT

UG_1.8V
BOOT1_1.8V

14

16

EN/PSV

PU6

PR65
2
0_0402_5%

3
2
1

BOOT_1.8V 1

PR66
100K_0402_5%

TON

1
PC55
@2200P_0402_25V7K

PC57
1U_0603_10V6K

2
1

PR64
0_0402_5%

PD7
1SS355_SOD323-2

PC54
1000P_0402_50V7K

<28,30,31> SYSON

PQ21
AO4468_SO8

PR62
1M_0402_5%

PR61
10_0402_5%

2
1
PC49
10U_1206_25V6M

PC47
680P_0402_50V7K

+5VALW

PC48
2200P_0402_50V7K
2
1

B+

LG_1.8V

EN

VOUT

FB

VOUT

+1.25VSP

+5VALW

(4.5A,180mils ,Via NO.= 9)

+1.25VSP

+3VL

(100mA,20mils ,Via NO.= 1)

+1.8V

PC63
10U_0805_10V4Z

(7A,280mils ,Via NO.= 14)

PAD-OPEN 4x4m
PJP6
+1.05V_VCCP

1
2
1
2

PU8

1
PAD-OPEN 2x2m

+VCCP

<7,13,14> V_DDR_MCH_REF

(6A,240mils ,Via NO.=12)

VIN

VCNTL

GND

NC

VREF

NC

VOUT

NC

TP

+5VALW

PR72
1K_0402_1%

PR150
59K_0402_1%

+1.8V

PJP4

(3A,120mils ,Via NO.= 6)

+3VLP

PC128
47P_0402_50V8J
B

+3VALW

PAD-OPEN 4x4m
PJP5
+1.8VP

PC130
22U_1206_6.3V6M

,Via NO.= 1)

+1.25VS(500mA,40mils

+3VALWP

2
PAD-OPEN 3x3m

2
PAD-OPEN 4x4m
PJP3

PC64
10U_0805_10V4Z

PJP2

+5VALWP

PR149
33.2K_0402_1%
APL5913-KAC-TRL_SO8
B

PJP1

PC129
10U_1206_6.3V6M

PC127
@ 0.01U_0402_16V7K

2
PR148
0_0402_5%

VIN

<24,30,31,33,36> SUSP#

VIN

PR71
10K_0603_0.1%

POK

GND

PC60
33P_0402_50V8J

2
PR147
@ 0_0402_5%

+1.5VS

PC126
1U_0603_6.3V6M

PU13

VCNTL

PR70
1
2
27K_0603_0.1%

+5VALW

PC65
1U_0603_16V6K

G2992F1U_SO8

+0.9V

<31> SUSP

(2A,80mils ,Via NO.= 4)

1
PR60
0_0402_5%

PR67
1K_0402_1%

2
G

+0.9VP

PC67
10U_1206_6.3V7K

PAD-OPEN 3x3m

PC68
@0.1U_0402_16V7K

PQ20
RHU002N06_SOT323-3

PJP8
+0.9VP

(6A,240mils ,Via NO.=12)

+1.5VS

2
PAD-OPEN 4x4m

PR73
@0_0402_5%

+1.5VSP

<27,31> SYSON#

PJP7

2
1
PC66
0.1U_0402_16V7K

PAD-OPEN 4x4m

Compal Secret Data

Security Classification
Issued Date

<Issued_Date>

Deciphered Date

<Deciphered_Date>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

1.8VP/0.9VSP/2.5VSP

Size

Document Number

R ev
0.2

LA-3732P
Date:

W ednesday, March 14, 2007

1

Sheet

35

of

40

PR76
75K_0402_1%

PR75
75K_0402_1%
1
2

PR77
29.4K_0402_1%

PR74
73.2K_0402_1%
1
2

5
6
7
8

PR78
0_0402_5%

PC131

PQ24
AO4468_SO8

17

16

3
2
1
20

DR VL1

19

+1.05V_VCCP

0.1U_0603_25V7K
LX_1.05V

1
1

1
VO1

VFB1

3
GND

4
TONSEL
15

PR85
15K_0402_1%
1
2

PR87
0_0402_5%
2
1

LL1

UG_1.05V

PL10
2.2UH_PCMC063T-2R2MN_8A_20%
<BOM Structure>
1
2

PC78

LG_1.05V
PC74
4.7U_0805_6.3V6K

TPS51124RGER_QFN24_4x4

PQ25
FDS6690AS_NL_SO8

PR86
18K_0402_1%

1
PR88
3.3_0402_5%

PC80
1U_0603_10V6K

PC79
@1000P_0402_50V7K

<24,30,31,33,35> SUSP#

14

13

PC76
4.7U_0805_6.3V6K

DR VH1

21

PR84
0_0402_5%
1
2

BST_1.05V

PC73
220U_6.3VM_R15

PGND2

DR VL2

22

VFB2

LL2

12

VO2

DR VH2

11

220U_6.3VM_R15
PC75

LG_1.5V

10

EN1
VBST1

PR82
0_0402_5%
1
2UG1_1.05V

PR81
2
1
0_0402_5%

LX_1.5V

VBST2

23

5
6
7
8

0.1U_0603_25V7K

UG_1.5V

EN2

24

3
2
1

SP8K10S FD5 2N SOP8

BST_1.5V

PGOOD1

PGND1

PGOOD2

TRIP1

PR83
0_0402_5%
1 1
2

PC77

VCCP_POK

18

UG1_1.5V

8
7
6
5

P PAD

V5IN

PL14
3.3UH_SIQB74B-3R3PF_5.9A_20%

+1.5VSP

D2
G2
D2
D1/S2/K
G1
D1/S2/K
S1/A D1/S2/K

25
PR80
1
2
0_0402_5%

V5FILT

1
2
3
4

PR79
0_0402_5%
1
2

TRIP2

PQ23

0.1U_0603_16V7K
PU9

PC69
@2200P_0402_50V7K
2
1
PC70
10U_1206_25V6M

1
2

PC72
4.7U_1206_25V6K

B+++

PL9
FBMA-L11-322513-151LMA50T_1210
1
2
PC71
@2200P_0402_50V7K
2
1

B+

1
1

+5VALWP
PC81
4.7U_1206_25V6K

SUSP#

0_0402_5%
PR89

PC82
@1000P_0402_50V7K

Compal Secret Data

Security Classification
Issued Date

2006/11/23

Deciphered Date

2007/11/23

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

1.2V_VP/1.5VSP/1.05VP

Size

Document Number

R ev
0.2

LA-3732P
Date:

W ednesday, March 14, 2007

1

Sheet

36

of

40

+5VS

CPU_B+

B+

PL11
SMB3025500YA_2P

CCI

10

CC1_CPU

39

DPRSLPVR

DH2

21

DH2_CPU

40

DPRSTP

BST2

20

BST2_CPU

PSI

LX2

22

LX2_CPU

PWRGD

DL2

24

DL2_CPU

CLKEN

PGND2

23

38

SHDN

CSP2

14

VRHOT

CSN2

15

POUT

GNDS

13

PC105
2
1

MAX8770GTL+_TQFN40

PR126
@10K_0402_5%

<5>

VSSSENSE

1
2

5
6
7
8
D
D
D
D
G
S
S
S
4
3
2
1
2

NTC PR120
@3K_0603_1%
2

PR121
@3K_0603_1%
1

PR124
20K_0402_1%

VCCSENSE

VCCSENSE <5>

2
100_0402_5%

PC104
4700P_0402_25V7K

2
CPU_B+

PC106
470P_0402_50V8J

PQ30
SI4684DY-T1-E3_SO8

VSSSENSE
PR130
1

PC111
0.1U_0402_16V7K

2
@0.022U_0402_16V7K

1
PR116

2.2_0603_5%
2

PL13

0.36UH_PCMC104T-R36MN1R17_30A_20%

PR132
2.1K_0603_1%
1

PR131
4.7_1206_5%

2
10K_0402_5%

2
3.65K_0402_1%

10KB_0603_5%_ERTJ1VR103J

PC102
0.22U_0603_16V7K

1
PC103

1
PR129

1
PR118

PQ31
FDS6676AS_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

POUT

2
@3K_0603_1%

PC112
680P_0603_50V7K

<4> H_PROCHOT#

2
@0_0402_5%

PR127
100_0402_5%
1
PR128

1
PR115

PQ32
FDS6676AS_SO8
1
2
1

CSN2_CPU

TP

2
<30> VR_ON

1
2
PR123 0_0402_5%
1
2
PR122 0_0402_5%
1
2
PR125
0_0402_5%

CLK_EN#

CSP2_CPU

1
<15,20> VGATE

FB

REF

CCV

11

1
2
PR109
3.48K_0402_1%

PC110
2200P_0402_50V7K
2
1

CSN1_CPU
FB1_CPU

12

PC108
10U_1206_25V6M
2
1

16

CSN1

NTC
PH2

TIME

CSP1_CPU

PR107
4.7_1206_5%

17

PC101
680P_0603_50V7K

CSP1

+VCC_CORE

PR105
2.1K_0603_1%

PC107
10U_1206_25V6M
2
1

D6

PQ29
FDS6676AS_SO8
2
1

37

5
6
7
8

18

D
D
D
D

27

GND

G
S
S
S

PGND1

D5

4
3
2
1

D4

36

PR117
2K_0402_1%

PC98
2

35

+VCC_CORE

1
2

26

+3VS

PR119
1.91K_0402_1%

DL1

5
6
7
8

H_PSI#

D3

G
S
S
S

<5>

LX1

34

D
D
D
D

<5,7,19> H_DPRSTP#

D2

28

0.36UH_PCMC104T-R36MN1R17_30A_20%

4
3
2
1

<7,20> DPRSLPVR

DL1_CPU

33

PL12

PR101 2.2_0603_5%
1
2

5
6
7
8

CPU_VID6

DH11_CPU
LX1_CPU

1
0_0402_5%

D
D
D
D

<5>
C

29

G
S
S
S

CPU_VID5

30

DH1

4
3
2
1

CPU_VID4

<5>

BST1

D1

DL1_CPU

<5>

D0

32

DL2_CPU

CPU_VID3

BST1_CPU 2
PR99

31

NTC
PH3
1
2
PR133
3.48K_0402_1%

10KB_0603_5%_ERTJ1VR103J
A

1
PC113

2
0.22U_0603_16V7K

Compal Electronics, Inc.

Title

+CPU_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

PQ27
SI4684DY-T1-E3_SO8

PQ28
FDS6676AS_SO8
4 G
D 5
3 S
D 6
2 S
D 7
1 S
D 8

CPU_VID2

<5>

1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
1
0_0402_5%
2
1
PR108
71.5K_0402_1%
1
2
PC99
470P_0402_50V8J
1
2
PC100 0.22U_0603_16V7K
1
2
PR110
499_0402_1%
1
2
PR112
0_0402_5%
1
2
PR111
0_0402_5%

BSTM2 CPU

<5>

2
PR98
2
PR100
2
PR97
2
PR102
2
PR104
2
PR103
2
PR106

1
2
PC109
0.22U_0603_16V7K

CPU_VID1

25

TON

1000P_0402_50V7K
2

CPU_VID0

<5>

VDD

THRM

41

<5>

Vcc

2
0_0402_5%

19

1
PR114

V CC

0.22U_0603_16V7K

BSTM1 CPU

PC94
2200P_0402_50V7K
2
1

+
2

PC93
10U_1206_25V6M
2
1

PU12
@470KB_0402_5%_ERTJ0EV474J
PH4
2
1

PC95
47U 25V M 6.3X6 ESR0.44 CE-LX
PC92
10U_1206_25V6M
2
1

1
1
2

PR96
200K_0402_5%

1
2
PC97
1U_0603_16V6K

2.2U_0603_6.3V6K

PR95
13K_0402_5%

PC90

2
1

PR94
10_0402_5%

PC91
0.01U_0402_25V7K

PC96
1000P_0402_50V7K

Size
Document Number
Custom
Date:

R ev
0.2
Sheet

Wednesday, March 14, 2007

1

37

of

40

VMB

BATT

PL15

PCN2

TYCO_C-1746706_6P

PD8
1

BATT_DET <33>
PR151
2
1
@1K_0402_5%
@SM05_SOT23

PC122
1000P_0402_50V7K

GND

EC_SMD
EC_SMC

SMD
SMC
RES
TS

6
5
4
3
2

BATT+

HCB4532KF-800T90_1812
1
2

PC123
0.01U_0402_50V4Z

PR152
6.49K_0402_1%
1
2

PD9
@SM24.TC_SOT23-3

+3VL

PR153
1K_0402_5%

PR138
100_0402_5%

BATT_TEMP <30>

PR139
100_0402_5%
SMB_EC_DA1

SMB_EC_DA1 <29,30>

SMB_EC_CK1

SMB_EC_CK1 <29,30>

PH1 under CPU botten side :

CPU thermal protection at 90 +-3 degree C
Recovery at 47 +-3 degree C
PR140
47K_0402_1%
1
2

+5VS

CPU

+5VS

PR141
10K_0402_5%

PH1
10K_TH11-3H103FT_0603_1%

PQ33
RHU002N06_SOT323-3

2
G

LM393DG_SO8

1
PR145
150K_0402_1%

P
O

PC125
1000P_0402_50V7K

PC124
0.22U_0603_10V7K

PR144
2.55K_0603_1%

PR143
150K_0402_1%

8
5

+5VS

PU2B

MAINPWON <34>
PR142
15K_0603_1%
1
2

Compal Secret Data

Security Classification
Issued Date

<Issued_Date>

Deciphered Date

<Deciphered_Date>

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.

BATTERY CONN

Size Document Number

Custom LA-3732P
Date:

Rev

Wednesday, March 14, 2007

D

Sheet

40

of

38

Version change list (P.I.R. List)

Item

Reason for change

Power section

PG#

Page 1 of 1

Modify List

HW request.

35

Change PR152 from 210K to 6.49K

38

Change PR152 from 210K to 6.49K

Follow Volga 2.0 design.

37

Delete PC118,PC119,PC120,PC121,PR113,PR134.

For layout concern.

Prevent S3 leakage issue.

Prevent LMV431 will oscillate.

Prevent LMV431 will oscillate.

Date

Modify 1.25VSP enable signal from SLP_S3# to SUSP#.

Phase

2/13
2/13
3/6

37

Change PC95 location behind PL11.

3/8

33

Change PD3 pin 2 connect from EC_ON to SUSP#

3/9

33

Change PR30 from 75K to 51K.

3/9

33

Change PC28 from 0.022u to 22P.

3/9

EMI request add CPU core snabber and gate driver use 2.2_0603

34

Change PR101&PR130 from 0_0402 to 2.2_0603

3/12

Modify DC in jack LED design for energy star.

35

Add PQ105.

3/12

Compal Secret Data

Security Classification
Issued Date

2006/02/28

2007/02/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

Changed-List History-1

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

39

of

40

Version Change List ( P. I. R. List ) for HW Circuit

Item
D

1
2
3
4
5
6
7
8
9
10
11
12
13
14

Change item
Change C117 from 220uF to 10uF.
Remove R401.
Change Crystal Y2 type (the same as Abita).
Connect LAN_RST# from EC_RAMRST# to GND.
Change ODD connector type.
Change U11 power from +5VS to +5VALW.
Change U11 enable signal from SLP_S3# to SUSP#.
Reverse JP19 USB Connector and
need to double check layout symbol.
Change Power and Battery charge LED
power from +3VALW to +5VALW.
Change HDD LED power from +3VS to +5VS.
Delete reserve component (D25 BSW2) for 14.1".
Change R329, R333, R470 from 200 ohm to 470 ohm.
Change R334, R339 from 200 ohm to 820 ohm.
Add pull down resistor R402 (100k ohm) for SUSP#.
Change C44, C49 type from DIP to SMD.
Add R402 pull high resistor for LID_SW#.
Add R403 pull high resistor for WL_BTN#.
Delete D19.
Change R300 from 10 ohm to 47 ohm
and C374 from 10pF to 33pF.
Delete JP27, R317, C392.
Delete R297.
Change RTC battery and connector.
Change C413 and 414 package from 0603 to 0402.
Add JP28 for USB card reader.
Change R105 from 22 ohm to 0 ohm.
Delete C49 and remount C46.
Change JP16 and JP17 Audio Jack.
Add R405.
Change USB connector (JP19) type.

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Page

Date

Phase

10

2/8

DB --> SI

19

2/5

DB --> SI

19

2/5

DB --> SI

20

2/5

DB --> SI

22

2/13

DB --> SI

24

2/12

DB --> SI

24

2/8

DB --> SI

27

2/12

DB --> SI

28

2/8

DB --> SI

28

2/8

DB --> SI

28

2/8

DB --> SI

28

2/8

DB --> SI

28

2/8

DB --> SI

30

2/5

DB --> SI

06

2/14

DB --> SI

30

2/14

DB --> SI

30

2/14

DB --> SI

28

2/16

DB --> SI

24

2/16

DB --> SI

26

2/16

DB --> SI

24

2/16

DB --> SI

19

2/26

DB --> SI

28

2/26

DB --> SI

27

2/28

DB --> SI

15

3/1

DB --> SI

06

3/1

DB --> SI

26

3/2

DB --> SI

04

3/6

DB --> SI

27

3/8

DB --> SI

Compal Secret Data

Security Classification
Issued Date

2006/02/28

2007/02/28

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.

HW Changed-List History-1

Size

Document Number

Rev
0.2

LA-3732P
Date:

Sheet

Wednesday, March 14, 2007

1

40

of

40