One reason for running gate-level simulation is design for test (DFT).

Because scan chains are inserted after the gate-level netlist is created, gate-level simulation is often used to determine whether scan chains are correct . Another motivation for gate-level simulation is that technology libraries at 45 nm and below have far more timing checks, and more complex timing checks, than olde r process nodes. to observe the glitches, and glitches may occur because of issues with simualtio n or logic timing voilations like setup,hold,recovery .... functianlity check ..because of mismatch between rtl & gate list ..

sta cannot find glitches ..since sta is not dynamic in nature. logic equivalence check behaves just like synthesis ....so it may not find misma tches between rtl & gate level netlist

------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------check timescale is correct or not check whether every filpflop is initalized or not during reset condition case 1: synchronous reset all fipflops should initialize at almost same time case 2: Asynchronous reset a) reset active period is minimum(glitch) now also, all fipflops should initialize at almost same time b) reset active perios is maximum

now also, all fipflops should initialize at almost same time e.g : output of one flipflop is an input to another filpflop , since first f/f g ot reset in advance , so first ff gets default value , and if data propagates faster than rese t, then system enter into different state .. check PLI/DLL configurations are correct or not & clock is togging correctly or not with respect to configurations see the chip initialization sequence & observe the sequence under full-timing si mulation & also in zero-delay ideal clock simulation See whether IO timings are correctly implemented or not concentrate on paths that are declared as false,multi-cycle,critical ,asynchrono us ...paths in STA i.e we need to check what are the false paths,multi-cycle paths ...and then we n eed to write a testcase to activate these paths in gate level simulation