Gcpu Files

University of Florida
Department of Electrical & Computer Engineering
EEL 3701 Revision 0
Drs. Gugel and Schwartz 10-Nov-10
Page 1/1
Bi-directional Data Bus
G-CPU Block Diagram

8 6
IR_LD CLK
IR5:0 Register IR5:0 6 CLK Z Flag N Flag
Controller
MSA1:0 MSB1:0 MSC3:0 CLK
MUXA
MUXB
ALU
Z Flag N Flag MUXC
(Reset not shown due to space constraints)
PC_INC PC_LD (U/L) MAR_INC MAR_LD (U/L) X_INC X_LD (U/L) Y_INC Y_LD (U/L) IR_LD R/-W ADDR_SEL1:0 XD_LD YD_LD
R/-W
R/-W
A15:0
Address Bus Mux 0

1 2 3
Program Counter (H/L)
Mem Addr Reg (H/L)
X Reg Block
16
S1
S0
ADDR_SEL1:0
Y Reg Block Note: PC, MAR, X, Y outputs are 16 bits X Reg Block = X displacement Reg + X Reg (H/L) Y Reg Block = Y displacement Reg + Y Reg (H/L)
EEL 3701
Revision 0
EEL 3701
Revision 0
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G-CPU Instruction Set

Instruction TAB TBA LDAA #data LDAB #data LDAA addr LDAB addr STAA addr STAB addr LDX #data LDY #data LDX addr LDY addr LDAA dd,X LDAA dd,Y LDAB dd,X LDAB dd,Y STAA dd,X STAA dd,Y STAB dd,X STAB dd,Y Operand none none 8-bit data 8-bit data 16-bit address 16-bit address 16-bit address 16-bit address 16-bit data 16-bit data 16-bit addr 16-bit addr 8-bit displacement 8-bit displacement 8-bit displacement 8-bit displacement 8-bit displacement 8-bit displacement 8-bit displacement 8-bit displacement Description Transfer A to B (inherent addressing) Transfer B to A (inherent addressing) Load A with immediate data (immediate addr.) Load B with immediate data (immediate addr.) Load A with data from memory location addr (extended addressing) Load B with data from memory location addr (extended addressing) Store data in A to memory location addr (extended addressing) Store data in B to memory location addr (extended addressing) Load X with immediate data (immediate addr.) Load Y with immediate data (immediate addr.) Load X with data from memory location addr. (extended addressing) Load Y with data from memory location addr. (extended addressing) Load A with data from memory location pointed to by X + dd (indexed addressing) Load A with data from memory location pointed to by Y + dd (indexed addressing) Load B with data from memory location pointed to by X + dd (indexed addressing) Load B with data from memory location pointed to by Y + dd (indexed addressing) Store data in A to memory location pointed to by X + dd (indexed addressing) Store data in A to memory location pointed to by Y + dd (indexed addressing) Store data in B to memory location pointed to by X + dd (indexed addressing) Store data in B to memory location pointed to by Y + dd (indexed addressing) # of States 2 2 3 3 5 5 5 5 4 4 6
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G-CPU Instruction Set

Instruction SUM_BA SUM_AB AND_BA AND_AB OR_BA OR_AB COMA COMB SHFA_L SHFA_R SHFB_L SHFB_R INX INY Operand none none none none none none none none none none none none none none Description Sum A, B and place in A (inherent addressing) Sum A, B and place in B (inherent addressing) AND A, B and place in A (inherent addressing) AND A, B and place in B (inherent addressing) OR A, B and place in A (inherent addressing) OR A, B and place in B (inherent addressing) Complement contents in A (inherent addressing) Complement contents in B (inherent addressing) Shift A left by one-bit (inherent addressing) Shift A right by one-bit (inherent addressing) Shift B left by one-bit (inherent addressing) Shift B right by one-bit (inherent addressing) Increment X (inherent addressing) Increment Y (inherent addressing) # of States 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Data Movement Instructions:

Machine Codes (hex) 00 01 02 mm 03 mm 04 ll hh 05 ll hh 06 ll hh 07 ll hh 08 ii jj 09 ii jj 0A ll hh 0B ll hh 0C dd 0D dd 0E dd 0F dd 10 dd 11 dd 12 dd 13 dd
ALU Related Instructions:

Machine Codes (hex) 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 30 31
Branch Instructions:
6 4 4 4 23 bb 4 4 4 4 4 BP Machine Codes (hex) 20 bb 21 bb 22 bb Instruction BEQ BNE BN Operand Description addrL Branch if A = 0, i.e., Z Flag = 1 (absolute addressing) addrL Branch if A 0, i.e., Z Flag = 0 (absolute addressing) Branch if A is negative, i.e., N Flag = 1 (absolute addrL addressing) Branch if A is positive (or zero), i.e., N Flag = 0 addrL (absolute addressing) # of States 3 3 3 3
Special Notes 1. Z flag and N flag are only set and cleared by the contents in register A. 2. A branch is accomplished by moving the operand address addr to the lower byte of the PC. The upper byte of the PC remains unchanged after a branch. 3. The Branch Instructions use absolute addressing where only the low byte of the address is used as an operand. If the branch condition is met, the high byte of the PC is unchanged and the low byte takes the value of the operand (addrL). 4. Explanations of the operands shown in the Machine Codes: mm 8-bit immediate data value ii Low-order byte of a 16-bit data jj High-order byte of a 16-bit data ll Low-order byte of a 16-bit address hh High-order byte of a 16-bit address dd 8-bit displacement value bb Low-order byte of a 16-bit address for a branch instruction
EEL 3701 Revision 0
EEL 3701 Revision 0
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G-CPU Controller Flow Charts
Page 2/6
Data Movement Instructions:

TAB 000000 TBA 000001 LDAA #data 000010 LDAB #data 000011 LDAA addr 000100
000000
IR_LD
Special Notes: 1. MSA[1..0] & MSB[1..0] are set to protect registers A & B when these registers are not in use. R_/W is always set H (read cycle) unless otherwise specified in the ASM chart. ADDR_SEL is always set to connect the PC to the Address Bus (i.e. ADDR_SEL = 00) unless otherwise specified in the ASM.
Instruction Fetch
A => B B => A
000010 data => A INC_PC
000011 data => B INC_PC
000100 addrL => MARL INC PC
2.
000101 addrH => MARH INC PC 000001
3.
INC_PC
Instruction Decode/Execution
000110 addr[ ] => A AddrSel = MAR Back to State0
LDAB addr 000101
STAA addr 000110
STAB addr 000111
LDX #data 001000
LDY #data 001001
010000 data => XL INC PC
010010 data => YL INC PC
IR[5..0]
001000 addrH => MARH INC PC 001011 addrH => MARH INC PC 001110 addrH => MARH INC PC 010001 data => XH INC PC 010011 data => YH INC PC
001001 addr[ ] => B AddrSel = MAR
001100 A => addr[ ] AddrSel = MAR R_/W = 0
001111 B => addr[ ] AddrSel = MAR R_/W = 0 Back to State0
Instructions Listed on Next Pages
EEL 3701 Revision 0
EEL 3701 Revision 0
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Data Movement Instructions (continued):

LDX addr 001010 LDY addr 001011 LDAA dd,X 001100 LDAA dd,Y 001101 LDAB dd,X 001110
ALU Related Instructions:

SUM_BA 010100 SUM_AB 010101 AND_BA 010110 AND_AB 010111 OR _BA 011000
011000 010100 addrL => MARL INC PC
011100 dd => Xdisp INC PC
011110 dd => Ydisp INC PC
A SUM B => A
A SUM B => B
A AND B => A
A AND B => B
A OR B => A
010101 addrH => MARH INC PC
011001 010101 addrH => MARH INC PC
011101 X[ ] => A AddrSel = X
011111 Y[ ] => A AddrSel = Y
100001 X[ ] => B AddrSel = X
Back to State0 OR_AB 011001 COMA 011010 COMB 011011 SHFA_L 011100 SHFA_R 011101
010110 addr[ ] => XL AddrSel = MAR INC MAR
011010 010110 addr[ ] => YL AddrSel = MAR INC MAR
A OR B => B 010111 addr+1[ ] => XH AddrSel = MAR 011011 addr+1[ ] => YH AddrSel = MAR Back to State0
/A => A
/B => B
A * 2 => A
A/2 => A
Back to State0
LDAB dd,Y 001111
STAA dd,X 010000
STAA dd,Y 010001
STAB dd,X 010010
STAB dd,Y 010011
SHFB_L 011110
SHFB_R 011111
B * 2 => B
B/2 => B
100011 Y[ ] => B AddrSel = Y
100101 A => X[ ] AddrSel = X R_/W = 0
100111 A => Y[ ] AddrSel = Y R_/W = 0
101001 B => X[ ] AddrSel = X R_/W = 0
101011 B => Y[ ] AddrSel = Y R_/W = 0 Back to State0 Back to State0
EEL 3701 Revision 0
EEL 3701 Revision 0
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Branch Instructions:
BEQ addr 100000 BNE addr 100001
Additional Instructions:
INX 110000
INY 110001
Z = 1?
Z = 0?
N INC X INC Y
101100 addr => PCL
101101 INC PC
101110 addr => PCL
101111 INC PC Back to State0
Back to State0
BN addr 100010
BP addr 100011
N = 1?
N = 0?
110000 addr => PCL
110001 INC PC
110010 addr => PCL
110011 INC PC
Back to State0
EEL 3701 Revision 0
Drs. Gugel and Schwartz 10-Nov-10 ADDR SEL ADDR SEL [1..0] 00 00 00 00 00 00 00 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 01 00 00 00 00 00 00 00 00 00 01 01 00 00 X,Y Loading X Y LD LD L/U L/U 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 00 01 00 00 00 00 10 00 01 00 00 00 00 00 00 10 00 01 00 00 00 00 00 Disp Regs XD_LD YD_LD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Pres State
G-CPU Controller Next State Table

Opcode
Flags
Next State
Mux Select MSA [1..0] 01 01 10 01 00 01 01 01 01 01 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 MSB [1..0] 10 01 10 10 10 10 00 10 10 10 10 10 10 10 00 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 MSC [3..0] 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Control IR LD 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R /W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Q[5..0] 000000 000001 000001 000001 000010 000001 000011 000001 000100 000101 000110 000001 000111 001000 001001 000001 001010 001011 001100 000001 001101 001110 001111 000001 010000 010001 000001 010010 010011 000001 010100 010101 010110 010111 000001 011000
IR[5..0] ****** 000000 000001 000010 ****** 000011 ****** 000100 ****** ****** ****** 000101 ****** ****** ****** 000110 ****** ****** ****** 000111 ****** ****** ****** 001000 ****** ****** 001001 ****** ****** 001010 ****** ****** ****** ****** 001011 ******
ZN ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **
D[5..0] 000001 000000 000000 000010 000000 000011 000000 000100 000101 000110 000000 000111 001000 001001 000000 001010 001011 001100 000000 001101 001110 001111 000000 010000 010001 000000 010010 010011 000000 010100 010101 010110 010111 000000 011000 011001
REG INC PC MAR XY 0000 1000 1000 1000 1000 1000 1000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1000 1000 1000 1000 1000 1000 1000 1000 0100 0000 1000 1000
PC PC LD L/U 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
MAR MAR LD L/U 00 00 00 00 00 00 00 00 10 01 00 00 10 01 00 00 10 01 00 00 10 01 00 00 00 00 00 00 00 00 10 01 00 00 00 10
Present State Function generic instruction fetch Transfer A to B (TAB) Transfer B to A (TBA) LDAA #data, state 1 LDAA #data, state 2 LDAB #data, state 1 LDAB #data, state 3 LDAA addr, state 1 LDAA addr, state 4 LDAA addr, state 5 LDAA addr, state 6 LDAB addr, state 1 LDAB addr, state 7 LDAB addr, state 8 LDAB addr, state 9 STAA addr, state 1 STAA addr, state A STAA addr, state B STAA addr, state C STAB addr, state 1 STAB addr, state D STAB addr, state E STAB addr, state F LDX #data, state 1 LDX #data, state 10 LDX #data, state 11 LDY #data, state 1 LDY #data, state 12 LDY #data, state 13 LDX addr, state 1 LDX addr, state 14 LDX addr, state 15 LDX addr, state 16 LDX addr, state 17 LDY addr, state 1 LDY addr, state 18
EEL 3701 Revision 0
Drs. Gugel and Schwartz 10-Nov-10 ADDR SEL ADDR SEL [1..0] 00 01 01 00 00 10 00 00 11 00 00 10 00 00 11 00 00 10 00 00 11 00 00 10 00 00 11 00 00 00 00 00 00 00 00 00 X,Y Loading X Y LD LD L/U L/U 00 00 00 10 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Disp Regs XD_LD YD_LD 00 00 00 00 10 00 00 01 00 00 10 00 00 01 00 00 10 00 00 01 00 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00
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Pres State

Opcode
Flags
Next State
Mux Select MSA [1..0] 01 01 01 01 01 00 01 01 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 11 01 11 01 11 01 11 01 11 MSB [1..0] 10 10 10 10 10 10 10 10 10 10 10 00 10 10 00 10 10 10 10 10 10 10 10 10 10 10 10 10 11 10 11 10 11 10 11 10 MSC [3..0] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0000 0001 0001 0010 0010 0011 0011 0100 0100 0101 0110 0111
Control IR LD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R /W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1
Q[5..0] 011001 011010 011011 000001 011100 011101 000001 011110 011111 000001 100000 100001 000001 100010 100011 000001 100100 100101 000001 100110 100111 000001 101000 101001 000001 101010 101011 000001 000001 000001 000001 000001 000001 000001 000001 000001
IR[5..0] ****** ****** ****** 001100 ****** ****** 001101 ****** ****** 001110 ****** ****** 001111 ****** ****** 010000 ****** ****** 010001 ****** ****** 010010 ****** ****** 010011 ****** ****** 010100 010101 010110 010111 011000 011001 011010 011011 011100
ZN ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **
D[5..0] 011010 011011 000000 011100 011101 000000 011110 011111 000000 100000 100001 000000 100010 100011 000000 100100 100101 000000 100110 100111 000000 101000 101001 000000 101010 101011 000000 000000 000000 000000 000000 000000 000000 000000 000000 000000
REG INC PC MAR XY 1000 0100 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 0000 1000 1000 1000 1000 1000 1000 1000 1000 1000
PC PC LD L/U 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
MAR MAR LD L/U 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Present State Function LDY addr, state 19 LDY addr, state 1A LDY addr, state 1B LDAA dd,X state 1 LDAA dd,X state 1C LDAA dd,X state 1D LDAA dd,Y state 1 LDAA dd,Y state 1E LDAA dd,Y state 1F LDAB dd,X state 1 LDAB dd,X state 20 LDAB dd,X state 21 LDAB dd,Y state 1 LDAB dd,Y state 22 LDAB dd,Y state 23 STAA dd,X state 1 STAA dd,X state 24 STAA dd,X state 25 STAA dd,Y state 1 STAA dd,Y state 26 STAA dd,Y state 27 STAB dd,X state 1 STAB dd,X state 28 STAB dd,X state 29 STAB dd,Y state 1 STAB dd,Y state 2A STAB dd,Y state 2B SUM_BA state 1 SUM_AB state 1 AND_BA state 1 AND_AB state 1 OR_BA state 1 OR_AB state 1 COMA state 1 COMB state 1 SHFA_L state 1
EEL 3701 Revision 0
Drs. Gugel and Schwartz 10-Nov-10 ADDR SEL ADDR SEL [1..0] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 X,Y Loading X Y LD LD L/U L/U 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Disp Regs XD_LD YD_LD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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Pres State

Opcode
Flags
Next State
Mux Select MSA [1..0] 11 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 MSB [1..0] 10 11 11 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 MSC [3..0] 1000 1001 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Control IR LD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R /W 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Q[5..0] 000001 000001 000001 000001 000001 101100 101101 000001 000001 101110 101111 000001 000001 110000 110001 000001 000001 110010 110011 000001 000001
IR[5..0] 011101 011110 011111 100000 100000 ****** ****** 100001 100001 ****** ****** 100010 100010 ****** ****** 100011 100011 ****** ****** 110000 110001
ZN ** ** ** 1* 0* ** ** 0* 1* ** ** *1 *0 ** ** *0 *1 ** ** ** **
D[5..0] 000000 000000 000000 101100 101101 000000 000000 101110 101111 000000 000000 110000 110001 000000 000000 110010 110011 000000 000000 000000 000000
REG INC PC MAR XY 1000 1000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1000 1000 0000 1000 1010 1001
PC PC LD L/U 00 00 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00 10 00 00 00
MAR MAR LD L/U 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Present State Function SHFA_R state 1 SHFB_L state 1 SHFB_R state 1 BEQ addr state 1 BEQ addr state 1 BEQ addr state 2C BEQ addr state 2D BNE addr state 1 BNE addr state 1 BNE addr state 2E BNE addr state 2F BN addr state 1 BN addr state 1 BN addr state 30 BN addr state 31 BP addr state 1 BP addr state 1 BP addr state 32 BP addr state 33 Increment X (INX) Increment Y (INY)
Date: November 10, 2010
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/computer.bdf
Project: computer
CPU
MCLK /RESET
INPUT VCC INPUT VCC
cpu
CLOCK /RESET
MCLK
External Memory
ADDR[15..0] R_/W DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 A[7..0] B[7..0] PC[15..0] MAR[15..0] X[15..0] Y[15..0] STATE[5..0] IR[5..0] ALU[7..0] ADDR_SEL[1..0] /IR_LD XDISP[7..0] YDISP[7..0] ZERO_FLAG NEG_FLAG MSC[3..0] ADDR[15..0] R_/W DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 A[7..0] B[7..0]
OUTPUT OUTPUT BIDIR VCC
R_/W ADDR[15..0] DATA[7..0]
CLK /RESET MCLK
ADDR12 ADDR13 ADDR14 ADDR15 R_/W
BAND4
AND2
ROM_Enable
31 32
ADDR12 ADDR13 ADDR14 ADDR15
NOT
BAND4
36
RAM_Enable
37
Simulation/Debug Purposes
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
ROM_Enable ROM_OUT[7..0]
TRI
RAM_RD_En
DATA[7..0]
RAM_OUT[7..0]
TRI
DATA[7..0]
inst4
inst15
A[7..0] B[7..0] X[15..0] Y[15..0] STATE[5..0] ALU[7..0] XDISP[7..0] YDISP[7..0] IR[5..0]
R_/W
X[15..0] Y[15..0] STATE[5..0] IR[5..0] ALU[7..0]
NOT AND2
AND2
RAM_WR_EN inst7
R_/W RAM_Enable inst14
RAM_RD_EN
RAM_Enable
File=eprom.mif
altsyncram0 ADDR[11..0] address[11..0]
4096 Word(s) RAM
OUTPUT OUTPUT OUTPUT
Z_FLG N_FLG MSC[3..0]
XDISP[7..0] YDISP[7..0] Z_FLG N_FLG MSC[3..0]
q[7..0] ROM_OUT[7..0]
MCLK
clock
inst Block Type: AUTO
File=sram.mif
OUTPUT
CLOCK
inst13
altsyncram1
4096 Word(s) RAM
OUTPUT OUTPUT
ROM_Enable ROM_OUT[7..0]
DATA[7..0] ADDR[11..0]
VCC TFF VCC TFF VCC
data[7..0] address[11..0] wren clock

inst11 Block Type: AUTO
q[7..0]
RAM_OUT[7..0]
RAM_WR_EN PRN T MCLK CLRN inst3 Q MCLK CLRN inst2 T PRN Q CLOCK MCLK
OUTPUT OUTPUT OUTPUT OUTPUT
RAM_Enable RAM_RD_EN RAM_WR_EN RAM_OUT[7..0]
VCC
Memory Map
EPROM Range = $0000 to $0FFF (read only) SRAM Range = $1000 to $1FFF (read/write)
Page 1 of 1
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/cpu/cpu.bdf
Project: computer
MCLK CLK /RESET
INPUT VCC INPUT VCC INPUT VCC
CPU ASM Controller

controller
CLK /RESET ZERO_FLAG NEG_FLAG IR[5..0]
MCLK
OUTPUT OUTPUT
ADDR[15..0] R_/W
Data Bus Tri-State Creation

R_/W
NOT
CLK /RESET ZERO_FLAG NEG_FLAG IR[5..0] MCLK
73 ALU[7..0]
TRI
DATA[7..0]
65
BIDIR VCC OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
DATA[7..0] A[7..0] B[7..0] PC[15..0] MAR[15..0] X[15..0] Y[15..0] STATE[5..0] IR[5..0] ALU[7..0] ADDR_SEL[1..0] /IR_LD XDISP[7..0] YDISP[7..0] ZERO_FLAG NEG_FLAG MSC[3..0] inst4
MSA[1..0] MSB[1..0] MSC[3..0] PC_INC /PC_LD_LOWER /PC_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER /IR_LD R_/W ADDR_SEL1 ADDR_SEL0 XD_LD YD_LD Q[5..0] ADDRESS[13..0] DATA[31..0]
MSA[1..0] MSB[1..0] MSC[3..0] PC_INC /PC_LD_LOWER /PC_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER /IR_LD R_/W ADDR_SEL1 ADDR_SEL0 XD_LD YD_LD STATE[5..0]
Instruction Register (IR)

ir
CLK /RESET /IR_LD DATA[5..0] IR[5..0] CLK /RESET /IR_LD DATA[5..0]
inst7
Program Counter (PC) & Memory Address Register (MAR) & Index Regs (X,Y)
pc_mar_ix
CLK /RESET DATA[7..0] PC_INC /PC_LD_LOWER /PC_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER ADDR_SEL0 ADDR_SEL1 XD_LD YD_LD CLK /RESET DATA[7..0] PC_INC /PC_LD_L /PC_LD_U X_INC /X_LD_L /X_LD_U Y_INC /Y_LD_L /Y_LD_U MAR_INC /MAR_LD_L /MAR_LD_U ADDR_SEL0 ADDR_SEL1 XD_LD YD_LD
inst5
IR[5..0]
ADDR[15..0] PC[15..0] MAR[15..0] X[15..0] Y[15..0] XDISP[7..0] YDISP[7..0]
ADDR[15..0] PC[15..0] MAR[15..0] X[15..0] Y[15..0] XDISP[7..0] YDISP[7..0]
Arithmetic Logic Unit (ALU)

alu
CLK /RESET MSA[1..0] MSB[1..0] MSC[3..0] DATA[7..0] CLK /RESET MSA[1..0] MSB[1..0] MSC[3..0] DATA[7..0]
inst6
OUT[7..0] NEG_FLAG ZERO_FLAG REGA[7..0] REGB[7..0]
ALU[7..0] NEG_FLAG ZERO_FLAG A[7..0] B[7..0]
10
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/controller/controller.bdf
Project: computer
Controller Input & Output

CLK /RESET ZERO_FLAG NEG_FLAG IR[5..0]
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC
Controller Logic
altsyncram2 ADDRESS[13..0]
address[13..0]
16384 Word(s) RAM
Controller Outputs
DATA31
q[31..0]
WIRE
D5 D4 D3 D2
DATA[31..0]
175
DATA30 DATA29 DATA28
WIRE
177
WIRE
MCLK
clock
inst Block Type: AUTO
176
WIRE
MSA[1..0] MSB[1..0] MSC[3..0] MCLK

INPUT VCC
178
File=controller_rom.mif
DATA27 DATA26
WIRE
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
PC_INC /PC_LD_LOWER /PC_LD_UPPER MAR_INC /MAR_LD_LOWER /MAR_LD_UPPER X_INC /X_LD_LOWER /X_LD_UPPER Y_INC /Y_LD_LOWER /Y_LD_UPPER CLRN 125
VCC
D1 D0 MSA1 MSA0
180
WIRE
ASM State Generation
179
DATA25 DATA24
WIRE
155
WIRE
154
DFF
D5 CLK
PRN D Q
Q5 DATA23 DATA22 DATA21

WIRE
MSB1 MSB0 MSC3 MSC2
157
WIRE
/RESET
/IR_LD
VCC
156
WIRE
158
R_/W ADDR_SEL1 ADDR_SEL0 XD_LD CLRN YD_LD 126

DFF
DATA20 D4 CLK
PRN D Q
WIRE
159
Q4 DATA19 DATA18 DATA17

WIRE
MSC1 MSC0 /IR_LD R_/W
161
WIRE
/RESET
168
NOT VCC
Debug Purposes
184
Q[5..0] ADDRESS[13..0] DATA[31..0]
DATA16
DFF
WIRE
D3 CLK
37
PRN D Q
Q3 DATA15 DATA14
162
WIRE
CLRN
PC_INC MAR_INC X_INC Y_INC
163
WIRE
Controller Inputs (State, Flags, Instruction)

Q5 Q4
WIRE
/RESET
VCC
165
DATA13 DATA12
WIRE
ADDRESS13
DFF
164
WIRE
140
WIRE
ADDRESS12
D2 CLK
38
PRN D Q
Q2
167
141 CLRN
DATA11 DATA10
WIRE
ADDR_SEL1 ADDR_SEL0 /PC_LD_LOWER /PC_LD_UPPER
Q3 Q2 Q1 Q0
WIRE
ADDRESS11 /RESET ADDRESS10
166
WIRE
142
WIRE
169
VCC
143
WIRE
DATA9 DATA8
NOT
ADDRESS9
DFF
185
NOT
144
WIRE
ADDRESS8
D1 CLK
39
PRN D Q
Q1 DATA7 DATA6
186
145
NOT
CLRN
/MAR_LD_LOWER /MAR_LD_UPPER /X_LD_LOWER /X_LD_UPPER
IR5 IR4 IR3 IR2
WIRE
ADDRESS7 /RESET ADDRESS6
187
NOT
148
WIRE
188
VCC
149
WIRE
fc
DATA5 DATA4
NOT
ADDRESS5
DFF
189
NOT
150
WIRE
ADDRESS4
D0 CLK
40
PRN D Q
Q0
190
151 CLRN
DATA3 DATA2 DATA1
NOT
/Y_LD_LOWER /Y_LD_UPPER XD_LD YD_LD
IR1 IR0 ZERO_FLAG NEG_FLAG
WIRE
ADDRESS3 ADDRESS2 ADDRESS1
/RESET
191
NOT
152
WIRE
192
WIRE
153
WIRE
202
198
WIRE
DATA0 ADDRESS0
WIRE
203
199
11
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/ir/ir.bdf
Project: computer
Instruction Register (IR)

CLK /RESET /IR_LD DATA[5..0]
INPUT VCC INPUT VCC INPUT VCC INPUT VCC
DATA0 IR0 IR_LD

1
21mux
A B S
DFF
VCC
Y MULTIPLEXER
13
PRN
IR0
CLK /RESET DATA1 IR1 21mux

A B S
2
CLRN
OUTPUT
IR[5..0]
10
DFF
VCC
/IR_LDNOT
54
IR_LD
Y MULTIPLEXER
14
PRN
IR1
CLRN
DATA2 IR2
21mux
A B S
30
DFF
32
VCC
Y MULTIPLEXER
34
PRN
IR2
CLRN
DATA3 IR3
21mux
A B S
31
DFF
33
VCC
Y MULTIPLEXER
35
PRN
IR3
CLRN
DATA4 IR4
21mux
A B S
36
DFF
40
VCC
Y MULTIPLEXER
44
PRN
IR4
CLRN
DATA5 IR5
21mux
A B S
37
DFF
41
VCC
Y MULTIPLEXER
45
PRN
IR5
CLRN
12

Mux A, Mux B, Reg A, Reg B Block
VCC
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/alu/alu.bdf
Mux C Block
VCC
Project: computer
98
MSA0 MSA1 DATA0 REGA0 REGB0 OUT0 DATA1 REGA1 REGB1 OUT1
138
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
97 PRN Q
CLK
REGA0 MSB0 MSB1 DATA0 REGA0 REGB0 OUT0
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
137
GND
DFF
CLK
PRN
REGB0
252
GND
CLRN 114
CLRN 113
1Y 2Y
A0 A1
/RESET
VCC
99
DFF
1Y 2Y
B0 B1
/RESET
VCC
100
DFF
CLK
PRN
REGA1
MULTIPLEXER
CLRN 116
DATA1 REGA1 REGB1 OUT1
CLK
PRN
REGB1
/RESET
VCC
MULTIPLEXER
CLRN 115
129
/RESET
VCC
GD MSC3 MSC2 MSC1 MSC0 REGA0 REGB0 SUM0 AND0 OR0 NEGA0 NEGB0 GD REGA1 GD REGB1
GD
161mux
GN SEL3 SEL2 SEL1 SEL0 IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 IN10 IN11 IN12 IN13 IN14 IN15
194
OUT
OUT0
GD MSC3 MSC2 MSC1 MSC0 REGA1 REGB1 SUM1 AND1 OR1 NEGA1 NEGB1 REGA0 REGA2 REGB0 REGB2
GD
161mux
195
OUT
OUT1
GD
161mux
197
OUT
OUT2
GD
161mux
196
OUT
OUT3
130
102
139
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
101 PRN Q
CLK
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
140
DFF
CLK
PRN
REGB2
CLRN 118
CLRN 117
1Y 2Y
A2 A3
/RESET
VCC
104
DFF
1Y 2Y
B2 B3
/RESET
VCC
103
DFF
CLK
PRN
REGA3
MULTIPLEXER
CLRN 119
CLK
PRN
REGB3
MULTIPLEXER
CLRN 120
132
/RESET
131
VCC GND
/RESET
VCC
106
MSA0 MSA1
DATA4 REGA4 REGB4 OUT4 DATA5 REGA5 REGB5 OUT5
141
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
105 PRN Q
CLK
REGA4
MSB0 MSB1
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
142
GND
DFF
CLK
PRN
REGB4
CLRN 122
CLRN 121 GD
161mux
201
OUT
OUT4
GD
161mux
200
OUT
OUT5
GD
161mux
199
OUT
OUT6
GD MSC3 MSC2 MSC1 MSC0 REGA7 REGB7 SUM7 AND7 OR7 NEGA7 NEGB7 REGA6 GD REGB6 GD
GD
161mux
198
OUT
OUT7
1Y 2Y
A4 A5
/RESET
VCC
108
DFF
1Y 2Y
B4 B5
/RESET
VCC
107
DFF
CLK
PRN
REGA5
MULTIPLEXER
CLRN 123
fs
CLK
PRN
REGB5
/RESET
VCC
MULTIPLEXER
CLRN 124
134
/RESET
VCC
133
110
144
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
109 PRN Q
CLK
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
143
DFF
CLK
PRN
REGB6
CLRN 126
CLRN 125
1Y 2Y
A6 A7
/RESET
VCC
112
DFF
1Y 2Y
B6 B7
/RESET
VCC
111
DFF
CLK
PRN
REGA7
MULTIPLEXER
CLRN 128
CLK
PRN
REGB7
MSC3:0 Selection __________________ 0000 REGA 0001 REGB 0010 Sum(A,B) 0011 AND(A,B) 0100 OR(A,B) 0101 COMA 0110 COMB 0111 SHFA_Left 1000 SHFA_Right 1001 SHFB_Left 1010 SHFB_Right
MULTIPLEXER
CLRN 127
136
/RESET
Sum & Carry Flag Generation Input & Output Signals

164 CLK /RESET
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC GND
135
GND
AND Generation
REGA0 REGB0
AND2
/RESET
See the next four pages for expanded views

Z & N Flag Generation
REGA0 REGA1 REGA2 REGA3 REGA4 REGA5 REGA6 REGA7
NOR8
OR Generation
REGA0 REGB0 REGA1 REGB1 REGA2 REGB2 REGA3 REGB3 REGA4 REGB4 REGA5 REGB5 REGA6 REGB6 REGA7 REGB7
OR2
Negate A
REGA0
NOT
Negate B
REGB0
NOT
74283
CIN A1 B1 A2 B2 A3 B3 A4 B4
162
AND0
204
AND2
OR0
212
OR2
NEGA0
NEGB0
236
244
MSA[1..0] MSB[1..0] MSC[3..0] DATA[7..0]

REGA0 REGB0 REGA1 REGB1 REGA2 REGB2 REGA3 REGB3
SUM1 SUM2 SUM3 SUM4 COUT
SUM0 SUM1 SUM2 SUM3 COUT0
AND1
205
AND2
OR1
229
OR2
REGA1
NOT
NEGA1
REGB1
NOT
NEGB1
237
245
ZERO_FLAG
AND2
206
AND2
OR2
230
OR2
REGA2
NOT
NEGA2
REGB2
NOT
NEGB2
238
246
161
AND3
207
AND2
OR3
231
OR2
REGA3
NOT
NEGA3
REGB3
NOT
NEGB3 REGA7
WIRE
OUT[7..0] NEG_FLAG ZERO_FLAG
4 BIT ADDER
239
247
Debug Signals
OUTPUT OUTPUT
REGA[7..0] REGB[7..0]
COUT0 REGA4 REGB4 REGA5 REGB5 REGA6 REGB6 REGA7 REGB7

163
74283
AND4
208
AND2
OR4
232
OR2
REGA4
NOT
NEGA4
REGB4
NOT
NEGB4
NEG_FLAG
240
248
265
REGA5 REGB5 REGA6 REGB6 REGA7 REGB7
AND5
209
AND2
OR5
233
OR2
REGA5
NOT
NEGA5
REGB5
NOT
NEGB5
241
249
AND6
210
AND2
OR6
234
OR2
REGA6
NOT
NEGA6
REGB6
NOT
NEGB6
242
250
AND7
211
OR7
235
REGA7
NOT
NEGA7
REGB7
NOT
NEGB7
4 BIT ADDER
243
251
13
Date: April 21, 2010
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-s10/alu/alu.bdf*
Mux A, Mux B, Reg A, Reg B Block
98
VCC
Project: computer
138
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
97 PRN Q
VCC
CLK
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
137
GND
DFF
CLK
PRN
REGB0
252
GND
CLRN 114
CLRN 113
1Y 2Y
A0 A1
/RESET
99
DFF VCC
1Y 2Y
B0 B1
/RESET
100
DFF VCC
CLK
PRN
REGA1
MULTIPLEXER
CLRN 116
CLK
PRN
REGB1
/RESET
102
VCC
MULTIPLEXER
CLRN 115
129
/RESET
101
VCC
130
139
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
CLK
PRN
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
140
DFF
CLK
PRN
REGB2
CLRN 118
CLRN 117
1Y 2Y
A2 A3
/RESET
104
DFF VCC
1Y 2Y
B2 B3
/RESET
103
DFF VCC
CLK
PRN
REGA3
MULTIPLEXER
CLRN 119
CLK
PRN
REGB3
MULTIPLEXER
CLRN 120
132
/RESET
131 106
VCC GND
/RESET
VCC
MSA0 MSA1
DATA4 REGA4 REGB4 OUT4 DATA5 REGA5 REGB5 OUT5
141
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
105 PRN Q
CLK
REGA4
MSB0 MSB1
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
142
GND
DFF
CLK
PRN
REGB4
CLRN 122
CLRN 121
1Y 2Y
A4 A5
/RESET
108
DFF VCC
1Y 2Y
B4 B5
/RESET
107
DFF VCC
CLK
PRN
REGA5
MULTIPLEXER
CLRN 123
CLK
PRN
REGB5
/RESET
110
VCC
MULTIPLEXER
CLRN 124
134
/RESET
109
VCC
133
144
GND
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
DFF
CLK
PRN
74153
A B 1GN 1C0 1C1 1C2 1C3 2GN 2C0 2C1 2C2 2C3
143
DFF
CLK
PRN
REGB6
CLRN 126
CLRN 125
1Y 2Y
A6 A7
/RESET
112
DFF VCC
1Y 2Y
B6 B7
/RESET
111
DFF VCC
CLK
PRN
REGA7
MULTIPLEXER
CLRN 128
CLK
PRN
REGB7
MULTIPLEXER
CLRN 127
136
/RESET /RESET
14
Mux C Block
Project: computer
252
GND
GD MSC3 MSC2 MSC1 MSC0 REGA0 REGB0 SUM0 AND0 OR0 NEGA0 NEGB0 GD REGA1 GD REGB1
GD
161mux
194
OUT
OUT0
GD
161mux
195
OUT
OUT1
GD
161mux
197
OUT
OUT2
GD
161mux
196
OUT
OUT3
GD
161mux
201
OUT
OUT4
GD
161mux
200
OUT
OUT5
GD
161mux
199
OUT
OUT6
GD MSC3 MSC2 MSC1 MSC0 REGA7 REGB7 SUM7 AND7 OR7 NEGA7 NEGB7 REGA6 GD REGB6 GD
GD
161mux
198
OUT
OUT7
fs
MSC3:0 Selection __________________ 0000 REGA 0001 REGB 0010 Sum(A,B) 0011 AND(A,B) 0100 OR(A,B) 0101 COMA 0110 COMB 0111 SHFA_Left 1000 SHFA_Right 1001 SHFB_Left 1010 SHFB_Right
15
Project: computer
Sum & Carry Flag Generation Input & Output Signals

164 CLK /RESET
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC GND
AND Generation
REGA0 REGB0
AND2
OR Generation
REGA0 REGB0 REGA1 REGB1 REGA2 REGB2 REGA3 REGB3 REGA4 REGB4 REGA5 REGB5 REGA6 REGB6 REGA7 REGB7
OR2
74283
162
AND0
204
AND2
OR0
212
OR2
MSA[1..0] MSB[1..0] MSC[3..0] DATA[7..0]

AND1
205
AND2
OR1
229
OR2
AND2
206
AND2
OR2
230
OR2
AND3
207
AND2
OR3
231
OR2
OUT[7..0] NEG_FLAG ZERO_FLAG
4 BIT ADDER
Debug Signals
OUTPUT OUTPUT
REGA[7..0] REGB[7..0]
COUT0 REGA4 REGB4 REGA5 REGB5 REGA6 REGB6 REGA7 REGB7
74283
AND4
208
AND2
OR4
232
OR2
REGA5 REGB5 REGA6 REGB6 REGA7 REGB7
AND5
209
AND2
OR5
233
OR2
AND6
210
AND2
OR6
234
OR2
AND7
211
OR7
235
163 4 BIT ADDER
16
Project: computer
Negate A
REGA0
NOT
Negate B
REGB0
NOT
Z & N Flag Generation

REGA0 REGA1 REGA2 REGA3 REGA4 REGA5 REGA6 REGA7
NOR8
NEGA0
NEGB0
236
244
REGA1
NOT
NEGA1
REGB1
NOT
NEGB1
237
245
ZERO_FLAG
REGA2
NOT
NEGA2
REGB2
NOT
NEGB2
238
246
161
REGA3
NOT
NEGA3
REGB3
NOT
NEGB3 REGA7
WIRE
239
247
REGA4
NOT
NEGA4
REGB4
NOT
NEGB4
NEG_FLAG
240
248
265
REGA5
NOT
NEGA5
REGB5
NOT
NEGB5
241
249
REGA6
NOT
NEGA6
REGB6
NOT
NEGB6
242
250
REGA7
NOT
NEGA7
REGB7
NOT
NEGB7
243
251
17

Program Counter Register
/PC_LD_L DATA0 DATA1 DATA2 DATA3 PC_INC /RESET CLK
3
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/pc_mar_ix/pc_mar_ix.bdf
Memory Address Register
74161
LDN A B C D ENT ENP CLRN
Project: computer
X Index Register
/X_LD_L DATA0 DATA1 DATA2 DATA3 X_INC /RESET CLK
123
Y Index Register
/Y_LD_L DATA0 DATA1 DATA2 DATA3 Y_INC /RESET CLK
127
X Displ. Generation
Y Displ. Generation
74161
QA QB QC QD RCO
PC0 PC1 PC2 PC3 PC_TC0
/MAR_LD_L DATA0 DATA1 DATA2 DATA3 MAR_INC /RESET CLK

171
74161
74161
GND
QA QB QC QD RCO
MAR0 MAR1 MAR2 MAR3 MAR_TC0
QA QB QC QD RCO
X0 X1 X2 X3 X_TC0
QA QB QC QD RCO
Y0 Y1 Y2 Y3 Y_TC0
74283
131
GND
74283
140
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER
X0 XDISP0 X1 XDISP1 X2 XDISP2 X3 XDISP3
XA0 XA1 XA2 XA3
Y0 YDISP0 Y1 YDISP1 Y2 YDISP2 Y3 YDISP3
YA0 YA1 YA2 YA3
/PC_LD_L DATA4 DATA5 DATA6 DATA7 PC_TC0 /RESET CLK

4
74161
QA QB QC QD RCO
/MAR_LD_L DATA4 DATA5 DATA6 DATA7 MAR_TC0 /RESET CLK

172
74161
QA QB QC QD RCO
/X_LD_L DATA4 DATA5 DATA6 DATA7 X_TC0 /RESET CLK

124
74161
QA QB QC QD RCO
X4 X5 X6 X7 X_TC1
/Y_LD_L DATA4 DATA5 DATA6 DATA7 Y_TC0 /RESET CLK

128
74161
4 BIT ADDER
4 BIT ADDER
74283
QA QB QC QD RCO
74283 XA4 XA5 XA6 XA7 Y4 YDISP4 Y5 YDISP5 Y6 YDISP6 Y7 YDISP7

141
Y4 Y5 Y6 Y7 Y_TC1
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER

133
YA4 YA5 YA6 YA7
/PC_LD_U DATA0 DATA1 DATA2 DATA3 PC_TC1 /RESET CLK

32
74161
4 BIT ADDER
4 BIT ADDER
QA QB QC QD RCO
/MAR_LD_U DATA0 DATA1 DATA2 DATA3 MAR_TC1 /RESET CLK

173
74161
QA QB QC QD RCO
/X_LD_U DATA0 DATA1 DATA2 DATA3 X_TC1 /RESET CLK

125
74161
QA QB QC QD RCO
X8 X9 X10 X11 X_TC2
/Y_LD_U DATA0 DATA1 DATA2 DATA3 Y_TC1 /RESET CLK

129
74161
74283
QA QB QC QD RCO
74283 Y8 XA8 XA9 XA10 XA11

142
Y8 Y9 Y10 Y11 Y_TC2
X8 X9 X10 X11
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER
135
Y9 Y10 Y11
YA8 YA9 YA10 YA11
4 BIT ADDER
4 BIT ADDER
74161
QA QB QC QD RCO
PC12 PC13 PC14 PC15

174
74161
QA QB QC QD RCO
MAR12 MAR13 MAR14 MAR15

126
74161
QA QB QC QD RCO
X12 X13 X14 X15

130
74161
74283 Y12 Y13 Y14 Y15 X12 X13 X14 X15

136
GND
74283 Y12 XA12 XA13 XA14 XA15

143
GND
QA QB QC QD RCO
Y13 Y14 Y15
YA12 YA13 YA14 YA15
CLK COUNTER 33
CLK COUNTER
CLK COUNTER
CLK COUNTER
4 BIT ADDER
4 BIT ADDER
xdr_ydr
Input / Output Signals

CLK /RESET DATA[7..0] PC_INC /PC_LD_L /PC_LD_U X_INC /X_LD_L /X_LD_U Y_INC /Y_LD_L /Y_LD_U MAR_INC /MAR_LD_L /MAR_LD_U
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC GND GND
Address Selection/Generation
CLK /RESET XD_LD YD_LD DATA[7..0]
CLK /RESET XD_LD YD_LD DATA[7..0]

inst1
XD[7..0] YD[7..0]
XDISP[7..0] YDISP[7..0]
GND
GND
MUX41 PC0 MAR0 XA0 YA0 ADDR_SEL1 ADDR_SEL0

155 INH D0 D1 D2 D3 S1 S0 Q

159 INH D0 D1 D2 D3 S1 S0 Q

164 INH D0 D1 D2 D3 S1 S0 Q

163 INH D0 D1 D2 D3 S1 S0 Q
ADDR0
ADDR4
ADDR8
ADDR12

156 INH D0 D1 D2 D3 S1 S0 Q

160 INH D0 D1 D2 D3 S1 S0 Q

166 INH D0 D1 D2 D3 S1 S0 Q

165 INH D0 D1 D2 D3 S1 S0 Q
ADDR1
ADDR5
ADDR9
ADDR13
ADDR_SEL0 ADDR_SEL1
____________________________ ADDR_SEL1:0 Addr Output 0 0 PC Register 0 1 MAR Register 1 0 X + Displ. 1 1 Y + Displ.

XD_LD YD_LD
OUTPUT INPUT VCC INPUT VCC

157 INH D0 D1 D2 D3 S1 S0 Q

161 INH D0 D1 D2 D3 S1 S0 Q

168 INH D0 D1 D2 D3 S1 S0 Q

167 INH D0 D1 D2 D3 S1 S0 Q
ADDR2
ADDR6
ADDR10
ADDR14
ADDR[15..0]
MUX41

162 INH D0 D1 D2 D3 S1 S0 Q

170 INH D0 D1 D2 D3 S1 S0 Q

169 INH D0 D1 D2 D3 S1 S0 Q
Debug Signals
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
PC[15..0] MAR[15..0] X[15..0] Y[15..0] XDISP[7..0] YDISP[7..0]
PC3 MAR3 XA3 YA3 ADDR_SEL1 ADDR_SEL0

158
INH D0 D1 D2 D3 S1 S0 Q
See the next three pages for expanded views

18
ADDR3
ADDR7
ADDR11
ADDR15

Program Counter Register
/PC_LD_L DATA0 DATA1 DATA2 DATA3 PC_INC /RESET CLK
3
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-s10/pc_mar_ix/pc_mar_ix.bdf*
Memory Address Register
74161
Project: computer
Y Index Register
/Y_LD_L DATA0 DATA1 DATA2 DATA3 Y_INC /RESET CLK
127
X Index Register
/X_LD_L DATA0 DATA1 DATA2 DATA3 X_INC /RESET CLK
123
74161
QA QB QC QD RCO
/MAR_LD_L DATA0 DATA1 DATA2 DATA3 MAR_INC /RESET CLK

171
74161
74161
QA QB QC QD RCO
QA QB QC QD RCO
X0 X1 X2 X3 X_TC0
QA QB QC QD RCO
Y0 Y1 Y2 Y3 Y_TC0
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER
/PC_LD_L DATA4 DATA5 DATA6 DATA7 PC_TC0 /RESET CLK

4
74161
QA QB QC QD RCO
/MAR_LD_L DATA4 DATA5 DATA6 DATA7 MAR_TC0 /RESET CLK

172
74161
QA QB QC QD RCO
/X_LD_L DATA4 DATA5 DATA6 DATA7 X_TC0 /RESET CLK

124
74161
QA QB QC QD RCO
X4 X5 X6 X7 X_TC1
/Y_LD_L DATA4 DATA5 DATA6 DATA7 Y_TC0 /RESET CLK

128
74161
QA QB QC QD RCO
Y4 Y5 Y6 Y7 Y_TC1
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER

32
74161
QA QB QC QD RCO

173
74161
QA QB QC QD RCO

125
74161
QA QB QC QD RCO
X8 X9 X10 X11 X_TC2

129
74161
QA QB QC QD RCO
Y8 Y9 Y10 Y11 Y_TC2
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER

33
74161
QA QB QC QD RCO
PC12 PC13 PC14 PC15

174
74161
QA QB QC QD RCO
MAR12 MAR13 MAR14 MAR15

126
74161
QA QB QC QD RCO
X12 X13 X14 X15

130
74161
QA QB QC QD RCO
Y12 Y13 Y14 Y15
CLK COUNTER
CLK COUNTER
CLK COUNTER
CLK COUNTER
19
Project: computer
X Displ. Generation
Y Displ. Generation
GND
74283
131
GND
74283
140
XA0 XA1 XA2 XA3
Y0 YDISP0 Y1 YDISP1 Y2 YDISP2 Y3 YDISP3
YA0 YA1 YA2 YA3
4 BIT ADDER
4 BIT ADDER
74283 X4 XDISP4 X5 XDISP5 X6 XDISP6 X7 XDISP7

133
74283 XA4 XA5 XA6 XA7 Y4 YDISP4 Y5 YDISP5 Y6 YDISP6 Y7 YDISP7

141
YA4 YA5 YA6 YA7
4 BIT ADDER
4 BIT ADDER
74283 X8 X9 X10 X11

135
74283 Y8 XA8 XA9 XA10 XA11

142
Y9 Y10 Y11
YA8 YA9 YA10 YA11
4 BIT ADDER
4 BIT ADDER
74283 X12 X13 X14 X15

136
GND
74283 Y12 XA12 XA13 XA14 XA15

143
GND
Y13 Y14 Y15
YA12 YA13 YA14 YA15
4 BIT ADDER
4 BIT ADDER
xdr_ydr
CLK /RESET XD_LD YD_LD DATA[7..0] CLK /RESET XD_LD YD_LD DATA[7..0]
inst1
XD[7..0] YD[7..0]
XDISP[7..0] YDISP[7..0]
20

Input / Output Signals
CLK /RESET DATA[7..0] PC_INC /PC_LD_L /PC_LD_U X_INC /X_LD_L /X_LD_U Y_INC /Y_LD_L /Y_LD_U MAR_INC /MAR_LD_L /MAR_LD_U
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC GND
Address Selection/Generation
Project: computer
GND
GND
GND

155 INH D0 D1 D2 D3 S1 S0 Q

159 INH D0 D1 D2 D3 S1 S0 Q

164 INH D0 D1 D2 D3 S1 S0 Q

163 INH D0 D1 D2 D3 S1 S0 Q
ADDR0
ADDR4
ADDR8
ADDR12

156 INH D0 D1 D2 D3 S1 S0 Q

160 INH D0 D1 D2 D3 S1 S0 Q

166 INH D0 D1 D2 D3 S1 S0 Q

165 INH D0 D1 D2 D3 S1 S0 Q
ADDR1
ADDR5
ADDR9
ADDR13
ADDR_SEL0 ADDR_SEL1
____________________________ ADDR_SEL1:0 Addr Output 0 0 PC Register 0 1 MAR Register 1 0 X + Displ. 1 1 Y + Displ.

XD_LD YD_LD
OUTPUT INPUT VCC INPUT VCC

157 INH D0 D1 D2 D3 S1 S0 Q

161 INH D0 D1 D2 D3 S1 S0 Q

168 INH D0 D1 D2 D3 S1 S0 Q

167 INH D0 D1 D2 D3 S1 S0 Q
ADDR2
ADDR6
ADDR10
ADDR14
ADDR[15..0]
MUX41

162 INH D0 D1 D2 D3 S1 S0 Q

170 INH D0 D1 D2 D3 S1 S0 Q

169 INH D0 D1 D2 D3 S1 S0 Q
Debug Signals
OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
PC[15..0] MAR[15..0] X[15..0] Y[15..0] XDISP[7..0] YDISP[7..0]
PC3 MAR3 XA3 YA3 ADDR_SEL1 ADDR_SEL0

158
INH D0 D1 D2 D3 S1 S0 Q
ADDR3
ADDR7
ADDR11
ADDR15
21
//mil.ufl.edu/ems/eel/3701/gcpu/gcpu-f10/xdr_ydr/xdr_ydr.bdf
Project: computer
CLK /RESET XD_LD
INPUT VCC INPUT VCC INPUT VCC INPUT VCC INPUT VCC
X Displacement Register (XDR)

XD0 DATA0 /XD_LD
7
Y Displacement Register (YDR)

YD0 DATA0 /YD_LD
38
21mux
A B S
DFF
13
VCC
21mux
A B S
DFF
46
VCC
Y MULTIPLEXER
19
PRN
XD0
Y MULTIPLEXER
54
PRN
YD0
YD_LD DATA[7..0]
OUTPUT
CLK /RESET
CLRN
CLK /RESET
CLRN
XD[7..0]
VCC VCC
OUTPUT
YD[7..0]
XD1 DATA1
XD_LD YD_LD
NOT
21mux
A B S
8
DFF
14
/XD_LD /YD_LD
Y MULTIPLEXER
20
PRN
XD1
YD1 DATA1
21mux
A B S
39
DFF
47
Y MULTIPLEXER
55
PRN
YD1
66
NOT
CLRN
VCC
CLRN
VCC
67
XD2 DATA2
21mux
A B S
9
DFF
15
Y MULTIPLEXER
21
PRN
XD2
YD2 DATA2
21mux
A B S
40
DFF
48
Y MULTIPLEXER
56
PRN
YD2
CLRN
VCC
CLRN
VCC
XD3 DATA3
21mux
A B S
10
DFF
16
Y MULTIPLEXER
22
PRN
XD3
YD3 DATA3
21mux
A B S
41
DFF
49
Y MULTIPLEXER
57
PRN
YD3
CLRN
VCC
CLRN
VCC
XD4 DATA4
21mux
A B S
11
DFF
17
Y MULTIPLEXER
23
PRN
XD4
YD4 DATA4
21mux
A B S
42
DFF
50
Y MULTIPLEXER
58
PRN
YD4
CLRN
VCC
CLRN
VCC
XD5 DATA5
21mux
A B S
12
DFF
25
Y MULTIPLEXER
24
PRN
XD5
YD5 DATA5
21mux
A B S
43
DFF
51
Y MULTIPLEXER
59
PRN
YD5
CLRN
CLRN
XD6 DATA6
21mux
A B S
26
DFF
27
VCC
Y MULTIPLEXER
28
PRN
XD6
YD6 DATA6
21mux
A B S
44
DFF
52
VCC
Y MULTIPLEXER
60
PRN
YD6
CLRN
VCC
CLRN
VCC
XD7 DATA7
21mux
A B S
29
DFF
31
Y MULTIPLEXER
33
PRN
XD7
YD7 DATA7
21mux
A B S
45
DFF
53
Y MULTIPLEXER
61
PRN
YD7
CLRN
CLRN
22

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University of Florida

Department of Electrical & Computer Engineering

EEL 3701 Revision 0

Drs. Gugel and Schwartz 10-Nov-10

G-CPU Block Diagram

IR5:0 Register IR5:0 6 CLK Z Flag N Flag

(Reset not shown due to space constraints)

Address Bus Mux 0

Program Counter (H/L)

Mem Addr Reg (H/L)

Drs. Gugel and Schwartz 10-Nov-10

Drs. Gugel and Schwartz 10-Nov-10

G-CPU Instruction Set

G-CPU Instruction Set

Data Movement Instructions:

ALU Related Instructions:

EEL 3701 Revision 0

Drs. Gugel and Schwartz 10-Nov-10

EEL 3701 Revision 0

Drs. Gugel and Schwartz 10-Nov-10

G-CPU Controller Flow Charts

G-CPU Controller Flow Charts

Data Movement Instructions:

000010 data => A INC_PC

000011 data => B INC_PC

000100 addrL => MARL INC PC

000101 addrH => MARH INC PC 000001

000110 addr[ ] => A AddrSel = MAR Back to State0

LDAB addr 000101

STAA addr 000110

STAB addr 000111

LDX #data 001000

LDY #data 001001

000111 addrL => MARL INC PC

001010 addrL => MARL INC PC

001101 addrL => MARL INC PC

010000 data => XL INC PC

010010 data => YL INC PC

001001 addr[ ] => B AddrSel = MAR

001100 A => addr[ ] AddrSel = MAR R_/W = 0

001111 B => addr[ ] AddrSel = MAR R_/W = 0 Back to State0

Instructions Listed on Next Pages

EEL 3701 Revision 0

Drs. Gugel and Schwartz 10-Nov-10

EEL 3701 Revision 0

Drs. Gugel and Schwartz 10-Nov-10

G-CPU Controller Flow Charts

G-CPU Controller Flow Charts

Data Movement Instructions (continued):

ALU Related Instructions:

010100 addrL => MARL INC PC

011000 010100 addrL => MARL INC PC

011100 dd => Xdisp INC PC

011110 dd => Ydisp INC PC

100000 dd => Xdisp INC PC

010101 addrH => MARH INC PC

011001 010101 addrH => MARH INC PC

011101 X[ ] => A AddrSel = X

011111 Y[ ] => A AddrSel = Y

100001 X[ ] => B AddrSel = X

010110 addr[ ] => XL AddrSel = MAR INC MAR

011010 010110 addr[ ] => YL AddrSel = MAR INC MAR

LDAB dd,Y 001111

STAA dd,X 010000