1.

Verilog Code for SR Flipflop module sr_ff(clk,reset,s,r,q,qb); parameter HOLD=2'b00, SET=2'b10, RESET=2'b01, INVALID=2'b11; input clk,reset,s,r; output reg q; output qb; always@(posedge clk or posedge reset ) begin if(reset) q<=1'b0; else begin case({s,r}) HOLD:q<=q; RESET:q<=0; SET:q<=1; INVALID:q<=1'bx; default:q<=q; endcase end end assign qb=~q; endmodule Test Bench Code for SR Flipflop: module sr_ff_tb(); reg clk, reset,s,r; wire q,qb; // Step 1. Define a parameter with name "cycle" which is equal to 10 parameter cycle=10; // Step 2. Instantiate the sr_ff design sr_ff SR1 (clk,reset,s,r,q,qb);

// Step 3. Understand the clock generation logic initial

begin

clk = 1'b0; forever #(cycle/2) clk=~clk;

end //Step 4. Write a task to reset dut task rst_dut(); begin reset=1'b1; #10; reset=1'b0; end endtask //Step 5. write a task to send input combinations. task din(input x,y); begin @(negedge clk); s=x; r=y; end endtask //Step 6. Run the test bench and assign inputs initial begin

End

rst_dut; din(0,0); din(0,1); din(1,0); din(1,1); din(1,0); din(0,0); din(0,1); din(1,1); din(0,1); #10; $finish;

// Step 4. Use $monitor to display the various inputs and outputs in batch mode initial $monitor("clk=%b,Input-> SR =%b%b, Reset = %b, Output-> Q =%b, Qbar=%b",clk,s,r, reset,q,qb); endmodule 2.Verilog Code for JK Flipflop module jk_ff(clk,reset,j,k,q,qb); parameter HOLD=2'b00, SET=2'b10, RESET=2'b01, TOGGLE=2'b11; input clk,reset,j,k; output reg q; output qb; always@(posedge clk or posedge reset ) begin if(reset) q<=1'b0; else begin case({j,k}) HOLD:q<=q; RESET:q<=0; SET:q<=1; TOGGLE:q<=~q; default:q<=q; endcase end end assign qb=~q; endmodule Test Bench Code for JK Flipflop: module jk_ff_tb(); reg clk, reset,j,k; wire q,qb;

// Step 1. Define a parameter with name "cycle" which is equal to 10 parameter cycle=10; // Step 2. Instantiate the sr_ff design jk_ff JK1 (clk,reset,j,k,q,qb); // Step 3. Understand the clock generation logic initial begin clk = 1'b0; forever #(cycle/2) clk=~clk;

end

//Step 4. Write a task to reset dut task rst_dut(); begin reset=1'b1; #10; reset=1'b0; end endtask //Step 5. write a task to send input combinations. task din(input x,y); begin @(negedge clk); j=x; k=y; end endtask //Step 6. Run the test bench and assign inputs initial begin

rst_dut; din(0,0); din(0,1); din(1,0); din(1,1); din(1,0);

end

din(0,0); din(0,1); din(1,1); din(0,1); #10; $finish;

// Step 7. Use $monitor to display the various inputs and outputs in batch mode initial $monitor("clk=%b, Input ->JK=%b%b, Reset = %b, Output ->Q =%b, Qbar=%b",clk,j,k, reset,q,qb); endmodule 3. Verilog Code for D Flipflop: module d_ff(clk,reset,d,q,qb); input clk,reset,d; output reg q; output qb; always@(posedge clk or posedge reset) begin if(reset) begin q<=1'b0; end else begin q<=d; end end assign qb=~q; endmodule Test Bench Code for D Flipflop: module d_ff_tb(); reg clk, reset, d; wire q,qb;
// Step 1. Define a parameter with name "cycle" which is equal to 10

parameter cycle=10;

// Step 2. Instantiate the dff design

d_ff D1 (clk,reset,d,q,qb);
// Step 3. Understand the clock generation logic

always

begin

end

clk = 1'b0; #(cycle/2) clk=1'b1; #(cycle/2);

//Step 4. Write a task to reset dut task rst_dut(); begin reset=1'b1; #10; reset=1'b0; end endtask //Step 5. write a task to send input combination. task din(input i); begin @(negedge clk); d=i; end endtask //Step 6. Run the test bench and assign inputs initial begin

rst_dut; din(0); din(1); din(0); din(1); din(1); rst_dut; din(0); din(1); #10; $finish;

end
// Step 5. Use $monitor to display the various inputs and outputs

initial $monitor("clk=%b,Input D = %b, Reset = %b, Output q =%b, ~q=%b",clk,d, reset,q,qb); endmodule 4. Verilog Code for MS Flipflop (using D Latch) Module d_latch (en,d,q); Input en d; Output reg q; always@(*) begin if(en) begin q=d; end end endmodule module ms_ff (clk,d,q,qb); input clk,d; output q,qb; wire w1; d_latch MASTER (~clk,d,w1); d_latch SLAVE (clk,w1,q); assign qb=~q; endmodule Test Bench Code for MS Flipflop module ms_ff_tb(); reg clk,d; wire q,qb;

// Step 1. Define a parameter with name "cycle" which is equal to 10

parameter cycle=10;
// Step 2. Instantiate the dff design

ms_ff MS1 (clk,d,q,qb);

// Step 3. Understand the clock generation logic

always begin clk = 1'b0; #(cycle/2) clk=1'b1; #(cycle/2);

end

//Step 4. write a task to send input combination. task din(input i); begin @(negedge clk); d=i; end endtask //Step 5. Run the test bench and assign inputs initial begin din(0); din(1); din(0); din(1); din(1); din(0); din(1); #10; $finish;

End
// Step 6. Use $monitor to display the various inputs and outputs

initial $monitor("clk=%b,Input D = %b,Output q =%b, ~q=%b",clk,d,q,qb); endmodule

5. Verilog code for T Flipflop: module t_ff(clk,reset,t,q,qb); parameter HOLD=1'b0, TOGGLE=1'b1; input clk,reset,t; output reg q; output qb; always@(posedge clk or posedge reset) begin if(reset) begin q<=1'b0; end else begin case(t) HOLD:q<=q; TOGGLE:q<=~q; default:q<=q; endcase end end assign qb=~q; endmodule T flipflop using D Flipflop:(first run with above code then with this) module t_ff (clk,reset,t,q,qb); input t,clk,reset; output q,qb; wire x; d_ff D1 (clk,reset,x,q,qb); xor X1 (x,t,q); endmodule TestBench Code for T Flipflop: module t_ff_tb(); reg clk, reset, t; wire q,qb;

// Step 1. Define a parameter with name "cycle" which is equal to 10

parameter cycle=10;
// Step 2. Instantiate the dff design

t_ff T1 (clk,reset,t,q,qb);
// Step 3. Understand the clock generation logic

always

begin

clk = 1'b0; #(cycle/2) clk=1'b1; #(cycle/2);

end //Step 4. Write a task to reset dut task rst_dut(); begin reset=1'b1; #10; reset=1'b0; end endtask //Step 5. write a task to send input combination. task din(input i); begin @(negedge clk); t=i; end endtask //Step 6. Run the test bench and assign inputs initial begin rst_dut; din(0); din(1); din(0); din(1); din(1); rst_dut; din(0); din(1); #10; $finish; end

// Step 5. Use $monitor to display the various inputs and outputs

Initial $monitor("clk=%b,Input D = %b, Reset = %b, Output q =%b, ~q=%b",clk,t, reset,q,qb); endmodule