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On2
b Combinational logic
Currstate
clk
State register
Nextstate
Combinational logic
Currstate
clk
State register
Nextstate
On3
ENTITY LaserTimer IS PORT (b: IN std_logic; x: OUT std_logic; Clk, Rst: IN std_logic ); END LaserTimer; ARCHITECTURE Beh OF LaserTimer IS TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); SIGNAL Currstate, Nextstate: Statetype; BEGIN CombLogic: PROCESS (Currstate, b) BEGIN ... END PROCESS CombLogic;
On1
On2
TYPE Statetype IS (S_Off, S_On1, S_On2, S_On3); Note: Enumeration lists all possible values for type
StateReg: PROCESS (Clk) BEGIN ... END PROCESS StateReg; END Beh;
Possible values for defined type Name of new type Type declaration
CombLogic Process
Sensitive to Currstate and input b
StateReg Process
Sensitive to Clk input
END PROCESS CombLogic; StateReg: PROCESS (Clk) BEGIN ... END PROCESS StateReg; END Beh;
b
x=1 On1 On2
b Combinational logic
Currstate
clk
State register
Nextstate
FSM outputs
FSM inputs
Ex:
clk
State register
Nextstate
FSM outputs
Off
b
cnt=0
FSM outputs
Nextstate Nextstate
13
HLSM outputs
cnt=0
HLSM inputs
b
Combinational logic Currstate Cnt
clk
Cnt register
CntNext
x=1 cnt=cnt-1
On (cnt=0)'
x HLSM outputs
HLSM inputs
b Combinational logic Currstate clk State register Nextstate Cnt Cnt register CntNext
Top-Down Design
Top-down design
Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first.
Capture behavior
k_s p_s s_s w_s k_s p_s s_s w_s
Simulate
Capture structure
Simulate
Top-Down Design
Top-down design
Capture behavior, and simulate Capture structure (circuit), simulate again Gets behavior right first.
Inputs: b; Outputs: x; Register: cnt(2) x=0 cnt=2 Off b
b
cnt=0
At RTL level
Capture behavior HLSM Capture structure: Controller and datapath
Controller
Datapath
Off
b
b cnt=0
Cnt_s Cnt_eq0
-1
Cnt_ld Clk
ld
Cnt
b
cnt=0
x=1 cnt=cnt-1
On
(cnt=0)' Datapath
"10"
Cnt_s
Off b
b
Cnt_eq0
Cnt_eq0
="00"
s 1 2x1 0
-1
Cnt_ld Clk
ld
Cnt
On
(Cnt_eq0)'
Controller
Datapath
"10"
Cnt_s
Off b
b
Cnt_eq0
Cnt_eq0
="00"
s 1 2x1 0
-1
Cnt_ld Clk
ld
Cnt
On
(Cnt_eq0)'
Controller
Two processes
Off
b
Cnt_eq0
x=1 Cnt_s=0, Cnt_ld=1
On
(Cnt_eq0)'
Controller
ARCHITECTURE CtrlDpBeh OF LaserTimer IS -- Shared signals SIGNAL Cnt_eq0, Cnt_s, Cnt_ld: std_logic; -- Datapath signals SIGNAL Cnt, CntNext: std_logic_vector(1 DOWNTO 0); -- Controller state signals TYPE Statetype IS (S_Off, S_On); SIGNAL Currstate, Nextstate: Statetype; BEGIN ------ Datapath processes -----DPCombLogic: PROCESS (Cnt_s, Cnt) ... END PROCESS DPCombLogic; DpRegs: PROCESS (Clk) ... END PROCESS DpRegs; ------ Controller processes -----CtrlCombLogic: PROCESS (Currstate, Cnt_eq0, b) ... END PROCESS CtrlCombLogic; CtrlRegs: PROCESS (Clk) ... END PROCESS CtrlRegs; END CtrlDpBeh;
"10"
="00"
s12x1 0
Off Off
b b
cnt=0 Cnt_eq0
Cnt_eq0
-1
Cnt_s=0, Cnt_ld=1
Cnt_ld
ld
Cnt
SAD
256-byte array
go
Wait until go equals '1' Sum := 0; FOR I IN 0 TO 255 LOOP Sum := Sum + |A(I) - B(I)|; END LOOP; SAD_out <= Sum;
S0 go
S1
(i<256)