Chapter 14: Arithmetic Modules

Chapter 14: Arithmetic Modules

Prof. Ming-Bo Lin

Department of Electronic Engineering National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Objectives
After completing this chapter, you will be able to: Describe both addition and subtraction modules Understand the principles of carry-look-ahead (CLA) adder Understand the essential ideas of parallel-prefix adders Describe the basic operations of multiplication Describe the basic operations of division Describe the designs of arithmetic-logic unit (ALU)
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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction
Carry-look-ahead (CLA) adders Parallel-prefix adders

Multiplication Division Arithmetic and logic unit

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Chapter 14: Arithmetic Modules

Bottleneck of Ripple-Carry Adder

Bottleneck of n-bit ripple-carry adder
The generation of carries

Ways of carry generation

carry-look-ahead (CLA) adder parallel-prefix adders:
Kogge-Stone adder Brent-Kung adder

others

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Chapter 14: Arithmetic Modules

A CLA adder
Definition
carry generate (gi): gi = xi yi carry propagate (pi): pi = xi yi

si = pi ci ci +1 = g i + pi ci

c1 = g 0 + p0c0
c2 = g1 + p1c1 = g1 + p1 ( g 0 + p0c0 ) = g1 + p1 g 0 + p1 p0 g 0
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Chapter 14: Arithmetic Modules

A Carry-Lookahead Generator

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Chapter 14: Arithmetic Modules

A CLA Adder

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Chapter 14: Arithmetic Modules

A CLA Adder
// a 4-bit CLA adder using assign statements module cla_adder_4bits(x, y, cin, sum, cout); // inputs and outputs input [3:0] x, y; input cin; output [3:0] sum; output cout; // internal wires wire p0,g0, p1,g1, p2,g2, p3,g3; wire c4, c3, c2, c1; // compute the p for each stage assign p0 = x[0] ^ y[0], p1 = x[1] ^ y[1], p2 = x[2] ^ y[2], p3 = x[3] ^ y[3];
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Chapter 14: Arithmetic Modules

A CLA Adder
// compute the g for each stage assign g0 = x[0] & y[0], g1 = x[1] & y[1], g2 = x[2] & y[2], g3 = x[3] & y[3]; // compute the carry for each stage assign c1 = g0 | (p0 & cin), c2 = g1 | (p1 & g0) | (p1 & p0 & cin), c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cin), c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & cin); // compute Sum assign sum[0] = p0 ^ cin, sum[1] = p1 ^ c1, sum[2] = p2 ^ c2, sum[3] = p3 ^ c3; // assign carry output assign cout = c4; endmodule
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Chapter 14: Arithmetic Modules

A CLA Adder --- Using generate statements

// an n-bit CLA adder using generate loops module cla_adder_generate(x, y, cin, sum, cout); // inputs and outputs parameter N = 4; //define the default size input [N-1:0] x, y; input cin; output [N-1:0] sum; output cout; Virtex 2 XC2V250 FG456 -6 // internal wires wire [N-1:0] p, g; wire [N:0] c; // assign input carry assign c[0] = cin;
n f (MHz) LUTs 4 104.3 8 8 78.9 16 16 53.0 32 32 32.0 64

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Chapter 14: Arithmetic Modules

A CLA Adder --- Using generate statements

genvar i; generate for (i = 0; i <N; i = i + 1) begin: pq_cla assign p[i] = x[i] ^ y[i]; assign g[i] = x[i] & y[i]; end endgenerate // compute generate and propagation generate for (i = 1; i < N+1; i = i + 1) begin: carry_cla assign c[i] = g[i-1] | (p[i-1] & c[i-1]); end endgenerate // compute carry for each stage generate for (i = 0; i < N; i = i + 1) begin: sum_cla assign sum[i] = p[i] ^ c[i]; end endgenerate // compute sum assign cout = c[n]; // assign final carry
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley 14-12

Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction
Carry-look-ahead (CLA) adder Parallel-prefix adders

Multiplication Division Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Parallel-Prefix Adders
The prefix sums s[i,0] = xi ~xi-1~ ~x1 ~x0
where 0 i < n

From bits k to i
g[ i ,k ] = g[ i , j +1] + p[ i , j +1] g[ j ,k ] p[ i ,k ] = pi , j +1] p[ j ,k ] where 0 i < n, k j < i, 0 k < n

g[i ,i ] = xi yi p[i ,i ] = xi yi
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Chapter 14: Arithmetic Modules

Parallel-Prefix Adders
The carry of ith-bit adder ci = gi 1 + pi 1 ci 1 can be written as
g[ i ,0] = g[ i , j +1] + p[ i , j +1] g[ j ,0]

Define group g[i,j] and p[i,j] as a group and denoted as

w[i,j] = (g[i,j], p[i,j])

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Parallel-Prefix Adders
The operator ~ in w[i,k] = w[i,j+1]~w[j,k] is a binary associative operator.
ci = gi 1 + pi 1 ci 1 g[ i ,0] = g[ i , j +1] + p[ i , j +1] g[ j ,0]

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Chapter 14: Arithmetic Modules

Kogge-Stone Adder

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Chapter 14: Arithmetic Modules

Brent-Kung Adder

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Parallel-Prefix Adders
An n-input Kogge-Stone parallel-prefix network
a propagation delay of log2n levels a cost of nlog2n - n + 1 cells

An n-input Brent-Kung parallel-prefix network

a propagation delay of 2log2n - 2 levels and a cost of 2n - 2 - log2n cells

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication
Shift-and-add multiplication Basic array multipliers A signed array multiplier

Division Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Shift-and-Add Multiplication

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Chapter 14: Arithmetic Modules

Shift-and-Add Multiplication
A sequential implementation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication
Shift-and-add multiplication Basic array multipliers A signed array multiplier

Division Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

A Basic Array Multiplier

An iterative logic structure

P = X Y = xi 2 y j 2 (xi y j ) 2
i j i =0 j =0 i =0 j =0

m1

n 1

m1 n 1

i+ j

m+ n 1 k =0

(Pk ) 2k
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Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

Chapter 14: Arithmetic Modules

A Basic Unsigned Array Multiplier

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Chapter 14: Arithmetic Modules

An Unsigned CSA Array Multiplier

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication
Shift-and-add multiplication Basic array multipliers A signed array multiplier

Division Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

A Signed Array Multiplier

Let X and Y be two twos complement number
X = xm1 2
m1

+ xi 2i
i =0

m2

Y = yn1 2
P = XY

n 1

+ yj2j
j =0

n2

m2 n2 m 1 i n 1 j = xm1 2 + xi 2 yn1 2 + y j 2 i =0 j =0

= xi y j 2
i =0 j =0

m2 n2

i+ j

+ xm1 yn1 2

m+ n2

n2 m2 i + n 1 j + m1 x y 2 x y 2 + i n 1 m1 j i = j = 0 0

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

A Signed Array Multiplier

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

A Signed Array Multiplier

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication Division
Nonrestoring division algorithm Implementations

Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

An Unsigned Non-restoring Division Algorithm

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Chapter 14: Arithmetic Modules

An Unsigned Non-restoring Division Algorithm

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Chapter 14: Arithmetic Modules

An Unsigned Nonrestoring Division Example

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication Division
Nonrestoring division algorithm Implementations

Arithmetic and logic unit

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

A Sequential Unsigned Non-restoring Division

A sequential implementation

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

An Unsigned Array Non-restoring Divider

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit
Basic functions Implementations

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Arithmetic-Logic Units
Arithmetic unit
addition subtraction multiplication division

Logical unit
AND OR NOT

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Shift Operations
Logical shift
Logical left shift Logical right shift

Arithmetic shift
Arithmetic left shift Arithmetic right shift

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Syllabus
Objectives Addition and subtraction Multiplication Division Arithmetic and logic unit
Basic functions Implementations

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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Chapter 14: Arithmetic Modules

Arithmetic-Logic Units

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008-2010, John Wiley

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