Embedded Tutorial July 25 Low Power Verification - overcoming the challenges Speaker: Srikanth Jadcherla, Group Director R&D,

Verification Group, Synopsys Inc. Abstract: The advent of LP design brings forth an explosion in the verification space to cover : new power intent

files, states, transitions, sequences etc. need to be verified in a productive and accurate manner. The tutorial will dwell into these changes in the context of verification flow. We will also look at topics for research for academia in this area briefly.

Srikanth Jadcherla came to Synopsys as part of the ArchPro acquisition, where he was founder and CTO. Prior to ArchPro, Jadcherla was an IC designer and architect at companies such as WSI, Intel, Jasmine and Synopsys. He is a veteran of low power designs and pioneer of many energy efficiency techniques and principles. Jadcherla received an Intel Achievement Award for his work on low power and is the author of 12 patents. He is an honorary green evangelist/technical advisor to various companies ranging from solar energy suppliers to real estate developers. Recently, he has been advocating new paradigms in energy efficient design in semiconductor systems worldwide from both the supply and demand side of energy consumption. Jadcherla holds a bachelors degree in electrical engg from IIT -Madras in India, and a masters degree in computational science and engg from the University of California, Santa Barbara.