Example 1

Program the divisor Latch for 300 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8

300*384=115200 115200*16=1843200

0 1

RX_TX / Divisor.low IER: Interrupt Enable Reg. / Divisor.high IIR: Interrupt Identification Reg.

3 4

LCR: Line Control Reg. MCR: Modem Control Reg.

5 6

LSR: Line Status Reg. MSR: Modem Status Reg.

Example 2
Program the divisor Latch for 2400 baud. Assume Xin=1.8432MHz The Base Address: 0x3F8

2400*48=115200 115200*16=1843200

Example 3
Program 8250 for 2400 baud, 8 data bit, even parity and 1 stop bit. Assume Xin=1.8432MHz The Base Address: 0x3F8

MOV MOV OUT MOV MOV OUT MOV INC OUT MOV MOV OUT

AL,80H DX,3FBH DX,AL AX,48 DX,3F8H DX,AL AL,AH DX DX,AL AL,00011011 DX,3FBH DX,AL

; Accessing DLAB ;Line Control Register Address ;baud=2400 115200:48=2400 ;Low byte of Divisor

; DLAB,Break,Even,1 stop, 8 data ;LCR

Synchronous Serial Communication

Introduction to USART Intel 8251

Serial Data Transfer

Asynchronous v.s. Synchronous
Asynchronous transfer does not require clock signal. However, it transfers extra bits
(start bits and stop bits) during data communication Synchronous transfer does not transfer extra bits. However, it requires clock signal

Frame Asynchronousdata Data transfer Start B0 B1 B2 B3 B4 B5 B6 Stop bits bit Parity

Synchronous Data transfer

clk
data B0 B1 B2 B3 B4 B5

(a) Serial data transmitted at the proper rate. (b) The data rate is too fast. (c) The data rate is too slow.

Serial Frame (Synchronous)

Bit

3 4 5

7 0

Time
No start or stop bits, timing synchronized with special ASCII characters (SYN)

Synchronous Protocols

CRC

In SDLC: G(X) = x**16 + x**12 + x**5 + 1

8251 Block Diagram

8251 Registers

Mode Register

Mode Instruction (Asynchronous)

Mode Instruction (Synchronous)

Command Register

Status Register

8251 Timing

8251 USART Interface

8251 D[7:0] RD WR A0 CLK A7 A6 A5 A4 A3 A2 A1 IO/M RD WR C/D CLK RS232

TxD
RxD TxC RxC

Programming 8251
8251 mode register

Mode register

Number of Stop bits 00: 01: 10: 11: invalid 1 bit 1.5 bits 2 bits

Parity enable 0: disable 1: enable

Baud Rate Syn. Mode x1 clock x16 clock x64 clock

Parity 0: odd 1: even

00: 01: 10: Character length11: 00: 5 bits 01: 6 bits 10: 7 bits 11: 8 bits

Programming 8251
8251 command register

EH

IR

RTS

ER SBRK RxE

DTR

TxE

command register

TxE: transmit enable DTR: data terminal ready RxE: receiver enable SBPRK: send break character ER: error reset RTS: request to send IR: internal reset EH: enter hunt mode

Programming 8251
8251 status register

DSR

SYNDET

FE

OE

PE

TxEMPTYRxRDY TxRDY

status register

TxRDY: RxRDY: TxEMPTY: PE: OE: FE: SYNDET: DSR:

transmit ready receiver ready transmitter empty parity error overrun error framing error sync. character detected data set ready

Simple Serial I/O Procedures

Read
start

Write
start

Check RxRDY Is it logic 1? Yes No

Check TxRDY Is it logic 1? Yes No

Read data register*

end * This clears RxRDY

Write data register*

end * This clears TxRDY

8251 Reset Sequence

write three successive zeros to control address to assure writing a reset to the command register. write command 40h to reset (reset chip) After the reset, 8251 expects mode settings write the mode settings to control address There after 8251 needs command settings. write command for command settings.

8251 Coding
MOV MOV OUT OUT OUT MOV OUT MOV OUT MOV OUT DX,309h AL,0 DX,AL DX,AL DX,AL AL,40h DX,AL AL,4Eh DX,AL AL,33h DX,AL Main: MOV IN MOV MOV Wait IN AND JZ MOV MOV OUT JMP DX,300h AL,DX AH,AL DX,309h AL,DX AL,01 Wait AL,AH DX,308h DX,AL Main