Multiplexeur 4 vers 1 : Description par flot de donnes entity mux4_1 is Port ( E0 : in STD_LOGIC; E1 : in STD_LOGIC; E2 : in STD_LOGIC; E3 : in STD_LOGIC; A0 : in STD_LOGIC; A1 : in STD_LOGIC;

S : out STD_LOGIC); end mux4_1; architecture flot_data of mux4_1 is signal S1,S2 : STD_LOGIC; begin S1 <= E0 when A0='0' else E1; S2 <= E2 when A0='0' else E3; S <= S1 when A1='0' else S2; end flot_data; Multiplexeur 8 vers 1 : Description structurelle : entity mux8_1 is Port ( E : in STD_LOGIC_VECTOR (7 downto 0); SEL : in STD_LOGIC_VECTOR (2 downto 0); S : out STD_LOGIC); end mux8_1; architecture struct of mux8_1 is component mux4_1 port( E0 : in STD_LOGIC; E1 : in STD_LOGIC; E2 : in STD_LOGIC; E3 : in STD_LOGIC; A0 : in STD_LOGIC; A1 : in STD_LOGIC; S : out STD_LOGIC); end component ; signal S1,S2 :STD_LOGIC; begin C1: mux4_1 port map(E(0),E(1),E(2),E(3),SEL(0),SEL(1),S1); C2: mux4_1 port map(E(4),E(5),E(6),E(7),SEL(0),SEL(1),S2); S <= S1 when SEL(2)='0' else S2; end struct;

Dmultiplexeur 1 vers 4 : description structurelle : Tout dabord on doit concevoir un dmultiplexeur 2 vers 1 par une description flot de donnes : Dmultiplexeur 1 vers 2 : entity demux1_2 is Port ( E : in STD_LOGIC; SEL : in STD_LOGIC; S0 : out STD_LOGIC; S1 : out STD_LOGIC); end demux1_2; architecture flot_data of demux1_2 is begin S0 <= E and not(SEL); S1 <= E and SEL; end flot_data; Dmultiplexeur 1 vers 4 : entity demux1_4 is Port ( E : in STD_LOGIC; A0 : in STD_LOGIC; A1 : in STD_LOGIC; S0 : out STD_LOGIC; S1 : out STD_LOGIC; S2 : out STD_LOGIC; S3 : out STD_LOGIC); end demux1_4; architecture STRUCT of demux1_4 is component demux1_2 Port ( E : in STD_LOGIC; SEL : in STD_LOGIC; S0 : out STD_LOGIC; S1 : out STD_LOGIC); end component ; signal B1,B2 : STD_LOGIC; begin C1 :demux1_2 port map(E,A1,B1,B2); C2 :demux1_2 port map(B1,A0,S0,S1); C3 :demux1_2 port map(B2,A0,S2,S3); end STRUCT;

Dmultiplexeur 1 vers 4 : description structurelle : entity demux1_8 is Port ( E : in STD_LOGIC; S : out STD_LOGIC_VECTOR (7 downto 0); SEL : in STD_LOGIC_VECTOR (2 downto 0)); end demux1_8; architecture STRUCT of demux1_8 is component demux1_4 Port ( E : in STD_LOGIC; A0 : in STD_LOGIC; A1 : in STD_LOGIC; S0 : out STD_LOGIC; S1 : out STD_LOGIC; S2 : out STD_LOGIC; S3 : out STD_LOGIC); end component; component demux1_2 Port ( E : in STD_LOGIC; SEL : in STD_LOGIC; S0 : out STD_LOGIC; S1 : out STD_LOGIC); end component ; signal B1 , B2 : STD_LOGIC; begin C1 : demux1_2 port map(E,SEL(2),B1,B2); C2 : demux1_4 port map(B1,SEL(0),SEL(1),S(0),S(1),S(2),S(3)); C3 : demux1_4 port map(B2,SEL(0),SEL(1),S(4),S(5),S(6),S(7)); end STRUCT;

Trieur sur deux entres (8 bit): description par flot de donnes entity tri_2 is Port ( A : in STD_LOGIC_VECTOR (7 downto 0); B : in STD_LOGIC_VECTOR (7 downto 0); MAX : out STD_LOGIC_VECTOR (7 downto 0); min : out STD_LOGIC_VECTOR (7 downto 0)); end tri_2; architecture flot_data of tri_2 is begin MAX <= A when (A>B) else B; min <= A when (A<B) else B; end flot_data; Trieur sur quatre entres (8 bit): description structurelle : entity tri_4 is port ( A,B,C,D : in std_logic_vector(7 downto 0) ; MM,Mm,mM,mm :out std_logic_vector(7 downto 0) ); end tri_4; architecture Behavioral of tri_4 is component tri port ( A,B :in std_logic_vector(7 downto 0);

MAX,min :out std_logic_vector(7 downto 0) ); end component ; signal max1,min1,max2,min2,min3,max4 :std_logic_vector(7 downto 0); begin C1: tri PORT MAP(A C2: tri PORT MAP(C ,B ,min1 ,max1 ); ,D ,min2 ,max2 );

C3: tri PORT MAP(max1 ,max2 ,min3 ,mm); C4: tri PORT MAP( min1 , min2 , MM , max4 ); C5: tri PORT MAP( min3 , max4 ,Mm , mM ); end Behavioral;

Registre universelle : entity registre_univ is Port ( RESET : in STD_LOGIC; load : in STD_LOGIC; D : in STD_LOGIC_VECTOR (7 downto 0); ES : in STD_LOGIC; Enable : in STD_LOGIC; Dir : in STD_LOGIC; CLK : in STD_LOGIC; Q : inout STD_LOGIC_VECTOR (7 downto 0); SS : out STD_LOGIC); end registre_univ; architecture Behavioral of registre_univ is begin process(RESET,CLK) begin if(RESET='1') then Q<="00000000"; elsif(CLK'EVENT and CLK='1')then if (LOAD='1') then Q<=D; elsif (Enable='1') then if (Dir='1') then Q <= ES &Q(7 downto 1); else Q<= Q(6 downto 0) & ES; end if; end if; end if; end process ; SS <=Q(0) when Dir='1' else Q(7); end Behavioral;

Compteur Dcompteur programmable 4 bits : entity compt is Port ( Reset : in STD_LOGIC; load : in STD_LOGIC;

D : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; UD : in STD_LOGIC; CLK : in STD_LOGIC; Q : inout STD_LOGIC_VECTOR (3 downto 0); RC0 : out STD_LOGIC); end compt; architecture Behavioral of compt is begin process (Reset ,CLK) begin if Reset='1' then Q<="0000"; elsif (CLK'EVENT and CLK='1') then if load='1' then Q<= D; elsif Enable='1' then if UD ='1' then Q <= Q+1; else Q <= Q-1; end if; end if; end if ; end process; process(Q,UD) begin RC0 <='0'; if UD='1' then if Q="0000" then RC0 <='1' ; if UD ='0' then if (Q ="1111") then RC0 <='1' ; end if ; end if ; end if ; end if ; end process ; end Behavioral;

Compteur modulo 10 : entity compteur_10 is Port ( Reset : in STD_LOGIC; load : in STD_LOGIC; D : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; CLK : in STD_LOGIC; Q : inout STD_LOGIC_VECTOR (3 downto 0); RC0 : inout STD_LOGIC); end compteur_10; architecture Behavioral of compteur_10 is begin process (Reset,CLK) begin if (Reset='1') then Q<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q<= D; elsif Enable='1' then if RC0='1' then Q<="0000"; else Q <= Q+1;

end if; end if; end if; end process; process(Q) begin RC0 <='0'; if Q="1001" then RC0 <='1' ; end if ; end process ; end Behavioral;

Compteur modulo 100 : entity compteur_100 is Port ( D1 : in STD_LOGIC_VECTOR (3 downto 0); D2 : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; load : in STD_LOGIC; RC : inout STD_LOGIC; Reset : in STD_LOGIC; CLK : in STD_LOGIC; Q1 : inout STD_LOGIC_VECTOR (3 downto 0); Q2 : inout STD_LOGIC_VECTOR (3 downto 0)); end compteur_100; architecture behavioral of compteur_100 is signal RC0 : STD_LOGIC; begin -- COMPTEUR UNITE process (Reset,CLK) begin if (Reset='1') then Q1<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q1<= D1; elsif Enable='1' then if RC0='1' then Q1<="0000"; else Q1 <= Q1+1; end if ; end if; end if; end process; process(Q1) begin RC0 <='0'; if Q1="1001" then RC0 <='1' ; end if ; end process ;

--COMPTEUR Dizaines process (Reset,CLK,RC0) begin if (Reset='1') then Q2<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q2<= D2;

elsif Enable='1' then if RC0='1' then Q2 <= Q2+1; if RC ='1' then Q2 <="0000"; end if ; end if; end if; end if; end process; process(Q2,CLK) begin RC <='0'; if Q2="1001" then RC <='1' ; end if ; end process ; end behavioral;

Compteur modulo 60 : entity compteur_60 is Port ( D1 : in STD_LOGIC_VECTOR (3 downto 0); D2 : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; load : in STD_LOGIC; RC : inout STD_LOGIC; Reset : in STD_LOGIC; CLK : in STD_LOGIC; Q1 : inout STD_LOGIC_VECTOR (3 downto 0); Q2 : inout STD_LOGIC_VECTOR (3 downto 0)); end compteur_60; architecture Behavioral of compteur_60 is signal RC0 : STD_LOGIC; begin -- COMPTEUR UNITE process (Reset,CLK) begin if (Reset='1') then Q1<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q1<= D1;

elsif Enable='1' then if RC0='1' then Q1<="0000"; else Q1 <= Q1+1; end if; end if ; end if; end process; process(Q1) begin RC0 <='0'; if Q1="1001" then RC0 <='1' ; end if ; end process ;

--COMPTEUR DIZAINES process (Reset,CLK,RC0) begin if (Reset='1') then Q2<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q2<= D2; elsif Enable='1' then if RC0='1' then Q2 <= Q2+1; if RC ='1' then Q2 <="0000"; end if; end if; end if; end if; end process; process(Q2) begin RC <='0'; if Q2="0101" then RC <='1' ; end if ; end process ; end Behavioral;

Compteur modulo 24 : entity compteur_24 is Port ( D1 : in STD_LOGIC_VECTOR (3 downto 0); D2 : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; load : in STD_LOGIC; RC : inout STD_LOGIC; Reset : in STD_LOGIC; CLK : in STD_LOGIC; Q1 : inout STD_LOGIC_VECTOR (3 downto 0); Q2 : inout STD_LOGIC_VECTOR (3 downto 0)); end compteur_24; architecture Behavioral of compteur_24 is signal RC0 : STD_LOGIC; begin -- COMPTEUR UNITE process (Reset,CLK) begin if (Reset='1') then Q1<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q1<= D1;

elsif Enable='1' then if RC0='1' then Q1<="0000"; else Q1 <= Q1+1; end if; end if ; end if; end process; process(Q1) begin RC0 <='0'; if Q1="1001" then RC0 <='1' ; end if ; end process ;

--COMPTEUR DIZAINES process (Reset,CLK,RC0) begin if (Reset='1') then Q2<="0000"; elsif (CLK'EVENT and CLK='1')then if load='1' then Q2<= D2; elsif Enable='1' then if RC0='1' then Q2 <= Q2+1; if RC ='1' then Q2 <="0000"; end if; end if; end if; end if; end process; process(Q2) begin RC <='0'; if Q2="0101" then RC <='1' ; end if ; end process ; process (Q1,Q2) begin if (Q1 =0011 and Q2=0010) then RC<=1 and RC0=1; End if ; End process ; end Behavioral;

Compteur Horaire : entity compteur_horaire is Port ( DH: in STD_LOGIC_VECTOR (7 downto 0); -- Donne heur DM : in STD_LOGIC_VECTOR (7 downto 0); -- Donne minute DS : in STD_LOGIC_VECTOR (7 downto 0); -- Donne seconde Enable : in STD_LOGIC; load : in STD_LOGIC; Reset : in STD_LOGIC; RC : inout STD_LOGIC; CLK : in STD_LOGIC; QH : inout STD_LOGIC_VECTOR (7 downto 0); QM : inout STD_LOGIC_VECTOR (7 downto 0)); QS : inout STD_LOGIC_VECTOR (7 downto 0)); end compteur_horaire; architecture STRUCT of compteur_horaire is component compteur_60 Port ( D1 : in STD_LOGIC_VECTOR (3 downto 0); D2 : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; load : in STD_LOGIC; RC : inout STD_LOGIC; Reset : in STD_LOGIC; CLK : in STD_LOGIC; Q1 : inout STD_LOGIC_VECTOR (3 downto 0); Q2 : inout STD_LOGIC_VECTOR (3 downto 0)); End component ;

Component compteur_24 Port ( D1 : in STD_LOGIC_VECTOR (3 downto 0); D2 : in STD_LOGIC_VECTOR (3 downto 0); Enable : in STD_LOGIC; load : in STD_LOGIC; RC : inout STD_LOGIC; Reset : in STD_LOGIC; CLK : in STD_LOGIC; Q1 : inout STD_LOGIC_VECTOR (3 downto 0); Q2 : inout STD_LOGIC_VECTOR (3 downto 0)); End component ; signal S1,S2, : STD_LOGIC; begin Cmp_second : compteur_60 port map ( DS(0), DS(1), DS(2), DS(3), DS(4), DS(5), DS(6),DS(7),Enable,load ,S1,Reset,CLK ,QS(0), QS(1), QS(2), QS(3), QS(4), QS(5), QS(6), QS(7)) ; Cmp_munite : compteur_60 port map ( DM(0), DM(1), DM(2), DM(3), DM(4), DM(5), DM(6),DM(7),S1,load ,S2,Reset,CLK ,QM(0), QM(1), QM(2), QM(3), QM(4), QM(5), QM(6), QM(7)) ; Cmp_munite : compteur_60 port map ( DH(0), DH(1), DH(2), DH(3), DH(4), DH(5), DH(6),DH(7),S2,load ,RC0,Reset,CLK ,QH(0), QH(1), QH(2), QH(3), QH(4), QH(5), QH(6), QH(7)) ; End STRUCT ;