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Color Television Chassis

EP1.1U
AA
For manual LGE PDP panel see: 3122 785 15590
For manual FHP PDP panel see: 3122 785 14580
For manual SDI PDP panel see: 3122 785 14990

F_15400_000.eps
200505

Contents Page Contents Page


1. Technical Specifications, Connections, and Chassis SSB: Viper: EEPROM (B5E) 57 68-73
Overview 2 SSB: Miscellaneous (B5F) 58 68-73
2. Safety Instructions, Warnings, and Notes 4 SSB: Video DAC (B6) 59 68-73
3. Directions for Use 6 SSB: HDMI: Supply (B7A) 60 68-73
4. Mechanical Instructions 7 SSB: HDMI: I/O + Control (B7B) 61 68-73
5. Service Modes, Error Codes, and Fault Finding 13 SSB: Analog I/O (B7C) 62 68-73
6. Block Diagrams, Test Point Overviews, and SSB: UART (B7D) 63 68-73
Waveforms SSB: Audio: Amplifier (B8A) 64 68-73
Wiring Diagram 42” & 50” 31 SSB: Audio: Connectors (B8B) 65 68-73
Block Diagram Video 32 SSB: SRP List Part 1 66 68-73
Block Diagram Control & Clock Signals 34 SSB: SRP List Part 2 67 68-73
I2C IC’s Overview 35 Side I/O Panel: (42” & 50”) (D) 74 75
Supply Lines Overview 36 Control Panel (42” & 50”) (E) 76 77
7. Circuit Diagrams and PWB Layouts Diagram PWB LED Panel (42” ME5FL) (J) 78 79
SSB: DC / DC (B1A) 37 68-73 Front IR / LED Panel (42” & 50” ME6) (J) 80 80
SSB: Supply + RS232 (B1B) 38 68-73 8. Alignments 81
SSB: Chanel Decoder (B2A) 39 68-73 9. Circuit Descriptions, Abbreviation List, and IC Data
SSB: Main Tuner (B2B) 40 68-73 Sheets 86
SSB: MPIF Main: Video Source Selection (B3A) 41 68-73 Abbreviation List 88
SSB: MPIF Main: Supply (B3B) 42 68-73 IC Data Sheets 91
SSB: MPIF Main: IF & SAW Filter (B3C) 43 68-73 10. Spare Parts List 101
SSB: MPIF Main: Audio Source Selection (B3D) 44 68-73 11. Revision List 101
SSB: MPIF Main: Audio Amplifier (B3E) 45 68-73
SSB: PNX2015: Audio / Video (B4A) 46 68-73
SSB: PNX2015: DV I/O Interface (B4B) 47 68-73
SSB: PNX2015: Tunnelbus (B4C) 48 68-73
SSB: PNX2015: DDR Interface (B4D) 49 68-73
SSB: PNX2015: Standby & Control (B4E) 50 68-73
SSB: PNX2015: Supply (B4F) 51 68-73
SSB: PNX2015: Display Interface (B4G) 52 68-73
SSB: Viper: Control (B5A) 53 68-73
SSB: Viper: Main Memory (B5B) 54 68-73
SSB: Viper: A/V + Tunnelbus (B5C) 55 68-73
SSB: Viper: Supply (B5D) 56 68-73

©
Copyright 2006 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.
All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.

Published by WS 0662 Customer Service Printed in the Netherlands Subject to modification EN 3122 785 16300
EN 2 1. EP1.1U Technical Specifications, Connections, and Chassis Overview

1. Technical Specifications, Connections, and Chassis Overview


Index of this chapter: 1.1.4 Miscellaneous
1.1 Technical Specifications
1.2 Connection Overview Power supply:
1.3 Chassis Overview - Mains voltage (VAC) : 110 - 240

Notes: - Mains frequency (Hz) : 50/60


• Some models in this chassis range have a different
mechanical construction. The information given here is
Ambient conditions:
therefore model specific. - Temperature range (°C) : +5 to +40
• Data below can deviate slightly from the actual situation,
- Maximum humidity : 90% R.H.
due to the different set executions.
• Specifications are indicative (subject to change).

1.1 Technical Specifications Power consumption (values are indicative)


- Normal operation (W) : ≈ 400 (42”)
1.1.1 Vision : ≈ 480 (50”)
- Standby (W) : <1
Display type : Plasma (SDI)
Screen size : 42” (107 cm), 16:9 Dimensions (WxHxD in inch) : 49.2x27.1x4.4 (42”)
: 50” (127 cm), 16:9 : 56.1x30.9x4.4 (50”)
Resolution (HxV pixels) : 1024(*3)x768p (42”)
: 1366(*3)x768p (50”) Weight, stand included (kg/lbs) : 40/87.6 (42”)
Min. contrast ratio : 10000:1 : 57/125.6 (50”)
Min. light output (cd/m2) : 1200 (42”)
: 1300 (52”)
Viewing angle (HxV degrees) : 160x160
1.2 Connection Overview
Tuning system : PLL
TV Color systems : ATSC Note: The following connector color abbreviations are used
: NTSC (acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy=
Video playback : NTSC Grey, Rd= Red, Wh= White, and Ye= Yellow.
Cable : Unscrambled digital
cable - QAM 1.2.1 Side Connections
Tuner bands : VHF, UHF, S, Hyper
Supported video formats : 640x480i - 1fH
: 640x480p - 2fH
: 1280x720p - 3fH
: 1920x1080i - 2fH
Supported computer formats : 640x480 @ 60Hz
: 800x600 @ 60Hz
: 1024x768 @ 60Hz
: 1366x768 @ 60Hz

1.1.2 Sound

Sound systems : AV Stereo


: BTSC
: Dolby Digital (AC3)
Maximum power (WRMS) : 2 x 15 W

1.1.3 Multimedia

Supported file formats : JPEG


: MP3
: Slideshow (.alb) G_16300_002.eps
USB input : USB1.1 030206

Figure 1-1 Side I/O connections

S-Video (Hosiden): Video Y/C - In


1 - Ground Y Gnd H
2 - Ground C Gnd H
3 - Video Y 1 VPP / 75 ohm j
4 - Video C 0.3 VPPP / 75 ohm j

Cinch: Video CVBS - In, Audio - In


Ye - Video CVBS 1 VPP / 75 ohm jq
Wh - Audio L 0.5 VRMS / 10 kohm jq
Rd - Audio R 0.5 VRMS / 10 kohm jq
Technical Specifications, Connections, and Chassis Overview EP1.1U 1. EN 3

Mini Jack: Audio Headphone - Out Rd - Video Pr 0.7 VPP / 75 ohm jq


Bk - Headphone 32 - 600 ohm / 10 mW ot Wh - Audio L 0.5 VRMS / 10 kohm jq
Rd - Audio R 0.5 VRMS / 10 kohm jq
USB1.1
AV1 Cinch: Video YPbPr - In, Audio - In
Gn - Video Y 1 VPP / 75 ohm jq
1 2 3 4 Bu - Video Pb 0.7 VPP / 75 ohm jq
E_06532_022.eps Rd - Video Pr 0.7 VPP / 75 ohm jq
300904 Wh - Audio L 0.5 VRMS / 10 kohm jq
Rd - Audio R 0.5 VRMS / 10 kohm jq
Figure 1-2 USB (type A)
HDMI 1 & 2: Digital Video, Digital Audio - In
1 - +5V k
2 - Data (-) jk 19 1
18 2
3 - Data (+) jk E_06532_017.eps

4 - Ground Gnd H 250505

Figure 1-4 HDMI (type A) connector


1.2.2 Rear Connections (under side)

1 - D2+ Data channel j


2 - Shield Gnd H
3 - D2- Data channel j
4 - D1+ Data channel j
5 - Shield Gnd H
G_16290_068.eps
300106
6 - D1- Data channel j
7 - D0+ Data channel j
8 - Shield Gnd H
Figure 1-3 Rear connections (under side) 9 - D0- Data channel j
10 - CLK+ Data channel j
AV3 S-Video (Hosiden): Video Y/C - In 11 - Shield Gnd H
1 - Ground Y Gnd H 12 - CLK- Data channel j
2 - Ground C Gnd H 13 - n.c.
3 - Video Y 1 VPP / 75 ohm j 14 - n.c.
4 - Video C 0.3 VPPP / 75 ohm j 15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
AV3 Cinch: Video CVBS - In, Audio - In 17 - Ground Gnd H
Ye - Video CVBS 1 VPP / 75 ohm jq 18 - +5V j
Wh - Audio L 0.5 VRMS / 10 kohm jq 19 - HPD Hot Plug Detect j
Rd - Audio R 0.5 VRMS / 10 kohm jq 20 - Ground Gnd H

AV2 Cinch: Video YPbPr - In, Audio - In Aerial - In


Gn - Video Y 1 VPP / 75 ohm jq - - F-type (US) Coax, 75 ohm D
Bu - Video Pb 0.7 VPP / 75 ohm jq

1.3 Chassis Overview

SIDE I/O
CONTROL D
E BOARD
PANEL

LED PANEL J
SMALL SIGNAL
B BOARD
G_16300_003.eps
030206

Figure 1-5 PWB/CBA locations (42 and 50-inch models)


EN 4 2. EP1.1U Safety Instructions, Warnings, and Notes

2. Safety Instructions, Warnings, and Notes


Index of this chapter: Service Default Mode (see chapter 5) with a color bar
2.1 Safety Instructions signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated
2.2 Warnings otherwise) and picture carrier at 475.25 MHz for PAL, or
2.3 Notes 61.25 MHz for NTSC (channel 3).
• Where necessary, measure the waveforms and voltages
with (D) and without (E) aerial signal. Measure the
2.1 Safety Instructions voltages in the power supply section both in normal
operation (G) and in stand-by (F). These values are
Safety regulations require that during a repair: indicated by means of the appropriate symbols.
• Connect the set to the Mains/AC Power via an isolation • The semiconductors indicated in the circuit diagram and in
transformer (> 800 VA). the parts lists, are interchangeable per position with the
• Replace safety components, indicated by the symbol h, semiconductors in the unit, irrespective of the type
only by components identical to the original ones. Any indication on these semiconductors.
other component substitution (other than original type) may • Manufactured under license from Dolby Laboratories.
increase risk of fire or electrical shock hazard. “Dolby”, “Pro Logic” and the “double-D symbol”, are
trademarks of Dolby Laboratories.
Safety regulations require that after a repair, the set must be
returned in its original condition. Pay in particular attention to 2.3.2 Schematic Notes
the following points:
• Route the wire trees correctly and fix them with the
• All resistor values are in ohms and the value multiplier is
mounted cable clamps.
often used to indicate the decimal point location (e.g. 2K2
• Check the insulation of the Mains/AC Power lead for
indicates 2.2 kohm).
external damage.
• Resistor values with no multiplier may be indicated with
• Check the strain relief of the Mains/AC Power cord for
either an "E" or an "R" (e.g. 220E or 220R indicates 220
proper function.
ohm).
• Check the electrical DC resistance between the Mains/AC
• All capacitor values are given in micro-farads (µ= x10-6),
Power plug and the secondary side (only for sets which
nano-farads (n= x10-9), or pico-farads (p= x10-12).
have a Mains/AC Power isolated power supply):
• Capacitor values may also use the value multiplier as the
1. Unplug the Mains/AC Power cord and connect a wire
decimal point indication (e.g. 2p2 indicates 2.2 pF).
between the two pins of the Mains/AC Power plug.
• An "asterisk" (*) indicates component usage varies. Refer
2. Set the Mains/AC Power switch to the "on" position
to the diversity tables for the correct values.
(keep the Mains/AC Power cord unplugged!).
• The correct component values are listed in the Spare Parts
3. Measure the resistance value between the pins of the
List. Therefore, always check this list when there is any
Mains/AC Power plug and the metal shielding of the
doubt.
tuner or the aerial connection on the set. The reading
should be between 4.5 Mohm and 12 Mohm.
4. Switch "off" the set, and remove the wire between the 2.3.3 Rework on BGA (Ball Grid Array) ICs
two pins of the Mains/AC Power plug.
• Check the cabinet for defects, to avoid touching of any General
inner parts by the customer. Although (LF)BGA assembly yields are very high, there may
still be a requirement for component rework. By rework, we
mean the process of removing the component from the PWB
2.2 Warnings and replacing it with a new component. If an (LF)BGA is
removed from a PWB, the solder balls of the component are
• All ICs and many other semiconductors are susceptible to deformed drastically so the removed (LF)BGA has to be
electrostatic discharges (ESD w). Careless handling discarded.
during repair can reduce life drastically. Make sure that,
during repair, you are connected with the same potential as Device Removal
the mass of the set by a wristband with resistance. Keep As is the case with any component that, it is essential when
components and tools also at this same potential. Available removing an (LF)BGA, the board, tracks, solder lands, or
ESD protection equipment: surrounding components are not damaged. To remove an
– Complete kit ESD3 (small tablemat, wristband, (LF)BGA, the board must be uniformly heated to a temperature
connection box, extension cable and earth cable) 4822 close to the reflow soldering temperature. A uniform
310 10671. temperature reduces the chance of warping the PWB.
– Wristband tester 4822 344 13999. To do this, we recommend that the board is heated until it is
• Be careful during measurements in the high voltage certain that all the joints are molten. Then carefully pull the
section. component off the board with a vacuum nozzle. For the
• Never replace modules or other components while the unit appropriate temperature profiles, see the IC data sheet.
is switched "on".
• When you align the set, use plastic rather than metal tools.
Area Preparation
This will prevent any short circuits and the danger of a
When the component has been removed, the vacant IC area
circuit becoming unstable. must be cleaned before replacing the (LF)BGA.
Removing an IC often leaves varying amounts of solder on the
2.3 Notes mounting lands. This excessive solder can be removed with
either a solder sucker or solder wick. The remaining flux can be
removed with a brush and cleaning agent.
2.3.1 General
After the board is properly cleaned and inspected, apply flux on
the solder lands and on the connection balls of the (LF)BGA.
• Measure the voltages and waveforms with regard to the Note: Do not apply solder paste, as this has shown to result in
chassis (= tuner) ground (H), or hot ground (I), depending problems during re-soldering.
on the tested area of circuitry. The voltages and waveforms
shown in the diagrams are indicative. Measure them in the
Safety Instructions, Warnings, and Notes EP1.1U 2. EN 5

Device Replacement avoid mixed regimes. If not to avoid, clean carefully the
The last step in the repair process is to solder the new solder-joint from old tin and re-solder with new tin.
component on the board. Ideally, the (LF)BGA should be • Use only original spare-parts listed in the Service-Manuals.
aligned under a microscope or magnifying glass. If this is not Not listed standard material (commodities) has to be
possible, try to align the (LF)BGA with any board markers. purchased at external companies.
So as not to damage neighboring components, it may be • Special information for lead-free BGA ICs: these ICs will be
necessary to reduce some temperatures and times. delivered in so-called "dry-packaging" to protect the IC
against moisture. This packaging may only be opened
More Information short before it is used (soldered). Otherwise the body of the
For more information on how to handle BGA devices, visit this IC gets "wet" inside and during the heating time the
URL: www.atyourservice.ce.philips.com (needs subscription, structure of the IC will be destroyed due to high (steam-
not available for all regions). After login, select “Magazine”, )pressure inside the body. If the packaging was opened
then go to “Repair Downloads”. Here you will find Information before usage, the IC has to be heated up for some hours
on how to deal with BGA-ICs. (around 90°C) for drying (think of ESD-protection!).
Do not re-use BGAs at all!
2.3.4 Lead Free Solder • For sets produced before 1.1.2005, containing leaded
soldering tin and components, all needed spare parts will
be available till the end of the service period. For the repair
Philips CE is producing lead-free sets (PBF) from 1.1.2005
of such sets nothing changes.
onwards.

In case of doubt whether the board is lead-free or not (or with


Identification: The bottom line of a type plate gives a 14-digit
mixed technologies), you can use the following method:
serial number. Digits 5 and 6 refer to the production year, digits
• Always use the highest temperature to solder, when using
7 and 8 refer to production week (in example below it is 1991
SAC305 (see also instructions below).
week 18).
• De-solder thoroughly (clean solder joints to avoid mix of
two alloys).

Caution: For BGA-ICs, you must use the correct temperature-


profile, which is coupled to the 12NC. For an overview of these
profiles, visit the website www.atyourservice.ce.philips.com
(needs subscription, but is not available for all regions)
You will find this and more technical information within the
"Magazine", chapter "Repair Downloads".
For additional questions please contact your local repair help
E_06532_024.eps desk.
230205

2.3.5 Practical Service Precautions


Figure 2-1 Serial number example

Regardless of the special lead-free logo (which is not always • It makes sense to avoid exposure to electrical shock.
indicated), one must treat all sets from this date onwards While some sources are expected to have a possible
according to the rules as described below. dangerous impact, others of quite high potential are of
limited current and are sometimes held in less regard.
• Always respect voltages. While some may not be
dangerous in themselves, they can cause unexpected
P reactions that are best avoided. Before reaching into a

b powered TV set, it is best to test the high voltage insulation.


It is easy to do, and is a good service precaution.

Figure 2-2 Lead-free logo

Due to lead-free technology some rules have to be respected


by the workshop during a repair:
• Use only lead-free soldering tin Philips SAC305 with order
code 0622 149 00106. If lead-free solder paste is required,
please contact the manufacturer of your soldering
equipment. In general, use of solder paste within
workshops should be avoided because paste is not easy to
store and to handle.
• Use only adequate solder tools applicable for lead-free
soldering tin. The solder tool must be able
– To reach at least a solder-tip temperature of 400°C.
– To stabilize the adjusted temperature at the solder-tip.
– To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature around 360°C
- 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
tips will rise drastically and flux-fluid will be destroyed. To
avoid wear-out of tips, switch “off” unused equipment or
reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
tin/parts is possible but PHILIPS recommends strongly to
EN 6 3. EP1.1U Directions for Use
3. Directions for Use
You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com
As the software upgrade is a new feature, it is explained below.
Mechanical Instructions EP1.1U 4. EN 7

4. Mechanical Instructions
Index of this chapter: • Several models in this chassis range have a different
4.1 Cable Dressing mechanical construction, the instructions given in this
4.2 Service Positions chapter are therefore very model specific.
4.3 Assy/Panel Removal • Figures below can deviate slightly from the actual situation,
4.4 Set Re-assembly due to the different set executions.
Notes: • Follow the disassemble instructions in described order.

4.1 Cable Dressing

G_16300_004.eps
030206

Figure 4-1 Cable dressing (42-inch model)


EN 8 4. EP1.1U Mechanical Instructions

G_16300_015.eps
030206

Figure 4-2 Cable dressing (50-inch model)

4.2 Service Positions 4.2.2 Aluminium Stands

For easy servicing of this set, there are a few possibilities


created:
• Foam bars (created for Service).
• Aluminium service stands (created for Service).

4.2.1 Foam Bars

E_06532_019.eps
170504

Figure 4-4 Aluminium stands (drawing of MkI)

The new MkII aluminium stands (not on drawing) with order


E_06532_018.eps
code 3122 785 90690, can also be used to do measurements,
170504 alignments, and duration tests. The stands can be
(dis)mounted quick and easy by means of sliding them in/out
Figure 4-3 Foam bars the "mushrooms". The new stands are backwards compatible
with the earlier models.
The foam bars (order code 3122 785 90580 for two pieces) can Important: For (older) FTV sets without these "mushrooms", it
be used for all types and sizes of Flat TVs. By laying the TV is obligatory to use the provided screws, otherwise it is possible
face down on the (ESD protective) foam bars, a stable situation to damage the monitor inside!.
is created to perform measurements and alignments.
By placing a mirror under the TV, you can monitor the screen.
Mechanical Instructions EP1.1U 4. EN 9

4.3 Assy/Panel Removal 4.3.5 Side I/O Panel

4.3.1 Metal Rear Cover You will find the Side I/O Panel on the inside of the right
Speaker Compartment Cover. After removal of this cover, this
panel is accessible.
Caution: Disconnect the Mains/AC Power cord before you
1. Disconnect the cable(s) from the panel.
remove the rear cover!
2. Remove the T10 mounting screws that hold the assy.
3. Take out the panel [1] from its bracket.
1. Place the TV set upside down on a table top, using the
When defective, replace the whole unit.
foam bars (see part "Foam Bars").
Caution: do not put pressure on the display, but let the
monitor lean on the speakers or the Front cover.
2. Remove all T10 screws around the edges of the metal rear
cover: “parker” screws around the outer rim, “tapping”
screws around the connector plate.
3. Remove the four "mushrooms" from the rear cover.
4. Lift the metal rear cover from the set. Make sure that wires
and flat foils are not damaged.

4.3.2 Speaker Compartment Cover

After removing the metal rear cover, you gain access to the
Speaker Compartment covers.
1. Remove all screws [1] (see Figure “Speaker compartment
cover removal”).
2. For removal of the right cover, note that the 1
I/O connection cable has to be removed as well.
3. After removal of all the screws, put a screwdriver between
the side of the cover and the front cabinet and slightly push
it upwards so you can take the cover out.

G_16300_006.eps
1 030206
1

Figure 4-6 Side I/O panel removal

1
4.3.6 LED Panel

1 1. Disconnect the cable [1] from the panel.


1 2. Remove the T10 mounting screws [2] that hold the panel.
3. Take out the panel.
1 When defective, replace the whole unit.

1
1

1 1
1

G_16300_005.eps
030206

Figure 4-5 Speaker compartment cover removal


2
4.3.3 Control Panel
G_16300_007.eps
After removal of the left Speaker Compartment Cover, this 030206
panel is accessible. Release the clamps and take out the panel

4.3.4 Speakers
Figure 4-7 LED panel removal
After removal of the Speaker Compartment Covers, you can
access the speakers.
EN 10 4. EP1.1U Mechanical Instructions

4.3.7 Small Signal Board (SSB)

1. Remove all SSB bottom shielding fixation screws [1] and


[3] at the connector plate (bottom side). See Figure “SSB
bottom shielding”.
2. Remove the mains supply unit [2] after having unplugged
the earthcable from the SSB top shielding plate.
3. Take out the SSB bottom shielding plate.
4. Remove all SSB top shielding fixation screws [1]. See
Figure “SSB top shielding”.
5. Take out the SSB top shielding plate; it hinges at the left
side.
6. Remove the fixation screws of the connector plate itself.
7. Unplug all cables on the SSB.
8. Lift the panel from the set.

1 2 1 1 1 1 1 1 1

G_16300_008.eps
030206

Figure 4-8 SSB bottom shielding

G_16300_009.eps
030206

Figure 4-9 SSB top shielding


Mechanical Instructions EP1.1U 4. EN 11

4.3.8 Plasma Display Panel / Glass Plate – Cable at LED panel.


– Keyboard cable at SSB side.
1. Remove the T20 display panel mounting screws [1]. – Audio Amplifier supply cable at the Main Supply board.
2. Remove the T10 [2] and the T15 [3] screws from the – Loudspeaker cables (incl. ferrites) at the Audio panel.
mounting frame. 4. Lift the metal frame (together with all PWBs) from the
3. Unplug all cable(s): display panel (see figure “Frame lift”).
– LVDS cable at SSB side (fragile connector!). 5. After removal of the frame, lift the PDP from the set.
– SSB supply cables at the Main Supply board.
– Mains cable at the Main Supply board.
– Side I/O cable at SSB side (fragile connector!).

2 2

1 1

2 2
3

G_16300_010.eps
030206

Figure 4-10 Display panel removal (photo from LC4.9 chassis)

F_15400_120.eps
200505

Figure 4-11 Frame lift (photo from LC4.9 chassis)


EN 12 4. EP1.1U Mechanical Instructions

4.3.9 PDP Glass Plate

In order to remove/exchange the PDP glass plate:


1. Remove the PDP as described earlier.
2. Remove the LED panel [2] as described previously in this
chapter.
3. Remove the T10 screws [1] from the mounting frame. See
Figure “Glass plate removal (photo from LC4.9 chassis)”.
4. After removal of the frame, you can lift the glass plate from
the set.

G_16300_011.eps
030206

Figure 4-12 Glass plate removal (photo from LC4.9 chassis)

4.4 Set Re-assembly

To re-assemble the whole set, execute all processes in reverse


order.

Notes:
• While re-assembling, make sure that all cables are placed
and connected in their original position. See figure "Cable
dressing".
• Pay special attention not to damage the EMC foams on the
SSB shields. Ensure that EMC foams are mounted
correctly.
Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 13

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: in the channel map and could be different from the one
5.1 Test Points corresponding to the physical channel 3.
5.2 Service Modes • All picture settings at 50% (brightness, color, contrast).
5.3 Stepwise Start-up • All sound settings at 50%, except volume at 25%.
5.4 Service Tools • All service-unfriendly modes (if present) are disabled, like:
5.5 Error Codes – (Sleep) timer.
5.6 The Blinking LED Procedure – Child/parental lock.
5.7 Protections – Picture mute (blue mute or black mute).
5.8 Fault Finding and Repair Tips – Automatic volume levelling (AVL).
5.9 Software Upgrading – Auto switch "off" (when no video signal was received
for 10 minutes).
– Skip/blank of non-favorite pre-sets.
5.1 Test Points – Smart modes.
– Auto store of personal presets.
As most signals are digital, it will be almost impossible to – Auto user menu time-out.
measure waveforms with a standard oscilloscope. Therefore,
waveforms are not given in this manual. Several key ICs are How to Activate SDM
capable of generating test patterns, which can be controlled via Use one of the following methods:
ComPair. In this way it is possible to determine which part is • Use the standard RC-transmitter and key in the code
defective. “062596”, directly followed by the “MENU” button.
Note: It is possible that, together with the SDM, the main
Perform measurements under the following conditions: menu will appear. To switch it "off", push the “MENU”
• Service Default Mode. button again.
• Video: Color bar signal. • Short for a moment the two solder pads [1] on the SSB,
• Audio: 3 kHz left, 1 kHz right. with the indication “SDM”. They are located outside the
shielding. Activation can be performed in all modes, except
5.2 Service Modes when the set has a problem with the Stand-by Processor.
See figure “SDM and SDI service pads”.
Service Default Mode (SDM) and Service Alignment Mode
(SAM) offer several features for the service technician, while
the Customer Service Mode (CSM) is used for communication
between a Customer Helpdesk and a customer.
2 1
There is also the option of using ComPair, a hardware interface
between a computer (see requirements below) and the TV SPI SDM
chassis. It offers the ability of structured troubleshooting, test
pattern generation, error code reading, software version
readout, and software upgrading.

Minimum requirements for ComPair: a Pentium processor,


Windows 95/98, and a CD-ROM drive (see also paragraph
“ComPair”).

5.2.1 Service Default Mode (SDM)

G_16300_012.eps
Purpose 030206
• To create a pre-defined setting, to get the same
measurement results as given in this manual. Figure 5-1 SDM and SDI service pads
• To override SW protections (only applicable for protections
detected by stand-by processor) and make the TV start up
After activating this mode, “SDM” will appear in the upper right
to the step just before protection (a sort of automatic
corner of the screen (if you have picture).
stepwise start up). See paragraph “Stepwise Start Up”.
• To start the blinking LED procedure (not valid in protection
mode). How to Navigate
When you press the “MENU” button on the RC transmitter, the
set will toggle between the SDM and the normal user menu
Specifications
(with the SDM mode still active in the background).

Table 5-1 SDM default settings


How to Exit SDM
Use one of the following methods:
Default • Switch the set to STAND-BY via the RC-transmitter.
Region Freq. (MHz) system • Via a standard customer RC-transmitter: key in “00”-
Europe, AP-PAL/Multi 475.25 PAL B/G sequence.
NAFTA, AP-NTSC, LATAM 61.25 (ch. 3) NTSC M
5.2.2 Service Alignment Mode (SAM)
• Tuning frequency 61.25 MHz for NTSC: The TV shall tune
to physical channel 3 only if channel 3 is an analog channel Purpose
or if there is no channel 3 installed in the channel map. If • To perform (software) alignments.
there is a digital channel installed in channel 3, then the • To change option settings.
frequency to which the set will tune, would be as specified • To easily identify the used software version.
EN 14 5. EP1.1U Service Modes, Error Codes, and Fault Finding

• To view operation hours. Table 5-2 Display option code overview (all FTV chassis)
• To display (or clear) the error code buffer.
Display HEX Display Type Size Vertical
Option Resolution
How to Activate SAM
000 00 PDP SDI 42” 768p
Via a standard RC transmitter: key in the code “062596”
001 01 PDP SDI 50” 768p
directly followed by the “INFO” button. After activating SAM
002 02 PDP FHP 42” 1024i
with this method a service warning will appear on the screen,
003 03 LCD LPL 30” 768p
you can continue by pressing the red button on the RC.
004 04 LCD LPL 37” 768p
005 05 LCD LPL 42” 768p
Contents of SAM:
006 06 SHARP 32” 768p
• Hardware Info.
007 07 PDP SDI V3 42” 480p
– A. VIPER SW Version. Displays the software version
008 08 PDP FHP 1024i 37” 1024i
of the VIPER software (main software) (example:
009 09 LCOS XION - 720p
EP23U-1.2.3.4_12345 = AAAAB_X.Y.W.Z_NNNNN).
010 0A LCD AUO 30” 768p
• AAAA= the chassis name.
011 0B LCD LPL 32” 768p
• B= the region: A= AP, E= EU, L= Latam, U = US.
012 0C LCD AUO 32” 768p
• X.Y.W.Z= the software version, where X is the
013 0D LCD SHARP 37” 768p
main version number (different numbers are not
014 0E LCD LPL 42” 1080p
compatible with one another) and Y is the sub
015 0F PDP SDI 37” 480p
version number (a higher number is always
016 10 PDP FHP 37” 1080i
compatible with a lower number). The last two
017 11 PDP FHP 42” 1080i
digits are used for development reasons only, so
018 12 PDP FHP 55” 768p
they will always be zero in official releases.
019 13 LCOS VENUS - 720p
• NNNNN= last five digits of 12nc code of the
020 14 LCOS VENUS - 1080p
software.
021 15 LCD LPL 26” 768p
– B. SBY PROC Version. Displays the software version
022 16 LCD LPL 32” 768p
of the stand-by processor.
023 17 LG SD 42” 480p
– C. Production Code. Displays the production code of
024 18 PDP SDI V4 42” 480p
the TV, this is the serial number as printed on the back
025 19 PDP SDI V4 42” 768p
of the TV set. Note that if an NVM is replaced or is
026 1A PDP FHP A2 42” 1024i
initialized after corruption, this production code has to
027 1B PDP SDI HD V4 50” 768p
be re-written to NVM. ComPair will foresee in a
028 1C LCD Sharp 37” 1080p
possibility to do this.
029 1D LCD AUO 32” 768p
• Operation Hours. Displays the accumulated total of
030 1E LCD Sharp 37” 1080p
operation hours (not the stand-by hours). Every time the
031 1F LCD Sharp 37” 1080p
TV is switched "on/off", 0.5 hours is added to this number.
032 20 LCD LPL 20” 768p
• Errors. (Followed by maximal 10 errors). The most recent
033 21 LCD QDI 23” 768p
error is displayed at the upper left (for an error explanation
034 22 ECO PTV 51” 1080i
see paragraph “Error Codes”).
035 23 ECO PTV 55” 1080i
• Defective Module. Here the module that generates the
036 24 ECO PTV 61” 1080i
error is displayed. If there are multiple errors in the buffer,
037 25 PDP FHP A3 42” 1024i
which are not all generated by a single module, there is
038 26 DLP 50” 720p
probably another defect. It will then display the message
039 27 DLP 60” 720p
“UNKNOWN” here.
040 28 LCD Sharp 32” 768p
• Reset Error Buffer. When you press “cursor right” and
041 29 LCD Sharp 32” 768p
then the “OK” button, the error buffer is reset.
042 2A PDP SDI V4 63” 768p
• Alignments. This will activate the “ALIGNMENTS” sub-
043 2B LCD Sharp 37” 768p
menu.
044 2C LCD Sharp 37” 768p
• Dealer Options. Extra features for the dealers.
045 2D LCD LPL 26” 768p
• Options. Extra features for Service.
• Initialise NVM. When an NVM was corrupted (or replaced)
in the former EMG based chassis, the microprocessor • Store. All options and alignments are stored when
replaces the content with default data (to assure that the pressing “cursor right” and then the “OK”-button
set can operate). However, all preferences and alignment • SW Maintenance.
values are gone now, and option numbers are not correct. – SW Events. Not useful for service purposes. In case of
Therefore, this was a very drastic way. In this chassis, the specific software problems, the development
procedure is implemented in another way: The moment the department can ask for this info.
processor recognizes a corrupted NVM, the “initialize – HW Events. Not functional at the moment this manual
NVM” line will be highlighted. Now, you can do two things is released, description will be published in an update
(dependent of the service instructions at that moment): manual if the function becomes available.
– Save the content of the NVM via ComPair for
development analysis, before initializing. This will give • Operation hours PDP. Displays the accumulated total of
the Service department an extra possibility for PDP operation hours.
diagnosis (e.g. when Development asks for this).
– Initialize the NVM (same as in the past, however now it How to Navigate
happens conscious). • In SAM, you can select the menu items with the “CURSOR
UP/DOWN” key on the RC-transmitter. The selected item
Note: When you have a corrupted NVM, or you have replaced will be highlighted. When not all menu items fit on the
the NVM, there is a high possibility that you will not have picture screen, move the “CURSOR UP/DOWN” key to display the
any more because your display option is not correct. So, before next/previous menu items.
you can initialize your NVM via the SAM, you need to have a • With the “CURSOR LEFT/RIGHT” keys, it is possible to:
picture and therefore you need the correct display option. To – (De) activate the selected menu item.
adapt this option, use ComPair. The correct HEX values for the – (De) activate the selected submenu.
options can be found in the table below.
Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 15

How to Exit SAM the Dolby Signaling bit. If a Dolby transmission is received
Use one of the following methods: without a Dolby Signaling bit, this indicator will show “OFF”
• Press the “MENU” button on the RC-transmitter. even though a Dolby transmission is received.
• Switch the set to STAND-BY via the RC-transmitter. • Sound Mode. Indicates the by the customer selected
sound mode (or automatically chosen mode). Possible
Note: As long as SAM is activated, it is not possible to change values are “STEREO” and “VIRTUAL DOLBY
a channel. This could hamper the White Point alignments SURROUND”. Change via “MENU”, “TV”, “SOUND”,
because you cannot choose your channel/frequency any more. “SOUND MODE”. It can also have been selected
Workaround: after you have sent the RC code “062596 INFO” automatically by signaling bits (internal software).
you will see the service-warning screen, and in this stage it is • Tuner Frequency. Not applicable for US sets.
still possible to change the channel (so before pressing the • Digital Processing. Indicates the selected digital mode.
“OK” button). Possible values are “STANDARD” and “PIXEL PLUS”.
Change via “MENU”, “TV”, “PICTURE”, “DIGITAL
5.2.3 Customer Service Mode (CSM) PROCESSING”.
• TV System. Gives information about the video system of
Purpose the selected transmitter.
When a customer is having problems with his TV-set, he can – M: NTSC M signal received
call his dealer or the Customer Helpdesk. The service – ATSC: ATSC signal received
technician can then ask the customer to activate the CSM, in • Center Mode. Not applicable.
order to identify the status of the set. Now, the service • DNR. Gives the selected DNR setting (Dynamic Noise
technician can judge the severity of the complaint. In many Reduction), “OFF”, “MINIMUM”, “MEDIUM”, or
cases, he can advise the customer how to solve the problem, “MAXIMUM”. Change via “MENU”, “TV”, “PICTURE”,
or he can decide if it is necessary to visit the customer. “DNR”
The CSM is a read only mode; therefore, modifications in this • Noise Figure. Gives the noise ratio for the selected
mode are not possible. transmitter. This value can vary from 0 (good signal) to 127
(average signal) and to 255 (bad signal). For some
software versions, the noise figure will only be valid when
How to Activate CSM
“Active Control” is set to “medium” or “maximum” before
Key in the code “123654” via the standard RC transmitter.
activating CSM.
• Source. Indicates which source is used and the video/
Note: Activation of the CSM is only possible if there is no (user)
audio signal quality of the selected source. (Example:
menu on the screen!
Tuner, Video/NICAM) Source: “TUNER”, “AV1”, “AV2”,
“AV3”, “HDMI 1”, “SIDE”. Video signal quality: “VIDEO”, “S-
How to Navigate VIDEO”, “RGB 1FH”, “YPBPR 1FH 480P”, “YPBPR 1FH
By means of the “CURSOR-DOWN/UP” knob on the RC- 576P”, “YPBPR 1FH 1080I”, “YPBPR 2FH 480P”, “YPBPR
transmitter, you can navigate through the menus. 2FH 576P”, “YPBPR 2FH 1080I”, “RGB 2FH 480P”, “RGB
2FH 576P” or “RGB 2FH 1080I”. Audio signal quality:
Contents of CSM “STEREO”, “SPDIF 1”, “SPDIF 2”, or “SPDIF”.
• SW Version (example: EP23U-1.2.3.4_12345). Displays • Audio System. Gives information about the audible audio
the built-in main software version. In case of field problems system. Possible values are “Stereo”, ”Mono”, “Mono
related to software, software can be upgraded. As this selected”, “Analog In: No Dig. Audio”, “Dolby Digital 1+1”,
software is consumer upgradeable, it will also be published “Dolby Digital 1/0”, “Dolby Digital 2/0”, “Dolby Digital 2/1”,
on the Internet. “Dolby Digital 2/2”, “Dolby Digital 3/0”, “Dolby Digital 3/1”,
• SBY Processor Version. Displays the built-in stand-by “Dolby Digital 3/2”, “Dolby Digital Dual I”, “Dolby Digital
processor software version. Upgrading this software will be Dual II”, “MPEG 1+1”, “MPEG 1/0”, “MPEG 2/0”. This is the
possible via a PC and a ComPair interface (see chapter same info as you will see when pressing the “INFO” button
Software upgrade). in normal user mode (item “signal”). In case of ATSC
• Set Type. This information is very helpful for a helpdesk/ receiving there will be no info displayed.
workshop as reference for further diagnosis. In this way, it • Tuned Bit. Indicates if the selected preset is automatically
is not necessary for the customer to look at the rear of the tuned (via “Automatic Installation” in the setup menu) or via
TV-set. Note that if an NVM is replaced or is initialized after the automatic tuning system of the TV. In this case “Tuned
corruption, this set type has to be re-written to NVM. bit” will show “YES”. If the TV was not able to auto-tune to
ComPair will foresee a possibility to do this. the correct frequency, this item will show “NO”. So if “NO”
• Production Code. Displays the production code (the serial is displayed, it could indicate that the customer has
number) of the TV. Note that if an NVM is replaced or is manually tuned to a frequency which was too far from a
initialized after corruption, this production code has to be correct frequency, that the TV was not able to auto-tune
re-written to NVM. ComPair will foresee a possibility to do any more.
this. • Preset Lock. Indicates if the selected preset has a child
• Code 1. Gives the latest five errors of the error buffer. As lock: “LOCKED” or “UNLOCKED”. Change via “MENU”,
soon as the built-in diagnose software has detected an “TV”, “CHANNELS”, “CHANNEL LOCK”.
error the buffer is adapted. The last occurred error is • Lock After. Indicates at what time the channel lock is set:
displayed on the leftmost position. Each error code is “OFF” or e.g. “18:45” (lock time). Change “MENU”, “TV”,
displayed as a 2-digit number. When less than 10 errors “CHANNELS”, “LOCK AFTER”.
occur, the rest of the buffer is empty (00). See also • TV Ratings Lock. Indicates the “TV ratings lock” as set by
paragraph Error Codes for a description. the customer. Change via “MENU”, “TV”, “CHANNELS”,
• Code 2. Gives the first five errors of the error buffer. See “TV RATINGS LOCK”. Possible values are: “ALL”,
also paragraph Error Codes for a description. “NONE”, “TV-Y”, “TV-Y7”, “TV-G”, “TV-PG”, “TV-14” and
• Headphone Volume. Gives the last status of the “TV-MA”.
headphone volume, as set by the customer. The value can • Movie Ratings Lock. Indicates the “Movie ratings lock” as
vary from 0 (volume is minimum) to 100 (volume is set by the customer. Change via “MENU”, “TV”,
maximum). Change via”MENU”, “TV”, “SOUND”, “CHANNELS”, “MOVIE RATINGS LOCK”. Possible values
“HEADPHONE VOLUME”. are: “ALL”, “NR”, “G”, “PG”, “PG-13”, “R”, “NC-17” and “X”.
• Dolby. Indicates whether the received transmitter • V-Chip Tv Status. Indicates the setting of the V-chip as
transmits Dolby sound (“ON”) or not (“OFF”). Attention: The applied by the selected TV channel. Same values can be
presence of Dolby can only be tested by the software on shown as for “TV RATINGS LOCK”.
EN 16 5. EP1.1U Service Modes, Error Codes, and Fault Finding

• V-Chip Movie Status. Indicates the setting of the V-chip the Stand-by Processor will enable the 3V3, but will not go to
as applied by the selected TV channel. Same values can protection now. The TV will stay in this situation until it is reset
be shown as for “MOVIE RATINGS LOCK”. (Mains/AC Power supply interrupted).
• Options 1. Gives the option codes of option group 1 as set
in SAM (Service Alignment Mode). The abbreviations “SP” and “MP” in the figures stand for:
• Options 2. Gives the option codes of option group 2 as set • SP: protection or error detected by the Stand-by
in SAM (Service Alignment Mode). Processor.
• AVL. Indicates the last status of AVL (Automatic Volume • MP: protection or error detected by the VIPER Main
Level): “ON” or “OFF”. Change via “MENU”, “TV”, Processor.
“SOUND”, “AVL”. AVL can not be set in case of digital
audio reception (e.g. Dolby Digital or AC3)
• Delta Volume. Indicates the last status of the delta volume
for the selected preset as set by the customer: from “-12”
to “+12”. Change via “MENU”, “TV”, “SOUND”, “DELTA
VOLUME”.
• HDMI key validity. Indicates the key’s validity.
• IEEE key validity. Indicates the key’s validity (n.a.).
• POD key validity. Indicates the key’s validity (n.a.).
• Digital Signal Quality. Indicates quality of the received
digital signal (0= low).

How to Exit CSM


Press any key on the RC-transmitter (with exception of the
“CHANNEL +/-”, “VOLUME”, “MUTE” and digit (0-9) keys).

5.3 Stepwise Start-up

The stepwise start-up method, as known from FTL/FTP sets is


not valid any more. The situation for this chassis is as follows:
when the TV is in a protection state detected via the Stand-by
Processor (and thus blinking an error) and SDM is activated via
shortcutting the pins on the SSB, the TV starts up until it
reaches the situation just before protection. So, this is a kind of
automatic stepwise start-up. In combination with the start-up
diagrams below, you can see which supplies are present at a
certain moment.
Important to know here is, that if e.g. the 3V3 detection fails
(and thus error 11 is blinking) and the TV is restarted via SDM,

Off

Mains
“off” Mains
“on”

- WakeUp requested WakeUp


- Acquisition needed requested

Stand-by Semi
(Off St-by)
Active
- No data Acquisition required
and no POD present
Stand-by
- St-by requested
- Tact SW pushed - Tact SW pushed

- WakeUp requested
- Acquisition needed

No data Acquisition WakeUp


required and requested
POD present
- POD Card removed GoToProtection
- Tact SW pushed
GoToProtection

POD*
Stand-by
GoToProtection

Protection
On
* Only applicable for sets with CableCARD TM
slot (POD)

F_15400_095.eps
020206

Figure 5-2 Transition diagram


Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 17

Off Stand-by or action holder: MIPS

Protection action holder: St-by


Mains is applied

autonomous action
Standby Supply starts running.
+5V2, 1V2Stb, 3V3Stb and +2V5D become present.
In case of PDP 3V3 Vpr to CPU PDP becomes present.

st-by µP resets If the protection state was left by short circuiting the
SDM pins, detection of a protection condition during
startup will stall the startup. Protection conditions in a
playing set will be ignored. The protection mode will
All I/O lines have a “high” default state:
- Assert the Viper reset. not be entered.
- Sound-Enable and Reset-Audio should remain “high”.
- NVM power line is “high”, no NVM communication possible.

- Switch Sound-Enable and Reset-Audio “high”.


Initialise I/O pins of the st-by µP, start keyboard scanning, RC They are “low” in the standby mode if the
detection, P50 decoding. Wake up reasons are “off”. standby mode lasted longer than 2s.

In case of FHP PDP: Switch PDPGO “low”


CPUGO (inverse of the stby I/O line POD-MODE) and PDPGO *
are then both “low” and the PDP is in the “low power” mode.

Switch “low” the NVM power reset line. Add a 2ms delay
Switching the POD-MODE
low in an FHP PDP set
*
Switching the POD-MODE and the
“on” mode “low” in an
SDI PDP set
makes the PDP supplies go to the
*
before trying to address the NVM to allow correct NVM “on” mode.Within 4 seconds, a
makes the CPUGO go “high”
initialization. valid LVDS must be sent to the
and starts the PDP CPU.
display to prevent protection.
(valid for V3 version)
Switch “on” all supplies by switching LOW the POD-MODE except in an FHP PDP Cold
and the ON-MODE I/O lines. Boot

*
+5V, +8V6, +12VS, +12VSW and Vsound are switched on The availability of the supplies is checked through detect signals (delivered by
dedicated detect-IC's) going to the st-by µP. These signals are available for
+12V, +8V6, +5V, +1V2 and +2V5. A low to high transition of the signals should
occur within a certain time after toggling the standby line. If an observers is
Wait 50ms and then start polling the detect- detected before the time-out elapses, of course, the process should continue in
5V, detect-8V6 and detect-12V every 40ms. order to minimize start up time.

detect-5V
received within
2900 ms after POD-MODE
toggle?
* No FHP PDP Set?
No

Switching the PDPGO “high”


will give a visual artefact and Yes
should only be done if really
necessary.
Switch PDPGO high:
PDP should start: 5V, 8V6 and
Yes 12V are activated

detect-5V
received within
activate +5V supply detection algorithm Yes No +5V error
2900 ms after PDPGO
toggle?

SP
detect-12VSW received within
No +12V error
2900 ms after POD-mode
toggle?

Yes

activate +12VSW supply


SP
detection algorithm

No need to wait for the 8V6 detection at this point.

detect-8V6 received
within 6300 ms after POD-mode toggle?*
Startup shall not wait for this detection
and continue startup.
Yes

No
Enable the +1V2 supply (ENABLE-1V2)

activate +8V6 supply


+8V6 error
detection algorithm

Start polling the detect-1V2 every 40ms

SP return F_15400_096a.eps
To part B To part B 020206

* Only applicable for sets with CableCARD TM


slot (POD)

Figure 5-3 “Off” to “Semi Stand-by” flowchart (part 1)


EN 18 5. EP1.1U Service Modes, Error Codes, and Fault Finding

From part A From part B


action holder: MIPS

action holder: St-by

autonomous action

detect-1V2
received within No +1.2V error
250ms?

Yes
SP
Enable the supply for
+2.5V and +3.3V (ENABLE-3V3)
No separate enable and
detect is present for the +2V5
supply in the Baby Jaguar.
No
Start polling the detect-3V3 every 40ms

detect-3V3
received within No +3.3V error
250 ms?

Yes

Activate supply detection algorithms for


SP
+1V2 and +3V3

SUPPLY-FAULT I/O line


No Supply fault error
is High?

Yes

Enable the supply fault detection


SP
interrupt

Set I²C slave address


of Standby µP to (A0h)

Detect EJTAG debug probe


(pulling pin of the probe interface to
ground by inserting EJTAG probe)

EJTAG probe
Yes
connected ?

No

No Cold boot?

Release viper reset


Yes Feed initializing boot script (3)
disable alive mechanism

Release viper reset Release viper reset


Feed warm boot script(2) Feed cold boot script(1)

Release PNX2015 reset 100ms


after Viper reset is released

Release PNX2015 reset 100ms after


Viper reset is released

Bootscript ready
No
in 1250 ms?

Yes

Set I²C slave address


of Standby µP to (64h)

RPC start (comm. protocol)

Flash to RAM image


No
transfer succeeded
within 30s?
Code = 5
Yes

Viper SW initialization
Switch Viper in reset Code = 53 No
succeeded
within 20s?

To part C To part C To part C To part C


F_15400_096b.eps
260505

Figure 5-4 “Off” to “Semi Stand-by” flowchart (part 2)


Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 19

From part B From part B From part B


action holder: MIPS
Wait 10ms Yes
action holder: St-by
Enable Alive check mechanism
Switch the NVM reset autonomous action
line HIGH.

MIPS reads the wake up reason Wait until Viper starts to


from standby µP. communicate
Disable all supply related protections and
switch off the +2V5, +3V3 DC/DC converter.

Wait 5ms Wait for the +8V6 to be detected if not yet present. (if
it does not come, the standby µP will enter a
protection mode, this is not a dead end here)

switch off the remaining DC/DC


converters

3-th try?
Switch POD-MODE and ON-MODE
* Switch “on” the LVDS output of
the PNX2015 with a correct PWR-OK-PDP *
*
I/O line “high”.
SDI PDP clock frequency within 4s after received within 10s
Yes No
Set? switching the POD and “on” after POD and “on” mode
mode to prevent PDP display toggle ?
Yes supply protection.
Log display
error and enter
Yes protection mode
Log Code as
error code

Init SDI PDP


These LVDS items are
SDI V3 display only !!
SP
SP No Switch LVDS back off if
end state is not the active
state.

Send STBYEN = 1
FHP PDP PFCON = 1
Yes Switch PDPGO “low”
Set? VCCON = 1
to PDP display (I²C)

Init FHP PDP

No

Start 4 seconds preheating timer in case of


a LPL scanning backlight LCD set.

AVIP needs to be started before the MPIF in order to have a good clock distribution.
AVIP default power-up mode is Standby. The Viper instructs AVIP via I²C to enable all the
PLLs and clocks and hence enter to Full Power mode.

Initialize PNX2015 HD subsystem

MPIFs should be initialized


MPIF should deliver 4 observers:
POR= 0; normal operation
MSUP = 1: Main supply is present
ASUP = 1; audio supply is present
ROK = 1; reference frequency is present (coming from AVIP)

Log appropriate
All observers present with correct state? No
Observer error

Yes

Initialize tuners and HDMI

Initialize source selection

Initialize video processing ICs


- Spider (if available)

Initialize Columbus
Initialize 3D Combfilter
Initialize AutoTV

Do not enter semi-standby state in case of an LPL


scanning backlight LCD set before 4 s preheating timer has
elapsed.

Semi-Stand-by
F_15400_096c.eps
* Only applicable for sets with CableCARD TM
slot (POD) 020206

Figure 5-5 “Off” to “Semi Stand-by” flowchart (part 3)


EN 20 5. EP1.1U Service Modes, Error Codes, and Fault Finding

42" / 50" SDI V4


action holder: MIPS
Semi Stand-by
action holder: St-by

autonomous action

RGB video blanking


and audio mute.

Initialize audio and video processing ICs and


functions.

Wait untill QVCP generates a valid LVDS


output clock

Switch “on” LVDS transmitter


(PNX2015) (if not already on).

Switch the SDI Picture Flag “low” to enable picture. 1.5


seconds later, the display will unblank automatically
and show the LVDS content.

Enable anti-aging
(if applicable).

Switch “off” RGB blanking after valid, stable video.

Switch Audio-Reset and sound enable “low” and demute.

Active F_15400_097.eps
260505

Figure 5-6 “Semi Stand-by” to “Active” flowchart


Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 21

42" / 50" SDI V4


action holder: MIPS
Active
action holder: St-by

autonomous action

Mute all sound outputs.

Switch RESET_AUDIO and


SOUND_ENABLE lines “high”

Blank PDP display.

Mute all video outputs.

Wait 600ms to prevent image


retention
(display error)

Switch “off” LVDS signal


(PNX2015).

Switch the SDI Picture Flag “high” to prevent


testpattern display in semi-standby mode

Semi Stand-by F_15400_098.eps


260505

Figure 5-7 “Active” to “Semi Stand-by” flowchart


EN 22 5. EP1.1U Service Modes, Error Codes, and Fault Finding

POD*
action holder: MIPS
Semi Stand-by
action holder: St-by

autonomous action

Transfer Wake up reasons to the


Stand-by µP.

Images are re-transferred to DDR-RAM from


Flash RAM (verification through checksum).

MIPS image completes the application reload,


stops DDR-RAM access, puts itself in a
sleepmode, and signals the standby µP when
the Stand-by mode can be entered.

DDR-RAM is put in self refresh mode and the images


are kept in the hibernating DDR-RAM.

Wait 5ms

Switch Viper in reset state

Wait 10ms

Switch the NVM reset line “high”.

Disable all supply related protections and switch “off”


the +2V5, +3V3 DC/DC converter.

Wait 5ms

Switch “off” the remaining DC/DC converters

Switch “off” all supplies by switching “high” the POD-


MODE and the ON-MODE I/O lines.
*
Important remark:
release RESET AUDIO and For PDP this means
SOUND_ENABLE 2 sec after CPUGO becomes low.
entering stand-by to save power

Stand-by

* Only applicable for sets with CableCARD TM


slot (POD) F_15400_099.eps
020206

Figure 5-8 “Semi Stand-by” to “Stand-by” flowchart


Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 23

action holder: MIPS


MP SP
action holder: St-by

autonomous action Log the appropriate error and


set stand-by flag in NVM

Redefine wake up reasons for protection


state and transfer to stand-by µP.

Switch “off” LCD lamp supply (for LCD sets)

If needed to speed up this transition, Wait 250ms (min. = 200ms)


this block could be omitted. This is
depending on the outcome of the
safety investigations.
Switch “off” LVDS signal

Switch “off” 12V LCD supply within a time frame of


min. 0.5ms to max. 50ms after LVDS switch “off”. (for LCD sets)

Ask stand-by µP to enter protection state

Switch Viper in reset state

Wait 10ms

Switch the NVM reset line “high”.

Disable all supply related protections and switch “off”


the +2V5, +3V3 DC/DC converter.

Wait 5ms

Switch “off” the remaining DC/DC converters

*
Switch “off” all supplies by switching “high” the POD-
MODE and the ON-MODE I/O lines.

Flash LED in order to indicate


protection state.

Protection
F_15400_102.eps
* Only applicable for sets with CableCARD TM
slot (POD) 020206

Figure 5-9 “Protection” flowchart


EN 24 5. EP1.1U Service Modes, Error Codes, and Fault Finding

5.4 Service Tools


TO TO
UART SERVICE I2C SERVICE
5.4.1 ComPair CONNECTOR CONNECTOR

Introduction
ComPair (Computer Aided Repair) is a service tool for Philips
Consumer Electronics products. ComPair is a further
development on the European DST (service remote control),
which allows faster and more accurate diagnostics. ComPair
has three big advantages:
1. ComPair helps you to quickly get an understanding on how PC VCR Power I2C
9V DC
to repair the chassis in a short time by guiding you E_06532_021.eps
systematically through the repair procedures. 180804

2. ComPair allows very detailed diagnostics (on I2C level) and


is therefore capable of accurately indicating problem areas.
Figure 5-10 ComPair interface connection
You do not have to know anything about I2C commands
yourself because ComPair takes care of this.
3. ComPair speeds up the repair time since it can How To Order
automatically communicate with the chassis (when the ComPair order codes:
microprocessor is working) and all repair information is • ComPair Software: ST4191.
directly available. When ComPair is installed together with • ComPair Interface Box: 4822 727 21631.
the Force/SearchMan electronic manual of the defective • AC Adapter: T405-ND.
chassis, schematics and PWBs are only a mouse click • ComPair Quick Start Guide: ST4190.
away. • ComPair interface extension cable: 3139 131 03791.
• ComPair UART interface cable: 3122 785 90630.
Specifications
ComPair consists of a Windows based fault finding program Note: If you encounter any problems, contact your local
and an interface box between PC and the (defective) product. support desk.
The ComPair interface box is connected to the PC via a serial
(or RS-232) cable. 5.4.2 LVDS Tool
For this chassis, the ComPair interface box and the TV
communicate via a bi-directional service cable via the service Introduction
connector(s). This service tool (also called “ComPair Assistant 1“) may help
you to identify, in case the TV does not show any picture,
The ComPair fault finding program is able to determine the whether the Small Signal Board (SSB) or the display of a Flat
problem of the defective television. ComPair can gather TV is defective.
diagnostic information in two ways: Furthermore it is possible to program EPLDs with this tool (Byte
• Automatically (by communicating with the television): blaster). Read the user manual for an explanation of this
ComPair can automatically read out the contents of the feature.
entire error buffer. Diagnosis is done on I2C/UART level.
ComPair can access the I2C/UART bus of the television. Since 2004, the LVDS output connectors in our Flat TV models
ComPair can send and receive I2C/UART commands to are standardized (with some exceptions). With the two
the microcontroller of the television. In this way, it is delivered LVDS interface cables (31p and 20p) you can cover
possible for ComPair to communicate (read and write) to most chassis (in special cases, an extra cable will be offered).
devices on the I2C/UART buses of the TV-set.
• Manually (by asking questions to you): Automatic
When operating, the tool will show a small (scaled) picture on
diagnosis is only possible if the microcontroller of the
a VGA monitor. Due to a limited memory capacity, it is not
television is working correctly and only to a certain extent.
possible to increase the size when processing high-resolution
When this is not the case, ComPair will guide you through
LVDS signals (> 1280x960). Below this resolution, or when a
the fault finding tree by asking you questions (e.g. Does the
DVI monitor is used, the displayed picture will be full size.
screen give a picture? Click on the correct answer: YES /
NO) and showing you examples (e.g. Measure test-point I7
and click on the correct oscillogram you see on the Generally this tool is intended to determine if the SSB is
oscilloscope). You can answer by clicking on a link (e.g. working or not. Thus to determine if LVDS, RGB, and sync
text or a waveform picture) that will bring you to the next signals are okay.
step in the fault finding process.
By a combination of automatic diagnostics and an interactive How to Connect
question / answer procedure, ComPair will enable you to find Connections are explained in the user manual, which is packed
most problems in a fast and effective way. with the tool.

How To Connect Note: To use the LVDS tool, you must have ComPair release
This is described in the chassis fault finding database in 2004-1 (or later) on your PC (engine version >= 2.2.05).
ComPair. For every TV type number and screen size, one must choose
the proper settings via ComPair. The ComPair file will be
Caution: It is compulsory to connect the TV to the PC as updated regularly with new introduced chassis information.
shown in the picture below (with the ComPair interface in
between), as the ComPair interface acts as a level shifter. If How to Order
one connects the TV directly to the PC (via UART), ICs will be • LVDS tool (incl. two LVDS cables: 31p and 20p):
blown! 3122 785 90671.
• LVDS tool Service Manual:
3122 785 00810.
Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 25

5.5 Error Codes – 00 00 00 00 00: No errors detected


– 06 00 00 00 00: Error code 6 is the last and only
5.5.1 Introduction detected error
– 09 06 00 00 00: Error code 6 was first detected and
error code 9 is the last detected error
The error code buffer contains all detected errors since the last
• Via the blinking LED procedure (when you have no
time the buffer was erased. The buffer is written from left to
picture). See next paragraph.
right, new errors are logged at the left side, and all other errors
• Via ComPair.
shift one position to the right.
When an error has occurred, the error is added to the list of
errors, provided the list is not full or the error is a protection 5.5.3 How to Clear the Error Buffer
error.
When an error occurs and the error buffer is full, then the new Use one of the following methods:
error is not added, and the error buffer stays intact (history is • By activation of the “RESET ERROR BUFFER” command
maintained), except when the error is a protection error. in the SAM menu.
To prevent that an occasional error stays in the list forever, the • With a normal RC, key in sequence “MUTE” followed by
error is removed from the list after 50+ operation hours. “062599” and “OK”.
When multiple errors occur (errors occurred within a short time • If the content of the error buffer has not changed for 50+
span), there is a high probability that there is some relation hours, it resets automatically.
between them.
5.5.4 Error Buffer
Basically there are three kinds of errors:
• Errors detected by the Stand-by Processor. These In case of non-intermittent faults, clear the error buffer before
errors will always lead to protection and an automatic start you begin the repair (before clearing the buffer, write down the
of the blinking LED for the concerned error (see paragraph content, as this history can give you significant information).
“The Blinking LED Procedure”). In these cases SDM can This to ensure that old error codes are no longer present.
be used to start up (see chapter “Stepwise Start-up”). If possible, check the entire contents of the error buffer. In
• Errors detected by VIPER that lead to protection. In this some situations, an error code is only the result of another error
case the TV will go to protection and the front LED will blink code and not the actual cause (e.g., a fault in the protection
at 3 Hz. Further diagnosis via service modes is not possible detection circuitry can also lead to a protection).
here (see also paragraph “Error Codes” -> “Error Buffer” - There are several mechanisms of error detection:
> “Extra Info”). • Via error bits in the status registers of ICs.
• Errors detected by VIPER that do not lead to • Via polling on I/O pins going to the stand-by processor.
protection. In this case the error can be read out via • Via sensing of analogue values on the stand-by processor.
ComPair, via blinking LED method, or in case you have • Via a “not acknowledge” of an I2C communication
picture, via SAM.
Take notice that some errors need more than 90 seconds
5.5.2 How to Read the Error Buffer before they start blinking. So in case of problems wait 2
minutes from start-up onwards, and then check if the front LED
Use one of the following methods: is blinking.
• On screen via the SAM (only if you have a picture). E.g.:

Table 5-3 Error code overview

Error Description Error/Prot Detected by Device Defective module Result


1 I2C1 P VIPER n.a. I2C1_blocked Protection + 3 Hz blinking
2 I2C2 P VIPER n.a. I2C2_blocked Protection + 3 Hz blinking
3 I2C3 P Stby µP n.a. I2C3_blocked Protection + 3 Hz blinking
4 I2C4 P VIPER n.a. I2C4_blocked Protection + 3 Hz blinking
5 VIPER does not boot (hardware failure) P Stby µP PNX8550 Protection + Error blinking
6 5V supply P Stby µP n.a. Protection + Error blinking
8 1.2V DC/DC P Stby µP n.a. Protection + Error blinking
11 3.3V DC/DC P Stby µP n.a. Protection + Error blinking
12 12V supply P Stby µP n.a. Protection + Error blinking
14 Supply Class D amplifiers P Stby µP Protection + Error blinking
17 MPIF1 Audio Supply (ASUP) E VIPER PNX3000 IF I/O Error logged
18 MPIF1 ref freq E VIPER PNX3000 IF I/O Error logged
25 Supply fault P Stby µP Protection + Error blinking
27 Phoenix E VIPER PNX2015B HD subsystem Error logged
29 AVIP1 E VIPER PNX2015 AV input processor 1 Error logged
32 MPIF1 E VIPER KN10241C Analog Front End 1 Error logged
34 Tuner1 E VIPER Tuner 1 Error logged
37 Channel decoder E VIPER NXT2003 Error logged
43 Hi Rate Front End E VIPER TDA8751 HDMI Error logged
45 Columbus 1 E VIPER PNX2015 Comb filter Error logged
53 VIPER does not boot (software failure) P Stby µP PNX8550 Protection + Error blinking
63 PDP Display P VIPER Display Protection + 3 Hz blinking
EN 26 5. EP1.1U Service Modes, Error Codes, and Fault Finding

Extra Info NVM gives no acknowledge, the stand-by software


• Error 1 (I2C bus 1 blocked). When this error occurs, the assumes that the bus is blocked, the TV goes to protection
TV will go to protection and the front LED will blink at 3 Hz. and error 3 will be blinking.
Now you can partially restart the TV via the SDM shortcut • Error 53. This error will indicate that the VIPER has started
pins on the SSB. Depending on the software version it is to function (by reading his boot script, if this would have
possible that no further diagnose (error code read-out) is failed, error 5 would blink) but initialization was never
possible. With the knowledge that only errors 1, 2, 4, and completed because of hardware peripheral problems
63 result in a 3 Hz blinking LED, the range of possible (NAND flash, ...) or software initialization problems.
defects is limited. Possible cause could be that there is no valid software
• Error 2 (I2C bus 2 blocked). When this error occurs, the loaded (try to upgrade to the latest main software version).
TV will go to protection and the front LED will blink at 3 Hz.
Now you can partially restart the TV via the SDM shortcut
pins on the SSB. Due to hardware restriction (I2C bus 2 is 5.6 The Blinking LED Procedure
the fast I2C bus) it will be impossible to start up the VIPER
and therefore it is also impossible to read out the error 5.6.1 Introduction
codes via ComPair or via the blinking LED method. With
the knowledge that only errors 1, 2, 4, and 63 result in a 3 The blinking LED procedure can be split up into two situations:
Hz blinking LED, the range of possible defects is limited. • Blinking LED procedure in case of a protection detected by
When you have restarted the TV via the SDM shortcut pins, the stand-by processor. In this case the error is
and then pressed "CH+" on your remote control, the TV will automatically blinked. This will be only one error, namely
go to protection again, and the front LED blink at 3 Hz the one that is causing the protection. Therefore, you do
again. This could be an indication that the problem is not have to do anything special, just read out the blinks. A
related to error 2. long blink indicates the decimal digit, a short blink indicates
• Error 3 (I2C bus 3 blocked). There are only three devices the units.
on I2C bus 3: VIPER, Stand-by Processor, and NVM. The • Blinking LED procedure in the “on” state. Via this
Stand-by Processor is the detection device of this error, so procedure, you can make the contents of the error buffer
this error will only occur if the VIPER or the NVM is blocking visible via the front LED. This is especially useful for fault
the bus. This error will also be logged when the NVM gives finding, when there is no picture.
no acknowledge on the I2C bus (see error 44). Note that if
the 12 V supply is missing (connector 1M46 on the SSB), When the blinking LED procedure is activated in the “on” state,
the DC/DC supply on the SSB will not work. Therefore the the front LED will show (blink) the contents of the error-buffer.
VIPER will not get supplies and could block I2C bus 3. So, Error-codes > 10 are shown as follows:
a missing 12 V can also lead to an error 3. 1. “n” long blinks (where “n” = 1 - 9) indicating decimal digit,
• Error 4 (I2C bus 4 blocked). Same remark as with error 1. 2. A pause of 1.5 s,
• Error 5 (I2C bus 5 blocked). This error will point to a 3. “n” short blinks (where “n”= 1 - 9),
severe hardware problem around the VIPER (supplies not 4. A pause of approx. 3 s.
OK, VIPER completely dead, I2C link between VIPER and 5. When all the error-codes are displayed, the sequence
Stand-by Processor broken, etc...). finishes with a LED blink of 3 s,
• Error 7 (8.6 V error). Except a physical problem with the 6. The sequence starts again.
8.6 V itself, it is also possible that there is something wrong
with the Audio DC Protection: see paragraph "Hardware Example: Error 12 9 6 0 0.
Protections" for this. After activation of the SDM, the front LED will show:
• Error 12 (12 V error). Except a physical problem with the 1. 1 long blink of 750 ms (which is an indication of the decimal
12 V itself, it is also possible that there is something wrong digit) followed by a pause of 1.5 s,
with the Audio DC Protection: see paragraph "Hardware 2. 2 short blinks of 250 ms followed by a pause of 3 s,
Protections" for this. 3. 9 short blinks followed by a pause of 3 s,
• Error 14 (Audio supply). This error is triggered in case of 4. 6 short blinks followed by a pause of 3 s,
too low voltage of the audio supplies and therefore a drop 5. 1 long blink of 3 s to finish the sequence,
of the audio supply voltage of below appr. 9 V per supply 6. The sequence starts again.
rail (or lower than 18 V rail to rail). Also a DC voltage of
higher than 1 V DC on the speakers will lead to protection
5.6.2 How to Activate
and error 14 blinking. For LCD sets this circuit can be found
on schematic SA3, for PDP sets this can be found on
schematic C. It should be noted that for 26-inch models Use one of the following methods:
there is only a supply link between the amplifiers and the • Activate the SDM. The blinking front LED will show the
stand-by µC whereas in all other models this link is entire contents of the error buffer (this works in “normal
implemented by Audio-Prot line pin 7 on 1 M02. operation” mode).
• Error 29 (AVIP1). This error will probably generate extra • Transmit the commands “MUTE” - “062500” - “OK”
errors. You will probably also see errors 32 (MPIF) and with a normal RC. The complete error buffer is shown.
error 31 (AVIP 2). Error 29 and 31 will always be logged Take notice that it takes some seconds before the blinking
together due to the fact that both AVIPs are inside the LED starts.
PNX2015 and are on the same I2C bus. In this case start • Transmit the commands “MUTE” - “06250x” - “OK”
looking for the cause around AVIP (part of PNX2015). with a normal RC (where “x” is a number between 1 and
• Error 31 (AVIP2). See info on error 29. 5). When x= 1 the last detected error is shown, x= 2 the
• Error 34 (Tuner 1). When this error is logged, it is not sure second last error, etc.... Take notice that it takes some
that there is something wrong with the tuner itself. It is also seconds before the blinking LED starts.
possible that there is something wrong with the
communication between channel decoder and tuner. See
schematic B2B.
• Error 37 (Channel decoder). This error will always log
error 34 (tuner) extra. This is due to the fact that the tuner
I2C bus is coming from the channel decoder.
• Error 44 (NVM). This error will never occur because it is
masked by error 3 (I2C bus 3). The detection mechanism
for error 3 checks on an I2C acknowledge of the NVM. If
Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 27

5.7 Protections 5.8 Fault Finding and Repair Tips

5.7.1 Software Protections Read also paragraph "Error Codes" - "Extra Info".

Most of the protections and errors use either the stand-by 5.8.1 Exit “Factory Mode”
microprocessor or the VIPER controller as detection device.
Since in these cases, checking of observers, polling of ADCs, When an "F" is displayed in the screen's right corner, this
filtering of input values are all heavily software based, these means that the set is in "Factory" mode, and it normally
protections are referred to as software protections. happens after a new SSB has been mounted.
There are several types of software related protections, solving To exit this mode, push the "VOLUME minus" button on the
a variety of fault conditions: TV's keyboard control for 5 seconds and restart the set
• Protections related to supplies: check of the 12V, +5V,
+8V6, +1.2V, +2.5V and +3.3V.
5.8.2 MPIF
• Protections related to breakdown of the safety check
mechanism. E.g. since a lot of protection detections are
done by means of the VIPER, failing of the VIPER Important things to make the MPIF work:
• Supply.
communication will have to initiate a protection mode since
• Clock signal from the AVIP.
safety cannot be guaranteed anymore.
• I2C from the VIPER.

Remark on the Supply Errors


5.8.3 AVIP
The detection of a supply dip or supply loss during the normal
playing of the set does not lead to a protection, but to a cold
reboot of the set. Important things to make the AVIP work:
• Supplies.
• Clock signal from the VIPER.
Protections during Start-up
• I2C from the VIPER (error 29 and 31).
During TV start-up, some voltages and IC observers are
actively monitored to be able to optimize the start-up speed,
and to assure good operation of all components. If these 5.8.4 DC/DC Converter
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the Introduction
observers are only used during start-up, they are described in • The best way to find a failure in the DC/DC converters is to
the start-up flow in detail (see paragraph “Stepwise Start-up"). check their starting-up sequence at power "on" via the
Mains/AC Power cord, presuming that the Stand-by
5.7.2 Hardware Protections Processor is operational.
• If the input voltage of the DC/DC converters is around 12 V
There is one hardware protection in this chassis: “Audio DC (measured on the decoupling capacitors 2U17/2U25/
2U45) and the ENABLE signals are "low" (active), then the
Protection”. This protection occurs when there is a DC voltage
output voltages should have their normal values.
on the speakers. In that case the main supply is switched "off",
but the stand-by supply is still working. • First, the Stand-by Processor activates the +1V2 supply
(via ENABLE-1V2).
For the Samsung V4 PDP displays, the 8V6 supply is switched
• Then, after this voltage becomes present and is detected
"off" and the LED on the display’s Main Supply blinks eleven
times, which means there is an overvoltage protection. The OK (about 100 ms), the other two voltages (+2V5 and
+3V3) will be activated (via ENABLE-3V3).
front LED of the TV will blink error 7 (8V6 error).
• The current consumption of controller IC 7U00 is around 20
In case of LCD supplies, the 12V supply will drop. This will be
detected by the stand-by processor, which will start blinking the mA (that means around 200 mV drop voltage across
resistor 3U22).
12 V error (error 12).
• The current capability of DC/DC converters is quite high
(short-circuit current is 7 to 10 A), therefore if there is a
Repair Tip linear integrated stabilizer that, for example delivers 1.8V
• It is possible that you have an audio DC protection because
from +3V3 with its output overloaded, the +3V3 stays
of an interruption in one or both speakers (the DC voltage
usually at its normal value even though the consumption
that is still on the circuit cannot disappear through the from +3V3 increases significantly.
speakers).
• The +2V5 supply voltage is obtained via a linear stabilizer
made with discrete components that can deliver a lot of
current. Therefore, in case +2V5 (or +2V5D) is short-
circuited to GND, the +3V3 will not have the normal value
but much less.
• The supply voltage +12VSW is protected for over-currents
by fuse 1U04.

Fault Finding
• Symptom: +1V2, +2V5, and +3V3 not present (even for a
short while ~10ms).
1. Check 12V availability (fuse 1U01, resistor 3U22,
power MOS-FETs) and enable signal ENABLE-1V2
(active low).
2. Check the voltage on pin 9 (1.5 V).
3. Check for +1V2 output voltage short-circuit to GND that
can generate pulsed over-currents 7-10 A through coil
5U03.
4. Check the over-current detection circuit (2U12 or 3U97
interrupted).
EN 28 5. EP1.1U Service Modes, Error Codes, and Fault Finding

• Symptom: +1V2 present for about 100 ms. Supplies +2V5 Table 5-4 SSB service kits (for EL and EP chassis)
and +3V3 not rising.
1. Check the ENABLE-3V3 signal (active "low"). Model Number New SSB order code
2. Check the voltage on pin 8 (1.5 V). 26PF5321D/37 3139 267 27681
3. Check the under-voltage detection circuit (the voltage 32PF5321D/37 3139 267 27711
on collector of transistor 7U10-1 should be less than 32PF7321D/37 3139 267 27731
37PF7321D/37 3139 267 27691
0.8 V).
42PF5421D/37 3139 267 27671
4. Check for output voltages short-circuits to GND (+3V3,
42PF7321D/37 3139 267 27661
+2V5 and +2V5D) that generate pulsed over-currents 42PF7421D/37 3139 267 27721
of 7-10 A through coil 5U00. 50PF7321D/37 3139 267 27701
5. Check the over-current detection circuit (2U18 or 3U83
interrupted).
5.9.2 Main Software Upgrade
• Symptom: +1V2 OK, but +2V5 and +3V3 present for about
100 ms. Cause: The SUPPLY-FAULT line stays "low" The software image resides in the NAND-Flash, and is
even though the +3V3 and +1V2 is available. The Stand-by formatted in the following way:
Processor is detecting that and switches all supply
voltages "off".
Partition 1
1. Check the drop voltage across resistor 3U22 (this Trimedia2 image
could be too high) Trimedia1 image USB CUSTOMER
2. Check if the +1V2 or +3V3 are higher than their normal MIPS image
values. This can be due to defective DC feedback of
the respective DC/DC converter (3U18 or 3UA7).
Partition 0
USB Download Application USB SERVICE
• Symptom: +1V2, +2V5, and +3V3 look okay, except the
ripple voltage is increased (audible noise can come from
the filtering coils 5U00 or 5U03). uBTM (boot block) EJTAG
Cause: Instability of the frequency and/or duty cycle of one
E_14700_082.eps
or both DC/DC converters. 120505
– Check resistor 3U06, the decoupling capacitors, the
AC feedback circuits (2U20 + 2U21 + 3U14 + 3U15 for Figure 5-11 NAND-Flash format
+1V2 or 2U19 + 2U85 + 3U12 + 3U13 for +3V3), the
compensation capacitors 2U09, 2U10, 2U23 and
Executables are stored as files in a file system. The boot loader
2U73, and IC 7U00.
(uBTM) will load the USB Download Application in partition 0
(USB drivers, bootscript, etc). This application makes it then
Note 1: If fuse 1U01 is broken, this usually means a pair of possible to upgrade the main software via USB.
defective power MOSFETs (7U01 or 7U03). Item 7U00 should
be replaced as well in this case. Installing "Partition 0" software is possible via an external
EJTAG tool, but also in a special way with the USB stick (see
5.9 Software Upgrading description in paragraph “Partition 0“).

5.9.1 Introduction Partition 1 (Customer)


To do a main software upgrade (partition 1) via USB, the set
must be operational, and the "Partition 0" files for the VIPER
The set software and security keys are stored in a NAND-Flash
must be installed in the NAND-Flash!
(item 7P80), which is connected to the VIPER via the PCI bus.
The new software can be uploaded to the TV by using a
It is possible for the user to upgrade the main software via the portable memory device or USB storage compliant devices
USB port. This allows replacement of a software image in a (e.g. USB memory stick). You can download the new software
standalone set, without the need of an E-JTAG debugger. A from the Philips website to your PC.
description on how to upgrade the main software can be found
in chapter 3 "Directions For Use".
Partition 0 (Service)
If the "Partition 0" software is corrupted, the software needs to
Important: When the NAND-Flash must be replaced, a new be re-installed.
SSB must be ordered, due to the presence of the security To upgrade this “USB download application” (partition 0 except
keys!!! See table “SSB service kits” for the order codes. the bootblock), insert an USB stick with the correct software,
Perform the following actions after SSB replacement: but press the “red” button on the remote control (in ”TV” mode)
1. Set the correct option codes (see sticker inside the TV). when it is asked via the on screen text.
2. Update the TV software (see chapter 3 for instructions).
3. Perform the alignments as described in chapter 8.
Caution:
4. Check in CSM menu 5 if the HDMI and POD keys are valid.
• The USB download application will now erase both
partitions (except the boot block), so you need to reload the
main SW after upgrading the USB download application.
As long as this is not done, the USB download application
will start when the set is switched “on”.
• When something goes wrong during the progress of this
method (e.g. voltage dip or corrupted software file), the set
will not start up, and can only be recovered via the EJTAG
tool!
Service Modes, Error Codes, and Fault Finding EP1.1U 5. EN 29

5.9.3 Manual Start of the Main Software Upgrade Application

Normally, the software upgrading procedure will start


automatically, when a memory device with the correct software
is inserted, but in case this does not work, it is possible to force
the TV into the software upgrade application. To do so:
• Disconnect the TV from the Mains/AC Power.
• Press the “OK” button on a Philips DVD RC-6 remote
control (it is also possible to use the TV remote in "DVD"
mode).
• Keep the “OK” button pressed while connecting the TV to
the Mains/AC Power.
• The software upgrade application will start.
• When a memory device with upgrade software is
connected, the upgrade process will start.

5.9.4 Stand-by Software Upgrade

It will be possible to upgrade the Stand-by software via a PC


and the ComPair interface. Check paragraph "ComPair" on
how to connect the interface. To upgrade the Stand-by
software, use the following steps:
1. Disconnect the TV from the Mains/AC Power.
2. Short circuit the SPI pins [2] on the SSB. They are located
outside the shielding (see figure “SDM and SPI service
pads” earlier in this chapter).
3. Keep the SPI pins shorted while connecting the TV to the
Mains/AC Power.
4. Release the short circuit after approx. two seconds.
5. Start up HyperTerminal (can be found in every Windows
application via Programs -> Accessories ->
Communications -> HyperTerminal. Use the following
settings:
– COM1
– Bits per second = 38400
– Data bits = 8
– Parity = none
– Stop bits = 1
– Flow control = Xon / Xoff.
6. Press “Shift U” on your PC keyboard. You should now see
the following info:
– PNX2015 Loader V1.0
– 19-09-2003
– DEVID=0x05
– Erasing
– MCSUM=0x0000
– =
7. If you do not see the above info, restart the above
procedure, and check your HyperTerminal settings and the
connections between PC and TV.
8. Via “Transfer” -> “Send text file ...”, you can send the
proper upgrade file to the TV. This file will be distributed via
the Service Organization.
9. After successful programming, you must see the following
info:
– DCSUM=0xECB3
– :Ok
– MCSUM=0xECB3
– Programming
– PCSUM=0xECB3
– Finished
10. If you do not see this info, restart the complete procedure.
11. Close HyperTerminal.
12. Disconnect and connect Mains/AC Power again.
EN 30 5. EP1.1U Service Modes, Error Codes, and Fault Finding

Personal Notes:

E_06532_012.eps
131004
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 31

6. Block Diagrams, Test Point Overviews, and Waveforms


Wiring Diagram 42” & 50”
WIRING 42” & 50” SDI PLASMA

PLASMA PANEL
8740 8740

8P9

CN8003
9P10
PDP Y-MAIN PDP PDP X-MAIN

CN8005
DRIVING BOARD POWER SUPPLY DRIVING BOARD

5P
CN1M03 CN1M02 CN1M10
RIGHT LEFT

4P
SPEAKER SPEAKER

7P
8M02

CN1M46
CN5003

CN4004
5P10

5P11
9P12

8P11
CN8006 CN8001
10P 2P3
8900

10P

8J02
8G50
CN2026 8M21
31P
8M60
LVDS
Shielding

7P 4P 10P13 4P 31P 3P 6P 9P
11P 8M36
1M02 1740 1J02 1M60 1G50 1M01 1M21 1M52
1M36
31P
1G50
B SSB
1H07
14P
8321

EJTAG
E CONTROL BOARD

D SIDE I/O

1M36
11P
FILTER
TUNER

1M65
3P
5P
1M16
3P Compair
AC/Supply

1M60
4P
8187

1M01
J LED PANEL 6P
3P 1M01

8M01 G_16290_013.eps
020206
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 32

Block Diagram Video


VIDEO
B02B MAIN TUNER B03 MPIF MAIN: B04 PNX 2015: B05 VIPER: B05B VIPER: MAIN MEMORY
7A00
PNX3000HL 7J00 7V00 7V01
PNX2015E PNX8550 K4D551638F
B03C IF B03B
1T04 1A10 B04C TUNNELBUS B05C B05B
TD1336/FGHP 7 107 VIFINP
SOUND GROUP
SUPPLY
TUNNELBUS MAIN MEMORY DDR
IF-OUT
12 IF-ANA IF-ANA 2
8 108 VIFINN
LPF TRAP DELAY 14 PNX2015 SDRAM 1
7T13 +5V TUN-VIPER-RX-DATA

MAIN HYBRID 1T01 LA7795T-E


SUPPLY 28
35
VIPER MM_DATA 8Mx16
14 1 7 2 7 QSS
TUNER IF-1 QSSOUT TUN-VIPER-TX-DATA
99 SIFINP Tunnel Memory 7V02
BPF LPF 44 SCL-DMA North tunnel South tunnel
15 14 8 3 6 DIGITAL controller K4D551638F
IF-2 TUN-VIPER-RX-DATA
SAW 44MHz
in out 100 SIFINN BLOCK 43 SDA-DMA
AGC COTROL TUN-VIPER-RX-DATA
FM-T
4
7T12
TO AM INTERNAL
TUN-VIPER-TX-CLKN
MM_A(0-12) DDR
13 LPF AUDIO SWITCH
IF-AGC 7A11 TUN-VIPER-TX-CLKP SDRAM 2
4
EF
5
3A17
120 CVBSOUTIF DVD 8Mx16
CSS
B02A CHANNNEL DECODER B03A CVBS-OUTA 19
N.C. B05C
SOURCE SELECTION CVBS/Y RIM LPF
B04A AUDIO/VIDEO 2D DE
CVBS-OUTB 22 N.C. AUDIO/VIDEO
CLAM P
7T22
NXT2004 C-PRIM
2-Layer
CVBSOUTIF-MAIN 123 CVBS-IF secondary
DTV CABLE AND 34 FAT-IF-AGC-MAIN Memory
TERRESTRIAL
38 AUX-IF-AGC AV1_CVBS 126 CVBS1 MPIF based scaler
VO-2 video out
RECEIVER N.C.
8 FAT-ADC-INN Dual SD
1 CVBS2 AF30 DV2A-CLK Temporal
QAM 8VSB DV2_CLK single HD C4
ADC 7 FAT-ADC-INP AK28 DV3F-CLK noise redux
Demodulator DV3_CLK MPE2 decoder
12 CVBS_DTV 1H00
STROBE1N 60 STROBE1N-MAIN R4 AVP1_DLK1SN
A 250Mhz A2 27M
From

DATA LINK 1
FEC + DATA STROBE1P 61 STROBE1P-MAIN R3 AVP1_DLK1SP B02A MIPS32
AV2_Y-CVBS 4 CVBS|Y3 LPF D AVIP-1 CPU B06 VIDEO-DAC B04G
B07C LINK CHANNEL
48 FM-TRAP AV2_C 5 C3 1 DATA1N 62 DATA1N-MAIN R2 AVP1_DLK1DN DECODER 7G40
Micro- B07C Yyuv ADV7123KSTZ140
GPIO 7 2FH Scaler and
Controller IRQ-FE-MAIN DATA1P 63 DATA1P-MAIN R1 AVP1_DLK1DP
B05A 8 CVBS|Y4 de-interlacer
MUX
9 C4 DV1_DATA(0-9) DV1F-DATA(0-7) DV-ROUT VIDEO
QPSK STROBE3N 50 STROBE3N-MAIN N4 AVP1_DLK3SN 1SD+1HD
ADC
Demodulator DAC

DATA LINK 3
29 YUV
AV7_Y-CVBS 15 Y_COMB A STROBE3P 51 STROBE3P-MAIN N3 AVP1_DLK3SP COLUMBUS 5 Layer
CLAMP DATA Video Video in
B07C 3D Comb primary
1T11 D LINK DV2_DATA(0-9) TS DV-GOUT
16 C_COMB DATA3N 52 DATA3N-MAIN N2 AVP1_DLK3DN filter and video out
30 25M14 3 router
MPEG_DATA 2nd noice HD/VGA/
Dual
SIF DATA3P 53 DATA3P-MAIN N1 AVP1_DLK3DP reduction 656
TO 25 R|PR|V_1 con
CVBS SEC A/D 1D50
DV1F-DATA(0-7) B05C Yyuv acces
YUV DV3_DATA(0-9) DV3F-DATA (0-7) DV-BOUT 34 1
VIPER 26 G|Y|Y_1 2Fh AV-ROUT
RGB Yyuv A STROBE2N 55 STROBE2N-MAIN P4 AVP1_DLK2SN
LEVEL 32 AV-GOUT 2

DATA LINK 2
27 B|PB|U_1 D
ADAPT

F27
F28
E30
DV-OUT-FFIELD G26
E29
CLAMP
U U,V DATA STROBE2P 56 STROBE2P-MAIN P3 AVP1_DLK2SP AVIP-2
30 R|PR|V_2 INV. 28 AV-BOUT 3
D SIDE I/O
1002 PAL V
A LINK
2 DATA2N 57 DATA2N-MAIN P2 AVP1_DLK2DN
(1302) 31 G|Y|Y_2 D ANALOG
1M36

DV-OUT-HS

DV-OUT-DE
DATA2P 123 DATA2P-MAIN

DV-OUT-VS
P1 AVP1_DLK2DP OUTPUT
(1304) MONO SEC.

DV-CLKIN
1M36 32 B|PB|U_2 (Reserved for PTV)
FRONT_Y-CVBS_IN 2 2 FRONT_Y-CVBS CLP PRIM 46 HV-PRM-MAIN M3
VIDEO TIMING
AVP1_HVINFO1
4 4 FRONT_C CLP SEC CIRCUIT 40 CLK-MPIF M4
CLP yuv MPIF_CLK
1001
MP-OUT-HS
(1301) AV2_FBL L2
AVP2_HSYNCFBL2 Video MPEG VO-1 RGB_HSYNC J29
1 N.C. decoder J28 MP-OUT-VS DV-OUT-VS 12
3 AV6_VSYNC G2 RGB_VSYNC
AVP2_VSYNC2 MP-CLKOUT DV-CLK-IN
S VIDEO 5 FRONT_C_IN N.C. RGB_CLK_IN J30 24
4 J27 MP-OUT-FFIELD
2 B07A HDMI +SUPPLY B07B HDMI: I/O + CONTROL RGB_UD
MP-OUT-DE DV-OUT-DE
B04B DV I/O INTERFACE RGB_DE K26 11

7B50
TDA9975HS RIN (0-9) MP-ROUT(0-9) DV-ROUT (Reserved for PTV)
1I06
( ) 26” - 32” 1 ARX2+ 180
RX2+A GIN (0-9) MP-GOUT(0-9) DV-GOUT
3 ARX2- 179
RX2-A
B07C ANALOG I/O 4 ARX1+ 174 HDMI DV4-DATA(0-7) DV4_DATA_0 T0 9
RX1+A VIP
6 ARX1- 173 Termination
Video
1

RX1-A resistance BIN (0-9) MP-BOUT(0-9) DV-BOUT


2

7 ARX0+ 168 output


RX0+A control
1I04 9 ARX0- 167 formatter
RX0-A DV5-DATA(0-7)
10 162 DV5_DATA_0 T0 9
PR1 ARXC+
RXC+A
PR B07b 12 ARXC- 161 2 DV4-CLK AK8 B04G VIPER/PNX 2015:
RXC-1
18

15 DISPLAY INTERFACE
19

PB1 ARX-DCC-SCL
PB B07b 16 1G50 1P06 (26” LCD)
ARX-DCC-SDA
AV1 Y1 1 1
Y
HDMI 19 ARX-HOTPLUG 7B20 VDISP
B07b
CONNECTOR 2 2
HPD-HIRATE
AV7_Y-CVBS 3 3
VIDEO 1B02 B05A
IN B03a LVDS_TX 4 4
VHREF DV-HREF AH9
1
RX2+B timing DV-HREF TXPNXA- 12 10
Upsample 201 DV-VREF AJ9 DV-VREF B26 5J50
RX2-B generator LVDS_AN
DV-FREF C26 TXPNXA+ 13 12
207 AK9 LVDS_AP
1I03 RX1+B Termination Derepeater DV-FREF
PR RX2-B resistance A25 TXPNXB- 5J52 15 13
PR B07b control LVDS_BN
RX0+B B25 TXPNXB+ 16 15
HDMI LVDS_BP
PB RX0-B HDCP
receiver
PB B07b RXC+B 144 SDA-MM-BUS1 D25 TXPNXC- 5J54 18 18
AV2 I2C slave LVDS_CN
Y RXC-B interface 143 SCL-MM-BUS1 E25 TXPNXC+ 19 20 LVDS
Y B07b LVDS_CP
HSCL B CONNECTOR
AV1_CVBS HSDA B TO SCREEN
VIDEO C23 TXPNXCLK- 5J56 21 21
B03a LVDS_CLKN
IN D23 TXPNXCLK+ 22 23
LVDS_CLKP
Line time
measuremebt
B24 TXPNXD- 5J58 24 26
LVDS_DN
1I02 C24 TXPNXD+ 25 28
(1I00) LVDS_DP
H-SYNC-VGA 131 Activity
HSYNC detection & Sync E24 TXPNXE- 5J60 27
AV2_Y-CVBS
N.C.
V-SYNC-VGA 128 seperator B04E PNX 2015: STANDBY B4E LVDS_EN
F24 TXPNXE+ 28
VSYNC sync selec.
VIDEO B03a N.C. Y 90 & CONTROL STANDBY LVDS_EP
B07A Y1 88 G/Y CTRL-DISP1 7
Slicers Clocks 7LA7
AV3 B07A 7L50 CTRL-DISP2 8
PR 96 generator M25P05 ONLY
1I01 B07A R/PR K4D261638F CTRL-DISP3 9 FHP SETS 9
PR1 94 5 SPI-SDO AK10
1 B04D 10
3 B07A Y 81 ADC CTRL-DISP4
6 SPI-CLK AH10 PMX-MA(0-12)
S VIDEO 5 AV2_C B07A Y1 79 G/Y
512K STANDBY DDR INTERFACE PMX-MA
B03a 1 SPI-CSB AG10 PROCESSOR SCL-I2C4 30 29
2
4 B07A
PB 68
FLASH 31 30
3 SPI-WP AJ27 SDA-I2C4
B07A PB1 66 B/PB
DDR
Memory
See
B07A
Block digram
controller PNX-MDATA PNX-MDATA SDRAM
(0-15)
Control
PNX-MCLK-P
128Mx16
AJ12 A17 45
MCLK_P
1LA0 A16 PNX-MCLK-N 46
MCLK_N
16M AH12
G_16290_006.eps
020206
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 33

Block Diagram Audio


AUDIO
B02B MAIN TUNER B03 MPIF MAIN: B4 PNX2015 B08A AUDIO: AMPLIFIER B08B AUDIO: CONNECTORS
7A00 7J00
PNX3000HL PNX2015E

1T04 B03C IF
TD1336/FGHP 1A10
7 107 VIFINP PNX2015 +12_20V
12 IF-ANA 2 7D2O÷7D21
MAIN 8 108 VIFINN 7D18
HYBRID TUNER SEE ALSO
BLOCKDIAGRAM 7D10-02 1740 Speaker L
VIDEO 5M02 15W/8Ω
LEFT-SPEAKER LEFT-SPEAKER 1

CONTROL
99 SIFINP AH1 ADAC1
DATA LINK 1 ADAC1 7D18

B02A 100 SIFINN DEM DEC


AUDIO 2

DATA LINK
7T22
PROCESSING 7D10-3 Speaker R
NXT2004 I2D
B03D AUDIO SOURCE DATA LINK 2 3 15W/8Ω
DTV FOR MORE MORE DETAILS AG1 ADAC2
SELECTIOM ADAC2
CABLE AND SEE ALSO BLOCK DIAGRAM -12_20V 5M03
7D10-01 7D11 RIGHT-SPEAKER 4
TERRESTRIAL VIDEO AND CONTROL
RECEIVER DATA LINK 3 FEEDBACK-LR
MPIF

CONTROL
DV1F-DATA(0-7) FEEDBACK PROT-AUDIOSUPPLY
AUDIO SWITCH
7D10-01
A DLINK1
LPF INV-MUTE FEEDBACK-RL B04E
D SIDE I/O D DLINK2
72 DSNDR2 AC3 ADCAC12 +12_20V (-12-16V-NF)
73 DSNDL2 1M02

DSND
1002 1M36 AUDIO AD3 ADCAC11
AMPS 7D14÷7D16 5M10
(1302) (1304) 1M36 AM SOUND 74 DSNDR1 AE3 ADCAC10 -12_20V 1
7D23 5M11 From 1M02
L 6 6 75 DSNDL1 AF3 ADCAC19 2
A
AUDIO IN (+12-16V-NF) 3
SUPPLY
AUDIO SWITCH

CONTROL
L+R AUDIO SWITCH 4
R 8 8 RIGHT-SPEAKER OR
(DIGITAL OUT) (ANALOG OUT) 5M12
AVIP 7D23
-12_20V
5M09
5 From CN1M02
AUDIO-IN5-L 6 PDP
128 L5
MUTE SOUND-ENABLE PROT-AUDIOSUPPLY 7 SUPPLY
AUDIO-IN5-R 127 R5 B05A
( ) 26” - 32”
40 CLK-MPIF M4 -12_20V
B07C ANALOG I/O AUDIO-IN1-R 85 R1
B07c 7D26 7D25
AUDIO-IN1-L 86 L1 MUTE
B07c
AUDIO-IN2-R 83 U-VOLT-DETECT
B07c R2 CONTROL CONTROL
AUDIO-IN2-L 84 L2 INV-MUTE
B07c ( ) For 26” LCD
AUDIO-IN4-L 80 L4
B07c
AUDIO-IN4-R 79 R4 B03E MPIF MAIN: AUDIO AMPLIFIER B03A MPIF MAIN: VIDEO SOURS D SIDE I/O
B07c
1I04
SELECTION
7A04-1
LINE / SCART L/R

AUDIO-IN4-R
AV1 B03d
AB1 ADAC7 AUDIO-HDPH-L-AP
AUDIO IN AUDIO-OUT1-R 70 ADAC7
L+R AUDIO-IN4-L B3f 1M36 1010
B03d AUDIO-OUT1-L 69
B3f 1M36 (1304) (1303)
AUDIO-HDPH-L-AP 10 10 SOUND L-HEADPHONE-OUT 2
1I03 7A04-2

AUDIO-IN1-R AA1 ADAC8 AUDIO-HDPH-R-AP AUDIO-HDPH-R-AP 11 11 SOUND R-HEADPHONE-OUT 3


B03d ADAC8
AV2 N.C. 7 7 DETECT 5 Headphone
AUDIO IN Out 3.5mm
L+R AUDIO-IN1-L
B03d
B05 VIPER:
A-PLOP CONTROL
7V00
1I00 PNX8552EH ( ) 26” - 32”
AUDIO-IN2-R
AV3 B03d B5C
I2S-WS-MAIN V3
AUDIO IN I2S_IN1_WS T29 I2S
AUDIO-IN2-L I2S-BCLK-MAIN V2 OUT
L+R
B03d I2S_IN1_SCK T30

1I02
(1I00)
VIPER T28 I2S-MCH-LR U2
AV3 I2S_OUT2_SD0
SPDIF-OUT1 AB29 T27 I2S-MCH-CSW U3
DIGITAL SPDIF-OUT1 I2S_OUT2_SD1
AUDIO R30 I2S-MCH-SLR U4 I2S
I2S_OUT2_SD2 IN
OUT U27 I2S-SUB-D V5
I2S_OUT1_SD0
I2S-MAIN-D V4
I2S_OUT2_SD3 R29

B05B VIPER: MAIN MEMORY


7V02
7V01
B05B MAIN MEMORY
K4D551638F MM_DATA
2X DDR DDR AA27 SPDIF-HDMI
SDRAM INTERFACE
8Mx16 MM_A(0-12)

B07A HDMI +SUPPLY B07B HDMI: I/O + CONTROL

7B50
TDA9970HS

1I06
HDMI PANELLINK
RECEIVER
RX2+ 183 SPDIF-HDMI
1

RX2-
2

RX1+
RX1- Termination
PARX2+ Resistance
Control Audio DV4-DATA
RX0+
RX0- Formatter DV
AUDIO
INPUT
MULTIPLEXED
18

RXC+ Audio PLL Audio FIFO


19

WITH VIDEO RXC- DV5-DATA


SEE ALSO
BLOCKDIAGRAM HDMI Packet
HDMI HDCP
VIDEO receiver extraction
CONNECTOR

G_16290_007.eps
020206
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 34

Block Diagram Control & Clock Signals


CONTROL + CLOCK SIGNALS
B02A CHANNAL DECODER B05 VIPER: B04A PNX2015: B06 VIDEO DAC
7V00 7G40
PNX8550EH/M1/S1 ADV7123KST140
B05C A/V + TUNNELBUS
E30 DV-CLKIN DV-CLKIN 24 VIDEO
7J00 DAC
PNX2015E
VIPER B04B DV I/O INTERFACE
AH19 DV2A-CLK AF30 J30 MP-CLKOUT

AG25 DV3F-CLK AK28


PNX2015
B03B MPIF MAIN: SUPPLY
B04C TUNNELBUS
7T22 K3 TUN-VIPER-RX-CLKP M29
NXT2004
T2 TUN-VIPER-TX-CLKN U30 7A00
PNX3000HL/N3
T1 TUN-VIPER-TX-CLKP U28
DV1F-DATA
DTV M4 CLK-MPIF 40
MPIF
30 CABLE AND E/W &
TERRESTRIAL 51 DV1F-CLK AH16
CONTROL
AG22
25M14

RECEIVER
1T11

B05E VIPER: EEPROM


29 B05A CONTROL AB28 CHDEC-CLK
7P80
84 IRQ-FE-MAIN IRQ-MAIN A26 TC58DVM92F1

59 RESET-FE-MAIN F1
NAND
EEPROM
AK12 NAND-CLE 16 (32Mx16)
D SIDE I/O AJ12 NAND-ALE 17
AK5 NAND-REn 8
AJ7 NAND-WEn 18
5000
1005 (5300) 1M60 AA2 NAND-SEL 9
(1308) (1309) 1M60 W2 19
1050
1 (5301-5302) 1 1 USB-BUS-PW AJ29
B04D PNX 2015: DDR INTERFACE
1

2 2 2 USB1-DM AJ28 D28 PLL-OUT


3 2

3 3 AH27 STBY-WP-NAND-FLASH
3 USB1-DP B04E

3H06
4 4 4
4

7L50
AD2 PCI-CLK-VPR B07B HDMI: I/O + CONTROL
K4D261638F
USB 1.1 B04D DDR INTERFACE PNX-MCLK-N
A16 46
CONNECTOR
C4 DDR
AD27 HPD-HIRATE
B07A SDRAM
SOUND-ENABLE A17 PNX-MCLK-P 45
C27
B08A 7B50 128Mx16
1H00

27M

TDA9975HS/8/C1

B04B DV I/O INTERFACE


A2 HDMI-COAST
AB27 124
D29 M135-CLK 135
HDMI
CONTROL
B5 POWERDOWN-HDMI 115
2 DV4-CLK AK8

C30 M27-PNX Y28


B04E STANDBY + CONTROL B04E PNX 2015: STANDBY & CONTROL
AD3 RESET-MIPS AG19
AD4 RESET-SYSTEM 7LA7
AJ21
M25P05-AVMN6P
B28 DEBUG-BREAK AG21
AH10 SPI-CLK 6 512K
FLASH
B05B VIPER: MAIN MEMORY AJ27 SPI-WP 3
7V01
B05B MAIN MEMORY
A18 MM_CLK_N 46 7V02
MM_CLK_P AH20 SDM 9P24
B18 45 DDR
SDRAM 9P14
16Mx16
SDM
AJ12
( ) For 26” - 32”

E TOP CONTROL B16A CONNECTIONS A

1LA0

16M
AH12
DETECT-1V2 (P2.0) AF16
DETECT-3V3 (P2.2) AH17
1M01
DETECT-5V (P2.3) AG17
(1684) 1M01
B04E DETECT-8V6 (P2.4) AK18
1706(1313) KEYBOARD 2 2
ON / OFF DETECT-12V (P2.5) AJ18 AG22 STBY-WP-NAND-FLASH
B05E
1703(1309) POWER-OK-DISPLAY AH14
CHANNEL +
1704(1310)
CHANNEL - AH15 ENABLE-1V2 (P0.2)
1701(1311) SUPPLY-FAULT AG13 B01A
VOLUME + B01A AK16 ENABLE-3V3 (P0.4)
1702(1312) DEBUG-BREAK AG21
VOLUME - B01A
1705(1314) P50-HDMI AG13
B07A
MENU PROT-AUDIOSUPPLY (P2.7) AG18
B08A

AJ21 RESET-SYSTEM B05A


( ) For 26” - 32”
AH21 RESET-AUDIO
B04A
J LED SWITCH PANEL KEYBOARD KEYBOARD AK23 AH22 RESET-MAIN-NVM
B05E
1870 1M21
6801-1 PC-TV-LED 6
6 LED1 LED1 AK21
AJ16 BACKLIGHT-CONTROL
B04G
CONTROL

LED1
RED AJ16 LAMP-ON (P0.5)
B16A
6801-2 LED-SEL AG16 UART-SWITCH (P0.7)
4 4 LED2 LED2 AG20 B10D
LED2
GREEN
7802 AJ16 RESET-PNX2015
3803 3 3
IR RC RC AK13
+3V3STBY
IR
SENSOR AA27

7808
LIGHT-SENSOR-SDM 1 1 LIGHT-SENSOR LIGHT-SENSOR AH23
LIGHT
SENSOR
Not for 26” Sets
G_16290_011.eps
270106
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 35

I2C IC’s Overview


I²C
B05A VIPER: CONTROL B07A HDMI + SUPPLY B07B HDMI: I/O + CONTROL B01B SUPPLY + RS232
+3V3

3H23
3H22
A25 3Q11 SDA-MM SDA-MM
I2C1-SDA
C25 3Q10 SCL-MM SCL-MM 1H07
I2C1-SCL JTAG-TRST 1

3B61

3B60
PROT EJTAG-DETECT 2
7V00-5 F26 TXD-VIPER 01 142 143
SM PNX8552EH 3
E27 RXD-VIPER EJTAG-TDI

1
1I06

2
VIPER 7B50-1 EJTAG
16 3Q11 EJTAG-TDO 5 CONNECTOR
ARX-DDC-SDA PARX-DDC-SDA 145 TDA9970HS
(FACTORY USE
3Q10 ONLY)
B27 EJTAG-TDI 15 ARX-DDC-SCL PARX-DDC-SCL 146 HDMI EJTAG-TMS 7
CONTROL

18
D25 EJTAG-TDO

19
PROT PROT

3B08

3B07
EJTAG-TCK 9
05 53 A29 EJTAG-TMS
ERR
A28 EJTAG-TCK 5 6 43 9U07 RESET-SYSTEM 11
2x HDMI
CONNECTOR 7B02 JTAG-TRST 107
C2 JTAG-TRST RES
M24C02 B5A
AD4 RESET-SYSTEM
EEPROM
B01B

B03B MPIF MAIN: SUPPLY B04E PNX 2015: STANDBY & CONTROL B02A CHANNEL DECODER B02B MAIN TUNER
+3V3
3H05
3H04

AF29 3Q13 SDA-DMA SDA-DMA


I2C2-SDA
+5VTUN
AD26 3Q12 SCL-DMA SCL-DMA
I2C2-SCL

3T28
3T25
3LH4

3LH3
3LG9

3LH1

3LH0
3A15

3A14

3LF8
PROT
02 I2C-SDA-TUNER
43 44 AG9 AF9 G5 G4 B27 C27
AF11 JTAG-TRST
I2C-SCL-TUNER
7A00-3 7J00-6
B05B VIPER: MAIN MEMORY AF21 EJTAG-DETECT +3V3

3T22

3T23
PNX3000HL PNX2015E
AJ21 RESET-SYSTEM 7T23
MPIF CONTROL PCA9515ADP 90 91 9 8

3T54
3T53
7V01
COLUMBUS AVIP HD 7L50
K4D551638F 3T52
K4D261638F 2 6 43 7T22 1T04
ERR ERR ERR ERR ERR ERR NXT2004 TD1336/FGHP
DDR 32 18 45 29 31 27 DDR
SDRAM 1 SDRAM 3T51
3 7 42 DTV MAIN
16Mx16
RECEIVER DIG TUNER
7V02
K4D551638F RES
ERR ERR
41 34
DDR 9T11 9T10
SDRAM 2
9T12 9T13

VIPER: EEPROM B05E VIPER: EEPROM B07D UART


B05E
+3V3-STANDBY 7P15
74HC4066PW
3LE3
3LE4

TXD-VIPER 10 8
AE27 3Q15 SDA-UP-VIP B5A 1M16
I2C3-SDA 3I10
TXD-UP 9 11 TXD 1
AG29 3Q14 SCL-UP-VIP
I2C3-SCL B4E
3I11
3LE2
3LF0

RXD-UP 2 1 RXD 3
PROT B4E
03 5 6 AG26 AH26 2
3LJ1 RXD-VIPER 3 4
TXD-UP AJ19
7P80 B5A
TC58DVM92F1TGI0 RESET-MAIN-NVM 7P14 7J00-5 7P16
3LJ0 UART-SWITCHn 5
M24C64 RXD-UP AK19 PNX2015E COMPAIR
3LM7 SERVICE
AG16 UART-SWITCH 12 CONNECTOR
7P18 EEPROM
EEPROM B05E PNX2015 (UART)
32Mx16 8 MAIN 7LA7 STANDBY +3V3-STANDBY

3LC6
3LC7
NVM M25P05-AVMN6P 7P17 6
3LH8 SCL-UP-SW
ERR DDR ERR AF14 13
44 26
SDRAM 3LH9
16Mx16 AG14 SCL-UP-SW

+3V3 B04G VIPER/PNX 2015: DISPLAY INTERFACE


3Q03
3Q04

1G50
A3 3H99 SDA-I2C4 SDA-I2C4 3J31 31
I2C4-SDA
TO
B4 3H98 SCL-I2C4 SCL-I2C4 3J30 30 DISPLAY
I2C4-SCL

PROT ERR
04 64
G_16290_008.eps
(OPTIONAL ONLY PDP SETS) 300106
Block Diagrams, Test Point Overviews, and Waveforms EP1.1U AA 6. EN 36

Supply Lines Overview


SUPPLY LINES OVERVIEW
A B01B SUPPLY + RS232 B03A MPIF MAIN: VIDEO SOURCE SELECTOIN B04F PNX2015: SUPPLY B06 VIDEO-DAC (OPTIONAL)

+5V +5V +3V3 +3V3


B01b +1V2 +1V2 B01a
B01a
5LN1 PLL-1V2 5G10 +3V3DAC

+3V3 +3V3
CN1M46 1J02 B01a +5V +5V
7 4
B03B MPIF MAIN: SUPPLY
5LN3 LVDS-3V3
B01b
5V2 7G42
5LN0 PLL-3V3 IN OUT
1 7 COM

+5V +5V
2 8 +1V2-STANDBY +1V2-STANDBY
B01b
5U37 B05f
9 9
12V 5A12 7A10 VREF-AUD-POS B04a +3V3-STANDBY +3V3-STANDBY B07A HDMI + SUPPLY
11 10 5U38 +12VS B05f
B01a 7A00 VREF-AUD 5LN2 UP-3V3 +3V3 +3V3
2 B03e B01a
5U35 MPIF
CN1M03 +2V5 +2V5 5B17 +3V3-APLL B07b
9 5 5U36 +5V2-STBY B01a
B03e,B04a,
B05e,f +2V5-DDRPNX +2V5-DDRPNX 5B11 3V3-PLL
4 6 7U25 +5V B07b
B04d
B03a,b,c,e,
7 11 STANDBY 5B12 3V3-DIG B07b
B04e,g,B05a,
B06,B07a
B03C MPIF MAIN: IF + SAW FILTER
1 12 BACKLIGHT-CNTRL-OUT 7U24 B04G PNX2015: DISPLAY INTERFACE 7B25
+1V8
+5V +5V IN OUT
B07b
3 13 LAMP-ON-OUT POD-MODE
B01b +3V3 +3V3 COM
B01a
5A16 +5VaM 5B18 +1V8-PLL
B07b
+3V3-STANDBY +3V3-STANDBY
+5VTUN +5VTUN B05f +5V +5V2-STBY
B01b
+12VSW B02b +5V +5V
PDP 5A17 +5VbM
B01b 7B45
IN OUT
+3V3-AV

POWER SUPPLY B01a


+12VSW +12VSW COM
5B10 +3V3-AVI
B07b
7J04
7J08 5J11 VDISP 1I06
HDMI
B01a

18 AIN-5V
CONNECTOR
B03D MPIF MAIN: AUDIO SOURCE SELECTION
7J07
+5VTUN +5VTUN +3V3 CONTROL
B02b B07B HDMI: I/O + CONTROL
+8V-AUD +8V-AUD
B03e
B07a +1V8 +1V8
B01A DC / DC

B01b
+12VS +12VS B05A VIPER: CONTROL B07a +1V8-PLL +1V8-PLL

1U01 +12VSW B04g,B07c B03E MPIF MAIN: AUDIO AMPLIFIER


+3V3 +3V3
B01a +3V3 +3V3
CN8001 B01b,B02b, B01a
+5V +5V
1 B03e,B04e, B07a +3V3-DIG +3V3-DIG
AC_L 5U02 7U01 5U00 +3V3 B01b +5V +5V
B01b
AC IN 2 +5V2-STBY +5V2-STBY
B07a +3V3-AVI +3V3-AVI
7U00 B02a,B04a,e,f,g, B01b
~ 3
AC_N 1 B05a,c,d,e,B06 +12VSW +12VSW
B07a,b B01a B07a +3V3-PLL +3V3-PLL
Control 7U03 5U03 +1V2
+8V-AUD
B02a, 7A17 B03d B05B VIPER: MAIN MEMORY
B07a +3V3-APLL +3V3-APLL
B04a,d,e,f, 7A05
16 +2V5-VPR +2V5-VPR
7U28 +2V5 B04c,f,B05d
B05d
B02a,B04e VREF-AUD VREF-AUD 3H52 VREFD-VPRDDR
7U27 +2V5D B03b B07C ANALOG I/O
+2V5
STABILIZER 3H50 VREF-VPRDDR +12VSW +12VSW
B01a

B04A PNX2015: AUDIO / VIDEO


B02A CHANNEL DECODER +1V2
B07D UART
+1V2
B01a
+3V3-STANDBY +3V3-STANDBY
+2V5 +2V5
+3V3
B05C VIPER: A/V + TUNNELBUS
B05f
B01a +3V3
B01a
5T20 +2V5D-PLL +3V3 +3V3
+5V2-STBY B01a
+5V2-STBY
B01b
B08A AUDIO: AMPLIFIER
5T21 +2V5A-PLL VREF-PNX VREF-PNX
+12VSW +12VSW B04c +3V3-STANDBY +3V3
B05f
5T23 +2V5A B01a
VREF-AUD-POS VREF-AUD-POS B08b +12_20V +12_20V
B03b
5T24 +2V5A-XTAL B05D VIPER: SUPPLY
3D43 7D24 VP
+1V2 +1V2
+2V5A-ADC B01a
5T25 B04C PNX2015: TUNNELBUS

+2V5 +2V5 +2V5 +2V5 B08b -12_20V -12_20V


5T26 +2V5F B01a B01a

3L38 3L20 VREF-PNX 5Q07 +2V5-VPR 5D16 VN


+3V3 +3V3 B05c B05b
B01a
+3V3 +3V3
5T27 +3V3F B01a
B04D PNX2015: DDR INTERFACE B08B AUDIO: CONNECTORS
+1V2 +1V2 +1V2 +1V2
B01a B01a B05E VIPER: EEPROM
7T21 +1V2_ATSC
+2V5 +2V5 +3V3 +3V3 1M02
B01a B01a
1 5M10 -12_20V
5T28 +1V2F B08a
5L52 +2V5-DDRPNX +3V3-STANDBY +3V3-STANDBY
B04f 2 5M11
7T20 B05f
CN1M02
+3V3 5L51 3L38 VREF-DDRPNX 3
6 CONTROL +5V2-STBY +5V2-STBY 1M02
+12VSW B01b
VSND_+18v PSU 4
5 SUPPLY 5M12 +12_20V
1M02 5 B08a
2 B08B
VSND_-18v AUDIO B02B MAIN TUNER B04E PNX2015: STANDBY & CONTROL B05F MISCELLANEOUS 6 5M09
1
+1V2 +1V2 +5V2-STBY +5V2-STBY
+12SW +12SW B01a B01b
B01a +1V2-STANDBY +1V2-STANDBY 7M05
7T10 B05f +3V3-STANDBY B07d,B08a
5T11 +5VTUN IN OUT
IN OUT B03c,d COM B04e,f,g,
COM +3V3 +3V3 B05e
B01a
7M06 LED PANEL
+1V2-STANDBY J
+3V3-STANDBY +3V3-STANDBY IN OUT
B05f COM 1M21 B04e,f 1870
+5V 5M00 5 5 +3V3STBY +3V3STBY
+5V
B01b
+12VSW +12VSW
B01a G_16290_014.eps
010206
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 37

7. Circuit Diagrams and PWB Layouts


SSB: DC / DC
0M96 H3 2U13 C2 2U20 D9 2U27 B8 2U41 E11 3U01 C2 3U08 C6 3U15 E9 3U22 A5 3U29 D5 3U54 D11 3U87 A2 3U97 C6 3UA8 D8 6U22 D7 7U03-2 B7 7U13-2 A3 9U03 H14 FU08 D12 IU04 B4 IU11 C3 IU18 A6 IU25 C6 IU32 B6 IU45 C6 IU60 D8 IU78 B11
0M97 H4 2U14 A3 2U21 D9 2U28 B8 2U46 E13 3U02 C3 3U09 D6 3U16 E9 3U23 A6 3U30 D5 3U55 D10 3U88 A3 3UA1 B12 3UA9 D8 6U23 D8 7U05-1 C3 7U15-1 D10 FU01 A14 FU13 C7 IU05 B4 IU12 C2 IU19 A6 IU26 D7 IU36 B6 IU54 B8 IU61 G3 IU79 B12
1U01 A14 2U15 C4 2U22 C9 2U29 D8 2U58 B12 3U03 C3 3U10 C6 3U17 E9 3U24 A6 3U31 D4 3U56 D11 3U89 B2 3UA2 B11 5U00 A8 6U25 D12 7U05-2 C4 7U15-2 D10 FU02 B4 FU18 F12 IU06 B4 IU13 D6 IU20 A2 IU27 E7 IU37 E5 IU55 D8 IU62 A3 IU80 D12
2U09 F3 2U16 A5 2U23 F3 2U30 E8 2U72 B11 3U04 C3 3U11 E8 3U18 D9 3U25 B6 3U32 E4 3U82 C7 3U93 D10 3UA3 D12 5U02 A11 7U00 B5 7U07 E7 7U27 C13 FU03 A8 FU19 F12 IU07 B4 IU14 C6 IU21 B8 IU28 E8 IU40 D9 IU56 D10 IU63 A3 IU81 D13
2U10 G3 2U17 A5 2U24 B9 2U31 A6 2U73 D12 3U05 C4 3U12 B8 3U19 F9 3U26 B6 3U33 E4 3U83 C7 3U94 D11 3UA4 D14 5U03 C9 7U01-1 A6 7U10-1 D4 7U28 D12 FU05 E13 FU23 A4 IU08 C4 IU15 C6 IU22 B8 IU29 B6 IU41 D8 IU57 D11 IU65 D5 IU86 A7
2U11 E7 2U18 C6 2U25 A11 2U32 B7 2U85 B9 3U06 C5 3U13 B8 3U20 D8 3U27 B6 3U37 G2 3U85 A3 3U95 E11 3UA5 D13 6U11 E5 7U01-2 A6 7U10-2 D4 7U29-1 B12 FU06 C9 IU01 A14 IU09 C4 IU16 B6 IU23 A6 IU30 B6 IU42 A12 IU58 D10 IU66 D4 IU88 F9
2U12 C6 2U19 B8 2U26 D8 2U37 F9 3U00 C2 3U07 C6 3U14 D9 3U21 B8 3U28 B6 3U38 G2 3U86 A3 3U96 C7 3UA7 E11 6U21 E8 7U03-1 B6 7U13-1 A3 7U29-2 B11 FU07 E12 IU03 B3 IU10 C5 IU17 B6 IU24 A5 IU31 B6 IU44 C7 IU59 D11 IU68 E4 c111 E12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B1A DC / DC IU86
5U02

10u
IU42

B1A

2U14

3U85

3U22

2U25
100n

10R
10K

22u
7U01-1

2U17

22u
4 IU18 7 8
3U86 2 SI4936ADY

IU24
BC847BPN
A IU20
7U13-2 5
IU62 10K 1
12V/3.3V CONVERSION A
3U23 IU23 2U31

2U16
3

1u0
FU01
4R7 3n3 +12VSW
FU03 5U00
3U87

3U24
7U01-2

10R
10K

7U13-1 IU63 3U88 FU23


BC847BPN SUPPLY-FAULT 10u 1U01
5 6 IU01
6 100R GND-SIG IU19 +12VS

3U21

2U19

2U85

2U24
100n
2 4 SI4936ADY

10R

3n3

22u
T 3A 420
IU03 3 7U03-2 7U29-1

3UA1
2U72

2U58
BC857BS

100n
1

1K0

1u0
7U00

14
3U89

5 6

IU54
NCP5422ADR2G 1

IU22
10K

IU29
Φ

3U25
SI4936ADY

VCC
4

2R2
FU02 3 4 2
IU31 IU78

2U27

3U13
4 1 7U29-2

6K8
1n0
BST H1 3U26 IU30 2U32 BC857BS IU79

3U27
B 5 6
B

10R
GATE IU32
IU04 2 4R7
L1 3n3

3UA2

100K
IU21
7 7U03-1 3
1 IU17 7 8
IU05 16 SI4936ADY
VFB H2

2U28
10

1n0
2 GATE IU16 3U28 2

3U12
15

1K0
IU06 L2
8 1
1 2R2 IU36
IU07 5
COMP +1 IU14 3U08 IU44 3U82
9 6
2 -1
3U02
2U13

220R
100n

IU10 IS 3K3 6K8


3U05

220R 13 12
ROSC +2

2U18

3U83
100n
11

6K8
-2 12V/1.2V CONVERSION

GND
IU11
IU08
2U15

3U06
100n

39K
3U07
C C

3
6 3
GND-SIG
3U00 3U03 IU09 IU15 6K8 3U10 IU45 3U96
IU12 2 5 FU13 FU06
7U05-1 7U05-2
BC847BS BC847BS IU25
33K
1
10K
4
3K3 6K8 +1V2
3U01

3U04
33K

22K

2U12

3U97

2U22
100n

6K8

22u
BAS316 5U03 7U27
TS2431

3UA3
3U54

10R

2K2
3U09 6U23 10u 3U55 IU56 IU80
6 1 K A 3
3UA8 IU60

3U20

2U20

2U21

3U18

1% 220R
100n
10R

3n3
GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG GND-SIG IU13 6K8 10K
+2V5 STABILIZER

IU57
7U15-1 2 7U28 R
68R 2
BC847BS
3UA9

IU55
1

IU40
IU81

2
PHD38N02LT 2U73 3UA4 1%
3U29

3U56
D 1
D
1K0

1K0
68R
1 4 3
2U26 1n0 1K0

2U29

3U14

6K8
BC857BS BC857BS

1n0
IU26

3UA5
7U10-1 2 7U10-2 5

47R
IU65 100n IU58 PDZ9.1-B
3U31 3U93
3

BAS316
IU66

6U22

IU41
6 3 IU59
10K 10K 3U94 6U25 FU08
3U30

5 +3V3
1K0

7U15-2
3U32

2U30
BC847BS
10K

1n0
3U33 3U11 3K3

2U11

3U15
IU68 4

IU27

1K0
1u0
IU28 FU07

3U95
+2V5

2K2
10K IU37 220R
BZX384-C9V1
6U11

2U46
7U07

1u0
BC817-25W

3U16

3U17

c111
E E

4K7

1% 1K0
BZX384-C18
BOOSTER

6U21
FU05
+2V5D
12V UNDER-VOLTAGE DETECTION GND-SIG GND-SIG
3UA7 1%

2U41

1u0
1K0

FU18
ENABLE-3V3
0V

F IU88 3U19 FU19


ENABLE-1V2 F
22K 0V
2U23

100p

2U37

470n
2U09
IU61
100p
1% 470R

3U38

2U10

100n
6K8

3U37

G GND-SIG GND-SIG GND-SIG


G

9U03

H 0M96 0M97 GND-SIG


H

G_16290_021.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 38

SSB: Supply + RS232


1 2 3 4 5 6 7 8 9
1H07 E2 FU46 E2
1J02 A1 FU47 F2

B1B SUPPLY + RS232 B1B 1U02 E9


1U03 E9
FU48 F2
FU49 F2
2U40 B4 FU50 F2
2U48 B2 FU51 E8
1J02 2U49 B2 FU52 E8
FU04 -12-16V-NF 2U50 B2 IU43 B6
1
A 2
3
FU11
FU10
GND-D FU12
+12-16V-NF A 2U51 B2
2U52 B3
IU46 B5
IU47 B6
5U35
4 2U53 B3 IU64 E7
FU14 5U36
5 +5V2-STBY 2U54 B3 IU70 E7
6 FU15 2U55 C7 IU72 E4
7 FU16
5U37 2U56 D2 IU73 E5
8
FU17 5U38
9 +12VS 2U60 D2 IU74 F4
10 2U61 C8 IU75 F5
0V2 FU20 3U47 STANDBY
11 +12VSW +5V2-STBY +5V2-STBY 2U63 D5 IU84 D7
0V3 FU21 3U48 100R BACKLIGHT-CNTRL-OUT
12
3V2 FU22 100R LAMP-ON-OUT 2U64 D7 IU85 D7
13
2U65 D7 IU87 E5
B13B-PH-K-S(LF)(SN) 2U66 D5 IU90 C3
2U48

2U49

2U50

2U51

2U52

2U53

2U54

2U40

3U39

100K
B B
100p

100p

100p

100p

100p

100n

100n

1u0
3U39 B7 IU91 C2
7U25-2 3U42 B6 IU92 D2
7U25-1
3U44 C6 IU93 D6
7 8 5 6 3U47 B3 IU94 D6
IU43 2 SI4936ADY 4 SI4936ADY
3U48 B3 IU95 D6
+5V2-STBY 3
IU46 3U42 IU47 1 FU33 3U72 C3 IU96 E6
POD-MODE 7U24 +5V
BC847BW +5V 3U73 C3 IU97 E7
0V 47K
3U74 C1 IU98 E7
3U75 D2 IU99 F5

3U44

2U55

2U61
100n
47K

1u0
3U76 D2
3U72

150R
3U73

150R
3U77 D2
3U74

1K0

3U79 E7
C FOR FACTORY IU90 C 3U81 E8
3U90 E3
USE ONLY IU91
7U20
3U91 E3
BC847B 3U92 F3
3V9 3U98 E8
2U60

7U21 9U13 3U99 E8


10n

3 1
TS431AILT RES 5U35 A3
+3V3-UART
K

NC

IU92 3U75 +3V3-UART 5U36 A3


4
REF

5U37 A3
1K0 FU30
NC

5U38 A3
A

10u 16V

RES
3U76

3U77

2U56

7U20 C3
1K0

1K5

5 2 7U22

D ST3232C
Φ
16
VCC D 7U21 D1
7U22 D6

+3V3
2U63 IU93 1 RS232 IU84
7U24 C6
C1+ 6 2U65 7U25-1 B7
100n IU94 3 V-
7U25-2 B8
C1- 2 100n 2U64 FOR 9U01 F6
2U66 IU95 4 V+
C2+ IU85 100n FACTORY 9U02 F6
3U91

3U90
10K

10K

100n IU96 5 9U07 E3


1H07 C2- USE ONLY 9U13 C6
FU40 JTAG-TRST 1U02 9U14 F6
1 IU72 IU73 IU70 3U98 RES FU51
FU41 EJTAG-DETECT GLINK-TXD 9U15 11 14 9U15 E5
2
FU42 EJTAG-TDI RES 10 T1 IN OUT
T1 7 1
3 T2 T2 IU64 100R 3U99 RES FU52 2 9U16 F5
E 4
5
FU43 EJTAG-TDO IU87
13
R1 R1
12
100R 5 4
3 E FU04 A2
8 IN OUT 9 FU10 A2
FOR FACTORY 6 TXD R2 R2

GND
FU44 EJTAG-TMS B3B-PH-SM4-TBT(LF) FU11 A1
7
RXD 1U03 FU12 A3
USE ONLY 8
FU45 EJTAG-TCK 15 IU97 3U79 RES FU31
9 1 FU14 A1
10 IU98 100R 3U81 RES FU32 2 FU15 A1
FU46 9U07 RESET-SYSTEM
11 3 FU16 A3
FU47 100R 5 4
12 IU99
FU48 FU17 A1
13 FU49
3U92

B3B-PH-SM4-TBT(LF)
10K

FU50 FU20 B2
14 RES
FU21 B2
5-147279-3 IU74 IU75 FU22 B2
GLINK-RXD 9U16
FU30 D6
F +3V3 RES
9U01 RES F FU31 E8
FU32 E8
9U02 RES FU33 B8
FU40 E2
9U14 RES
FU41 E2
FU42 E2
G_16290_022.eps FU43 E2
3104 313 6095.3 010206 FU44 E2
FU45 E2

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 39

SSB: Chanel Decoder


1 2 3 4 5 6 7 8 9 10 11 12 13 1T10 H1 IT30 B1
1T11 E6 IT31 E7

B2A CHANNEL DECODER B2A


2T30 A2
2T31 B2
2T33 B2
IT32 F7
IT33 F6
IT34 E6
2T34 C2 IT36 G8
2T35 D2 IT37 E7
2T36 D8 IT38 E6
A 5T20 FT20
A 2T37 D6
2T38 D6
IT40 G6
IT41 I5
+2V5D-PLL
220R 2T39 D6 IT45 F1
2T40 D6 IT46 F2

2T30

10n
2T41 D7 IT47 F1
2T42 D7 IT48 F2
2T43 D7 IT49 F2
5T21 FT21
+2V5A-PLL 2T44 D7 IT50 F3
220R 2T45 D8 IT51 H4
2T46 D7 IT52 I2

2T31

10n
2T47 D11 IT53 I3
B B 2T48 D12 IT54 I4
2T49 D12
5T23 FT22
+2V5 IT30 +2V5A 2T50 D12

+2V5A-XTAL
+2V5A-ADC

+2V5A-PLL
2T52 E5

+2V5D-PLL
220R
2T53 E6
2T33

+1V2F
+1V2F
+1V2F
+1V2F
+1V2F
+1V2F
+1V2F
+1V2F

+2V5F
+2V5F

+3V3F
+3V3F
+3V3F
+3V3F
+3V3F
+3V3F
+2V5A
+2V5A
+2V5A
+2V5A
10n

2T54 E6
2T56 E7
2T57 E7
5T24 FT23
+2V5A-XTAL 2T58 E6
220R 2T59 E7
C C 2T60 E12
2T34

10n

2T61 F12
2T62 F7
2T63 F7
5T25 FT24
+2V5A-ADC 2T64 G2
220R 2T65 G7
2T66 G7
2T35

10n

2T67 H5
3T31 G5
5T26
3T35-1 G11
FT25
3T35-2 G12
D 220R
+2V5F
D 3T35-3 G11
5T27 FT26

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
3T35-4 G12

100n 16V
+3V3 +3V3F

2T36
600R 3T36-1 G11

2T37

2T38

2T39

2T40

2T41

2T42

2T43

2T44

2T46

2T45

2T47

2T48

2T49

2T50
3T36-2 G12
3T36-3 G11
3T36-4 G12
2T52 IT38 7T22 3T37-1 F12
CHDEC-CLK

100
5T28 FT27

97
95
26
21

10
11

31

16
23
33
45
52
63
80
92

18
64

32
44
50
70
79
88
NXT2004
3T37-2 F12

1
+1V2_ATSC +1V2F 10n 1T11
Φ
IT34

AVDD-OSC
AVDD-PLL

DVDD_PLL
220R RES AVDD AVDD_ADC VDD1.2 VDD2.5 VDD3.3 3T37-3 F12
29
25M14 IN VSB/QAM 3T37-4 F12

2T53

2T54

RES
33p

33p
E 30
OUT
OSC_XTAL
15 E 3T38 G7

1u0 16V

1u0 16V
NC 3T39 H7

2T58

2T59

2T56

2T57
IT31 4 22

10n

10n
VREF_N 3T40 F11
5 AT35
VREF_P
IT37 6
INCM ADC OSC_CLK
28 3T41 F7
7
INP
2T60
3T42 F2
8 35
INN PDET_REF_OUT
+12VSW +12VSW +1V2 FAT-ADC-INP IT01 3T43 F11
100n
3T41 37 34 3T40 FAT-IF-AGC 3T44 F7
PDET_COMP_IN IF
FAT-ADC-INN 220R 1K0
FT29 FT28 3T44 41 38 3T43
3T45 F1
UC_EN AGC AUX AUX-IF-AGC
3T46 F1
3T42

220R IT32 1K0 2T61


8K2

1u0 16V
2T62

2T63
59 40

10n
3T48 POWER_RESET RF 100n 3T47 F2
7T20-2
F IT45 3T45 IT46 +3V3
4 3T37-4 5 F 3T48 F6
3

BC847BPN 4K7 78 49 DV1F-DATA8_ERR


0 ERR
IT47 47K IT48 7T21 77 I2C_SLAVE_ADDR 68R
3T49 F3
3T46 3T47 1
7T20-1 1 SI2306DS RESET-FE-MAIN
IT33 51 3 3T37-3 6 DV1F-CLK 3T50 F1
+3V3 BC847BPN CLK
3T51 42
2

47K 1K0 SCL MPEG 68R 3T51 F6


IT49 100R 3T52 43 I2C 53 2 3T37-2 7 DV1F-DATA9_SOP
3T49 SDA PKT_SYNC
3T50

3T52 F7
47K

100R 68R
IT50 90 55 1 3T37-1 8 DV1F-VALID
2T64 47K 0 DATA_EN 3T53 G6
3T53

3T54

2T65

2T66
+3V3F
1K0

1K0

91

68p

68p
+1V2_ATSC 1 68R 3T54 G6
89 71 1 8 DV1F-DATA0
100n 2 0 3T35-1 68R
87
3 1
69 2 7 DV1F-DATA1 3T55 H2
86 GPIO 68 3 6 3T35-2 68R DV1F-DATA2
4 2 3T56 H3
3T31

3T35-3 68R
RES

4 5
4K7

84 67 DV1F-DATA3
5 3 3T57 I3
48 MPEG_DATA 66 1 8 3T35-4 68R DV1F-DATA4
6 4 3T36-1 68R
+3V3F 47 62 2 7 DV1F-DATA5 3T58 I4
G IRQ-FE-MAIN
I2C ADRESS=24/26 7 5
6
58
56
3
3T36-3
6 3T36-2
68R 4
68R
5
DV1F-DATA6 G 5T20 A2
I2C-SDA-TUNER 7 DV1F-DATA7
I2C-SCL-TUNER 98 3T36-4 68R 5T21 B2
BIAS_RES SER_DATA
FM-TRAP
AGND DGND DGND
5T23 B2
SDA-DMA

SCL-DMA

3T38 5T24 C2

3
12
13
14
20
25
27
96
99

2
17
19
24
36
39
46
54
57
60
61
65
72
73
74
75
76
81
82
83
85
93
94
IT36
9T10 IT40 5T25 C2
33K
RES
3T39 5T26 D2
+3V3F
5T27 D2
33K
5T28 E2
2T67 7T20-1 F1
9T11

9T12

7T20-2 F2
H 3T55 3T56
100n
H 7T21 F3
8

+3V3 +3V3 7T23 7T22 E8


4K7 4K7 PCA9515ADP
VCC 7T23 H4
1T10 9T10 G5
IT51
+5V 3 SDA0 SDA1 6 9T11 H3
5 6
4 9T12 H3
3 IT52 3T57
2 9T13 I5
100R 3T58 2 SCL0 SCL1 7 IT41
1 AT35 E11
IT53 100R
B4B-PH-SM4-TBT(LF) 5 EN 1 FT20 A2
NC
GND FT21 B2
RES IT54
I I FT22 B2
4

FT23 C2
FT24 C2
FT25 D2
9T13 FT26 D2
RES FT27 E2
G_16290_023.eps
3104 313 6095.3 010206
FT28 F3
FT29 F2
IT01 F12
1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 40

SSB: Main Tuner


1 2 3 4 5 6 7 8 9 10 11 12
1T01 D5
1T04 B1

B2B MAIN TUNER B2B 2T10 C1


2T11 C2
2T12 C2
2T13 C2
2T14 D2
2T15 D2
A A 2T16 C8
2T17 D9
2T18 D2
2T19 D6
2T20 D6
2T21 D9
2T22 E7

1T04
MAIN DIG TUNER C0 2T23 E3
2T24 D12
TD1316O/FGHP
2T25 C2
B TUNER B 2T26 D2
18 17 2T27 E2
DC_PWR

3T10 C12

IF_AGC
IF_OUT
+5VTUN
RF_GC

19 16

VTUN
FM-T

3T15 C3
OOB

DNU

SDA

IF_1
IF_2
SCL
+5V

NC
AS

3T18 C4
3T20 C11
IT12 10
11
12
13
14
15
IT10

3T15
1
2
IT11 3
4
5
6
7
8
9

4K7
3T21 C4
IT13 IT60 3T20 IT61 3T10 IT62 5T11 3T22 E2
IT14 +12VSW +5VTUN 3T23 E2
2T10

2T25

2T11

2T12

47R 47R 220R


IT15 IT16 3T25 E2
3T18
C 7T12
BC847BW C 3T27 E2
10n
10n

10n

10n

4K7 7T10
+5VTUN LD1117DT 3T28 E2

3T21
3T29 E7

4K7
FT10 FT11
3 2
+5VTUN +5VTUN IN OUT 5T11 C12
2T13

2T16 7T10 C11


COM
2T14

2T15

1u0 7T12 C3
1

2T24
10n

1u0
10n

7T13 D7
10n

AT13 D4
FT12

1
7T13 AT14 D4
UPC3218GV
1T01 AT20 D6

VCC
X7351P
44M IT17 IT18 2T17 IT19 AT23 D6
2T18

2 INPUT1 OUTPUT1 7
D D
10n

AT20 2T19 FAT-ADC-INP


AT14 1 7 FT10 C2
IT08 I O 10n 10n
14 8 2T20
AT13
IGND OGND AT23 3 6
IT21 2T21 IT22 FT11 C3
10n FAT-ADC-INN
IT09 2 4 IT24 INPUT2 OUTPUT2 FT12 D2
10n
6 9 FT15 E3

GND1

GND2
2T26 GND GND IT25
11 13 4 VAGC AGC CONTROL
FT30 E7
180p
IT08 D2
2T27
IT09 D2

5
180p FT15 2T22 IT10 C2
220R

3T27

IT11 C2
+5VTUN

+5VTUN

10n
IT12 C2
3T22

E E
1K0

IT13 C3
2T23

100n

IT14 C1
3T23

3T29

1K0
IT15 C4
220R

IT16 C4
3T28

3T25
4K7

FT30 IT17 D7
4K7

IT18 D9
IT19 D9
IT27 IT26
IT21 D9
IT22 D9
IT24 D7
I2C-SDA-TUNER
I2C-SCL-TUNER

F F IT25 D7

AUX-IF-AGC
FAT-IF-AGC

IT26 F2
FM-TRAP

IT27 F2
IF-ANA

IT60 C11
IT61 C11
IT62 C12

G G

G_16290_024.eps
3104 313 6095.3 010206

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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 41

SSB: MPIF Main: Video Source Selection


1 2 3 4 5 6 7 8 9 10 11 12 13
0T00 I3

MPIF MAIN: VIDEO SOURCE SELECTION 0T10 I4

B3A +5V
B3A 0T11 I5
0T12 I6
0T13 I6
1A01 F7
1M36 D5
A 2A97 A 1MM1 I2
2A04 F3
100n
2A05 G4
7A00-4 2A06 H3
PNX3000HL/N2
7A20 2A07 E3
IA10 FC02 BC847BW 2A08 E3
2A10
CVBSOUTIF-MAIN 123
CVBS_IF SOURCE SELECT 2A09 E3
2A11 22n
IA11
126
AND DATA LINK 2A10 B3
AV1_CVBS CVBS1

3A04
22n 2A11 B3

2K2
2A30 IA12 IA13
CVBS-IN 1 19
CVBS2 CVBS_OUTA 2A12 B3
IA14 IA15
B 22n
12
CVBS_DTV CVBS_OUTB
22 B 2A13 B4
2A14 B5

2A12

2A13

2A14
RES

RES
22n

22n

22n
4 60 2A15 C3
CVBS|Y3 STROBE1N STROBE1N-MAIN
2A16 C3
5 61 STROBE1P-MAIN
C3 STROBE1P 2A17 C3
8 62 DATA1N-MAIN
2A18 C3
2A15 CVBS|Y4 DATA1N
AV2_Y-CVBS 2A20 C5
9 63 DATA1P-MAIN
22n 2A16 C4 DATA1P 2A21 C6
AV2_C IA17
15 2A23 E4
2A17 22n Y_COMB 50
FRONT_Y-CVBS IA16 STROBE3N STROBE3N-MAIN 2A24 E4
16
2A25 E4
C FRONT_C
22n 2A18
6
C_COMB
STROBE3P
51 STROBE3P-MAIN C 2A26 E10
2A31 22n GND_VSW 52

2A20

2A21
RES

RES
2A27 E8

22n
AV7_Y-CVBS DATA3N-MAIN

22n
DATA3N
22n 2A94 53 2A29 D8
25 DATA3P-MAIN
R|PR|V_1 DATA3P 2A30 B3
2A95 22n
26 2A31 C3
G|Y|Y_1 55
2A96 22n STROBE2N STROBE2N-MAIN 2A32 E8
27
B|PB|U_1 2A94 C8
56 STROBE2P-MAIN
22n STROBE2P
30 2A95 C8
R|PR|V_2 57 DATA2N-MAIN
31
DATA2N 2A96 D7
G|Y|Y_2 58 DATA2P-MAIN 2A97 A11
D 1M36
32
B|PB|U_2
DATA2P
D 3A01 G3
FA10 3A02 G4
46 HV-PRM-MAIN
1 5A10 FA11 HV_PRIM
FRONT_Y-CVBS 3A60 FA25 +5V 49 IA18 3A03 G4
2 VCC_DIG
45 3A04 B11
470R 3 HV_SEC
FRONT_C 3A61 FA26 48
4 GND_DIG 3A05 G3

2A29

100n
470R 5 IA19
47

2A26
3A62 FA27 3A06 G3

22n
AUDIO-IN5-L 6 VD2V5
100R 7 54
3A60 D3
AUDIO-IN5-R 3A63 FA28
8 FUSE10 3A61 D2

2A27

22n
100R 5A64 9
AUDIO-HDPH-L-AP FA29
10
64
VCC_I2D
3A62 E3
AUDIO-HDPH-R-AP 5A65 600R FA30 11 3A63 E2
600R 59
E FA31 B11B-PH-K
GND_I2D
E 5A10 D7
2A07

2A08

2A09

2A23

2A24

2A25
100p

100p

5A11 E7
2n2

2n2

2n2

2n2

5A11 FA12
+5V 5A64 E3
5A65 E2

2A32

100n
7A00-4 A9
7A20 A11
AA47 H7
2A04
FA01 G7
1A01
1n0
FA32
FA02 G7
SDA-DMA 1
SCL-DMA FA33 FA03 G7
2
POWER-DOWN_BOLT-ON FA34 FA10 D12
F AUDIO-IN3-R FA35
3
4 F FA11 D8
5
AUDIO-IN3-L FA36 FA12 E8
6
7 FA25 D4
CVBS-IN FA37
8 FA26 D4
9
DMMI_B-PB-IN FA38
10
FA27 E4
11 FA28 E4
DMMI_G-Y-IN FA39
12 FA29 E4
13
DMMI_R-PR-IN FA40
14
FA30 E4
H_SYNC_IN FA41
15 FA31 E4
FA01 16 FA32 F7
G 3A05 17
G
3A06

3A01

3A02

3A03

2A05

FA33 F7
75R

75R

75R

75R

FA02
1n0

AV1-AV6_FBL-HSYNC 18
100R 19 FA34 F7
FA03 20 FA35 F7
21
22 FA36 F7
FA42
FA43
23 FA37 F7
AUDIO-OUT1-L 24
AUDIO-OUT1-R FA38 F7
+3V3-STANDBY 25
RC 26 FA39 G7
V_SYNC_IN
FA44
27 FA40 G7
HP-DET-R-DC 28
SC-STANDBY FA45 FA41 G7
29
ITV-IR-SW-RESET FA46 FA42 G7
30

H AA47 31
32 H FA43 G7
FA44 H7
2A06

1n0

33 34
FA45 H7
AF732L-N2G1A
FA46 H7
FC02 B6
IA10 B3
1MM1 0T00 0T10 0T11 0T12 0T13 IA11 B4
EMC HOLE
IA12 B4
IA13 B10
IA14 B5
IA15 B10
I I IA16 C6
IA17 C5
IA18 D10
IA19 D8

G_16290_025.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 42

SSB: MPIF Main: Supply


1 2 3 4 5 6 7 8
2A35 A6

B3B MPIF MAIN: SUPPLY B3B 2A37 B6


2A38 B5
2A39 C4
2A40 C4
FA13 5A12 2A41 C4
+5V
2A42 D6
A 220R
A 2A43 D6

2A35

100n
3
2A44 E5
IA20
1 7A10 2A45 E4
BC847BW
3V9 3A10 B5
2
IA21 FA14 3A11 B5
9A10 VREF-AUD-POS
7A00-3 3V2 3V2
3A12 B5

560R
3A10
PNX3000HL/N2 3A13 C4

2A37

100u 4V
3A14 F4
MPIF-SUPPLY IA22
3A15 F4
E/W & CONTROL 3A16 E5
B 2A38
B 3A21 F6

3A11
2

1K2
VOUTO
1n0 5A12 A6
3 IA23 5A13 D7
VAUDS VREF-AUD
5A14 D5
1V4
5A15 E4
20

3A12

1K2
VDEFLO 7A00-3 B2
7A10 A5
21 9A10 A6
VDEFLS
IA24 3A13 AC40 F6
13
RREF
47K
FA13 A6
FA14 A7
C BGDEC
7 C FA15 D6
IA25
FA16 D5
33

2A39

2A40

2A41
100n

1u0

1u0
FUSE9 FA17 E4
10 IA20 A5
FUSE8
IA21 A6
23
FUSE7 IA22 B5
IA23 B5
GND_FILT
11 IA24 C4
IA25 C4
29
GND_RGB IA26 E3
D GND_VADC
34 D IA27 E3
FA15 5A13 IA28 F3
14 +5V
VCC_FILT IA29 F3
220R
IA30 F6

10u 16V
FA16 5A14

2A42

2A43

100n
28 +5V
VCC_RGB
220R
FA17 5A15

2A44

100n
35 +5V
VCC_VADC
220R
18
TESTPIN3
2A45

100n

24
TESTPIN2
E E
36 +5V
EWVIN
IA26
38
REW
37 IA27
3A16

10K
RES

EWIOUT

44 IA28 3A14
SCL SCL-DMA

IA29 100R 3A15


43 SDA-DMA
SDA
100R IA30
42 IRQ-MPIF
IRQ
3A21 AC40
F XREF
40 CLK-MPIF F
470R
39
ADR +5V
41
FUSE6

G_16290_026.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 43

SSB: MPIF Main: IF & SAW Filter


1 2 3 4 5 6 7 8 9
1A10 C2

B3C MPIF MAIN: IF + SAW FILTER B3C


2A19 B5
2A47 B5
2A49 B4
2A50 B2
2A51 C9
2A52 C3
2A53 C4
2A54 D7
A A 2A55 D3
2A56 D7
+5V 2A57 D7
2A58 E3
2A90 C1
3A17 C7
220R
5A16

100n
3A18 C8
IA36 2A47 3A19 C9
+5VbM
+5VaM
3A20 C4
IA34 5A16 B1
2A50

10n

B +5VTUN
5A17
B 5A17 B4
5A18 C1
220R IA37
IA31 2A19 IA35 7A00-2 C4

2A49

10n
7A11 C8
10n
9A15 C7
AA18 C3
+5VbM
AA19 C3

109

103

104
7A00-2

112

110
AA46 C1
PNX3000HL/N2
3 CVBSOUTIF-MAIN FA20 D3

GND1_IF

VCC_IF

DTVIFPLL

DTVIFINP

DTVIFINN
IA41 IA40 IA45 7A11
2A52 3A20 111 120 3A17 IA38 IA31 B5
1 BC847BW
VIFPLL CVBSOUTIF
1A10 IA34 B5
C AA46
2A90
OFWM1967L
AA18
100n 390R
107 116
100R
2
IA39 3A18 3A19
C IA35 B6
IF-ANA 2
I1 O1
7
VIFINP IF PART DTVOUTP 180R 180R IA36 B2
3 8 9A15
10n I2 O2 AA19 108 117

2A51

330p
VIFINN DTVOUTN RES IA37 B5
5A18

560n

1
99 IA38 C8
4 11
SIFINP IA39 C8
2A53
5 12 122

10n
VCC1_VSW +5VaM
6 NC 16 100 IA40 C4
SIFINN IA42
9 17 118
VCC_SUP +5VTUN IA41 C4
10 GND IA43
13 101 125 IA42 D7
SIFAGC VCC2_VSW +5VaM
14 IA44 IA43 D4
15 114
105 2NDSIFAGC IA44 D7
2A55

18
10n

D TUNERAGC
102
D IA45 C7

2A56

2A57

2A54
1u0

1u0

10n
FA20 DTVIFAGC

GND_SUP

TESTPIN1
45M75 113

GND2_IF
2NDSIFEXT

FUSE5
106
FUSE4

115

121
2A58

119

124
10n

E E

G_16290_027.eps
3104 313 6095.3 010206

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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 44

SSB: MPIF Main: Audio Source Selection


1 2 3 4 5 6 7 8
2A01 E3

MPIF MAIN: AUDIO SOURCE SELECTION 2A02 E3

B3D B3D 2A33 E3


2A34 F3
2A60 A3
2A61 A3
A IA47
A 2A62 A4
2A63 B3
2A64 B4
7A00-1
2A65 C4

2A60

2A61

2A62

100n
PNX3000HL/N2

1u0

1u0
2A66 E3
2A67 E3
91 AUDIO SOURCE SELECT
VAADCP 2A68 E3
IA48 2A69 E3
+5VTUN 77
VCC_AADC
IA49 IA50 2A71 F3
+8V-AUD 9A19 98
VCC1_ASW 2A73 F3
2A98 F7
B 88
VCC2_ASW B

2A63

2A64
100n

100n
2A99 F7
92 7A00-1 A5
MIC2N
9A19 B4
93 IA01 F8
MIC2P
94 IA02 F8
MIC1N
IA08 E7
95
MIC1P IA09 F7
IA32 E4
IA51
89 IA33 F4
VAADCREF
90 IA47 A3
C VAADCN C IA48 B3

2A65

100n
97
GND1_ASW IA49 B4
96 IA50 B4
FUSE1 IA51 C4
78 IA53 E4
FUSE2
76
IA55 E4
GND_AADC IA57 E4
71 IA58 E4
FUSE3
87
IA63 F4
GND2_ASW
IA65 F4

SCART1R

SCART2R
SCART1L

SCART2L
DSNDR1

DSNDR2
DSNDL1

DSNDL2
AMEXT
D D IA90 E4

LINER
LINEL
IA91 E4

R1

R2

R3

R4

R5
L1

L2

L3

L4

L5
128
127
86
85

84
83

82
81

80
79

75
74

73
72

68
67

70
69

66
65
17
2A66 IA53
AUDIO-IN1-L
1u0 2A67 IA55
AUDIO-IN1-R
2A68 1u0 IA57
AUDIO-IN2-L

E AUDIO-IN2-R
1u0 2A69 IA58
E
2A01 1u0 IA90
AUDIO-IN3-L
1u0 2A02 IA91 AUDIO-OUT1-R
AUDIO-IN3-R
2A33 1u0 IA32 AUDIO-OUT1-L
AUDIO-IN4-L IA08 2A98 IA01 DSNDR1
1u0 2A34 IA33
AUDIO-IN4-R IA09 1u0 2A99 IA02 DSNDL1
2A71 1u0 IA63
AUDIO-IN5-L 1u0
1u0 2A73 IA65
AUDIO-IN5-R

F 1u0 F

G_16290_028.eps
3104 313 6095.3 010206

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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 45

SSB: MPIF Main: Audio Amplifier


1 2 3 4 5 6 7 8 9 10
2A76 B2

MPIF MAIN: AUDIO AMPLIFIER


2A78 C5

B3E B3E 2A79 C4


2A80 C3
2A81 D5
2A83 D6
2A84 E5
2A85 E5
A A 2A86 F2
+5V2-STBY 2A87 G4
A-PLOP +5V2-STBY 2A92 G4
3A08 G2

3A23

100K
3A23 A3

BAS316
3A24 B7

6A11
IA68 3A24 IA69
7A08 BC857BW 3A25 B3
BC847BW 3 7A15 IA70
5V 10K 3A26 B2
IA72 3A25 IA71
1 3A27 B6
680K 0V 3A28 C6
B 2
B 3A29 C8

2A76

3A26
9A01

47K
1u0
3A30 C4
+5V 3A31 D3
3A32 D4
3A27 3A33 D6
7A04-1 3A34 D6
TS482IST 33R

8
ADAC7 3 FK02
1
2A78 3A28
AUDIO-HDPH-L-AP 3A35 D8
IA73
2 3A36 E5
IA88 16V 100u IA74 33R
3A37 E4

4
IA75
7A16
3A29 3A38 E5
C 3A51 IA76 2A79
BC817-25W
1K0 C 3A39 F3
3A41 F2
27K 9A02
33p 3A42 F2
3A30

2A80 RES
+5V 3A43 G3
15K 3A44 G3

1u0
RES RES 3A51 C3
3A31 3A32
3A52 E4

2A81

100n
15K IA77 27K 6A11 B2
7A04-1 C4
7A04-2 3A33
TS482IST 7A04-2 D5
33R 7A05-2 E1
D D

8
ADAC8 5
2A83 3A34 FK11
7 AUDIO-HDPH-R-AP 7A08 B3
6 33R 7A14 D8
IA89 16V 100u IA78

4
7A15 B7
7A14
BC817-25W 7A16 C7
IA92 3A35 7A17 F3
IA79 2A84 9A01 B4
1K0
9A02 C5
33p
3A52 3A36 FA21 G4
FK02 C6
27K 15K
FK11 D7
E E
RES
2A85

1u0 IA05 F3
RES RES IA68 B3
3A37 3A38
IA69 B7
+12VSW 15K IA80 27K IA70 B8
+12VSW
IA71 B3
7A05-2 IA72 B2
LM324 3
4 IA73 C3
5 IA81
VREF-AUD 3A41 IA82 IA74 C6
7 1 7A17
6 BC847BW IA75 C8
1K0
2
11 IA76 C3
3A42

10K

F IA05 F IA77 D3
IA78 D6
IA79 E5
IA80 E5
2A86

3A39
1n0

33R

IA81 F2
IA82 F3
FA21
IA83 G2
+8V-AUD IA88 C4
IA89 D6
3A43

IA92 D8
10K

1u0
2A87

IA97 G4
G IA83 IA97 G
3A08

3A44

2A92
18K

10K

1u0

H H

G_16290_029.eps
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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 46

SSB: PNX2015: Audio / Video


1 2 3 4 5 6 7 8 9
0E02 F5

PNX2015: Audio / Video 0E03 F5

B4A B4A 2J01 A1


2J03 A6
2J06 B6
2J08 B6
VREF-AUD-POS
2J10 C6
A A 2J13 E6
2J16 E6

100n
2J01
7J00-7 2J18 E6
PNX 2015
5J00 2J20 F6
Φ
IJ00
+1V2 2L65 D1
Y5
AUDIO / VIDEO 2J03 120R
2L66 D1
ADAC_CLK
AVP1_DLK_VDDA N5
IJ01 100n 5J01 2LA5 B1
ADAC1 AH1 AVP1_DLK_VDDD M5
ADAC1 2LA6 B1
AH2 AVP1_DLK_VSSA P5
2LA5 ADAC1N 2J06 120R
AH3 AVP1_DLK_VSSD R5 2LA8 C1
ADAC1P
AVP1_DLK1DN R2 DATA1N-MAIN
3n3 100n 2LA9 D1
ADAC2 AG1 AVP1_DLK1DP R1 DATA1P-MAIN
ADAC2
B 2LA6
AG2
AG3
ADAC2N
ADAC2P
AVP1_DLK1SN
AVP1_DLK1SP
R4
R3
STROBE1N-MAIN
STROBE1P-MAIN
B 2LT0 E9
3J01 E4
AVP1_DLK2DN P2 DATA2N-MAIN
3n3
AF1 P1
3J07 F4
ADAC3 AVP1_DLK2DP DATA2P-MAIN
AF2 AVP1_DLK2SN P4 STROBE2N-MAIN 5J02
3J12 C4
ADAC3N IJ02
AG4 AVP1_DLK2SP P3 STROBE2P-MAIN 3J13 C4
ADAC3P +3V3
AVP1_DLK3DN N2 DATA3N-MAIN 2J08 120R 3JA2 E4
AE1 AVP1_DLK3DP N1 DATA3P-MAIN
ADAC4
AE2
ADAC4N AVP1_DLK3SN N4 STROBE3N-MAIN IJ03 100n 5J03 3L00 E9
AB5 AVP1_DLK3SP N3 STROBE3P-MAIN 3L01 E8
ADAC4P +1V2
AVP1_DTC_CLVSS T6
2J10 120R 3L02 E9
AD1 AVP1_DTC_VDD3 T3
ADAC5
AD2
ADAC5N AVP1_DTC_VDDA T4
100n
3L03 E8
AB4 AVP1_DTC_VSSA T5 9J22
ADAC5P 5J00 A6
C AC1
ADAC6
AVP1_HSYNCFBL1
AVP1_HSYNCFBL2
T1
T2 9J24
AV1-AV6_FBL-HSYNC
AV2_FBL
C 5J01 B6
AC2
ADAC6N AVP1_HVINFO1 M3 HV-PRM-MAIN 5J02 B6
AB3 AVP1_VSYNC1 M1
ADAC6P 5J03 C6
AVP1_VSYNC2 M2
ADAC7 AB1 5J04 D6
ADAC7

120R
3J12
120R
3J13
2LA8
AB2
ADAC7N AVP2_DLK_VDDA H5 5J05 E6
AA4 AVP2_DLK_VDDD G6
ADAC7P 5J06 E6
AVP2_DLK_VSSA J5
3n3 5J07 F6
ADAC8 AA1 AVP2_DLK_VSSD K5
ADAC8
AA2 AVP2_DLK1DN K2 6J07 D9
2LA9 ADAC8N +5V2-STBY
AA3 AVP2_DLK1DP K1 +12VSW
ADAC8P 6J08 D9
AVP2_DLK1SN K4
3n3
DSNDL1 AF3 AVP2_DLK1SP K3 AV6_VSYNC 7J00-7 A3
ADAC9
D 2L65
AF4
AF5
ADAC9N
ADAC9P
AVP2_DLK2DN
AVP2_DLK2DP
J2
J1 IJ53 IJ54 D 7J01 E8
7J02-1 F9
AVP2_DLK2SN J4
3n3

BAT54 COL
DSNDR1 AE3 AVP2_DLK2SP J3 7J02-2 E9

BAS316
ADAC10

6J07

6J08
AE4 AVP2_DLK3DN H2 5J04 9J22 C4
2L66 ADAC10N IJ04
AE5 AVP2_DLK3DP H1
ADAC10P +1V2 9J24 C5
AVP2_DLK3SN H4
3n3 120R
FLA8 E7

100n
2J13
AD3 AVP2_DLK3SP H3 IJ09
ADAC11
AD4 AVP2_DTC_CLVSS K6 IJ00 A5
ADAC11N 11V3
AD5 AVP2_DTC_VDD3 L3
ADAC11P IJ01 B5
AVP2_DTC_VDDA L4 5J05
IJ05

2LT0
AC3 L5 IJ02 B5

1u0
ADAC12 AVP2_DTC_VSSA
AC4 AVP2_HSYNCFBL1 L1 3JA2 120R
ADAC12N 120R IJ03 C5

100K

100K
100n

3L01

3L00
2J16
AC5 AVP2_HSYNCFBL2 L2 AV2_FBL
ADAC12P IJ04 D6
E I2S-MCH-LR U2
I2S_IN_SD1
AVP2_HVINFO1
AVP2_VSYNC1
G3
G1 3J01 120R E IJ05 E6
I2S-MCH-CSW U3 AVP2_VSYNC2 G2 AV6_VSYNC IJ55
I2S_IN_SD2 IJ06 5J06 IJ06 E6
I2S-MCH-SLR U4 4
I2S_IN_SD3 +3V3 IJ25 3L02 11V1 IJ07 F6
I2S-MAIN-D V4 I2S_OUT_SCK Y2 3 BC847BPN
I2S_IN_SD4 120R 11V1 7J02-2

100n
2J18
I2S-SUB-D V5 I2S_OUT_SD1 W1 IJ11 5 IJ09 E9
I2S_IN_SD5 FLA8 3L03 10K IJ26
W5 I2S_OUT_SD2 W2 RESET-AUDIO 1 7J01
I2S_IN_SD6 BC847BW 3
IJ11 E8
I2S_OUT_SD3 V1 470K 0V IJ25 E9
I2S-BCLK-MAIN V2 I2S_OUT_SD4 W3 3J07 68R I2S-MAIN-ND IJ07 5J07 2 0V
I2S_SCK_SYS
I2S_OUT_SD5 W4 IJ26 E9
+1V2 IJ27
I2S-WS-MAIN V3 I2S_OUT_SD6 Y4 6
I2S_WS_SYS 120R IJ27 F8

100n
0V

2J20
I2S_OUT_WS Y3 A-PLOP
CLK-MPIF M4 2 7J02-1 IJ53 D9
MPIF_CLK BC847BPN IJ54 D9
F U1
U5
I2S_SCK_XTRA
I2S_WS_XTRA
1
F IJ55 E8
0E02 0E03

3
2
1

G_16290_030.eps
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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 47

SSB: PNX2015: DV I/O Interface


1 2 3 4 5 6 7 8 9
3LR0 D4

PNX 2015: DV I/O Interface 3LR1 C4

B4B B4B 3LR9-1 D4


3LR9-2 E4
3LR9-3 D4
3LR9-4 D4
3LS0-2 D4
3LS0-3 D4
3LS0-4 E4
A A 3LS1-1 D4
3LS1-2 D4
3LS1-3 E4
3LS1-4 E4
7J00-2 B7
7J00-4 7J00-4 B2
PNX 2015
AJ10 D8
Φ
DV INPUT
DV4-CLK AK8 DV_CLK AD28 7J00-2
DV1_CLK PNX 2015
DV4-VALID AH8 DV_VALID AD29
B DV4-DATA0_SOP AG8
DV1_VALID
AB27
Φ B
DV4_DATA_0 DV1_DATA0 OUTPUT INTERFACE
DV4-DATA1_ERR AK7 DV4_DATA_1 AA30 MP-ROUT-0 A27
DV1_DATA1 RIN0
DV4-DATA2_0 AJ7 DV4_DATA_2 AA29 MP-ROUT-1 A28 LVDS_AN B26 TXPNXA-
DV1_DATA2 RIN1
DV4-DATA3_1 AH7 DV4_DATA_3 AA28 MP-ROUT-2 A29 LVDS_AP C26 TXPNXA+
DV1_DATA3 RIN2
DV4-DATA4_2 AG7 DV4_DATA_4 AB29 MP-ROUT-3 A30
DV1_DATA4 RIN3
DV4-DATA5_3 AF7 DV4_DATA_5 AB28 MP-ROUT-4 B28 LVDS_BN A25 TXPNXB-
DV1_DATA5 RIN4
DV4-DATA6_4 AK6 DV4_DATA_6 AC30 MP-ROUT-5 B30 LVDS_BP B25 TXPNXB+
DV1_DATA6 RIN5
DV4-DATA7_5 AJ6 DV4_DATA_7 AC28 MP-ROUT-6 C28
DV1_DATA7 RIN6
DV4-DATA8_6 AH6 DV4_DATA_8 AC27 MP-ROUT-7 C29 LVDS_CN D25 TXPNXC-
DV1_DATA8 RIN7
DV4-DATA9_7 AG6 DV4_DATA_9 AB30 MP-ROUT-8 C30 LVDS_CP E25 TXPNXC+
DV1_DATA9 RIN8
MP-ROUT-9 D27
RIN9
DV5-DATA0_SOP AF6 DV5_DATA_0 AF30 33R 3LR1 DV2A-CLK LVDS_DN B24 TXPNXD-
DV2_CLK
DV5-DATA1_ERR AK5 DV5_DATA_1 AF27 MP-GOUT-0 D28 LVDS_DP C24 TXPNXD+
C DV5-DATA2_0 AH5
AG5
DV5_DATA_2
DV2_VALID
AE30
MP-GOUT-1 D29
D30
GIN0
GIN1
E24
C
DV5-DATA3_1 DV5_DATA_3 DV2_DATA0 MP-GOUT-2 GIN2 LVDS_EN TXPNXE-
DV5-DATA4_2 AK4 DV5_DATA_4 AF28 MP-GOUT-3 E27 LVDS_EP F24 TXPNXE+
DV2_DATA1 GIN3
DV5-DATA5_3 AJ4 DV5_DATA_5 AD27 MP-GOUT-4 E28
DV2_DATA2 GIN4
DV5-DATA6_4 AH4 DV5_DATA_6 AD26 MP-GOUT-5 E30
DV2_DATA3 GIN5
DV5-DATA7_5 AK3 DV5_DATA_7 AD30 MP-GOUT-6 F26 LVDS_CLKN C23 TXPNXCLK-
DV2_DATA4 GIN6
DV5-DATA8_6 AJ3 DV5_DATA_8 AE26 MP-GOUT-7 F27 LVDS_CLKP D23 TXPNXCLK+
DV2_DATA5 GIN7
DV5-DATA9_7 AK2 DV5_DATA_9 AE27 MP-GOUT-8 F28 AJ10
DV2_DATA6 GIN8
AE28 MP-GOUT-9 F29 RGB_CLK_IN J30 MP-CLKOUT
DV2_DATA7 GIN9
DV-VREF AJ9 DV_VREF AE29 RGB_UD J27 MP-OUT-FFIELD
DV2_DATA8
DV-FREF AK9 DV_FREF AG27 MP-BOUT-0 F30 RGB_HSYNC J29 MP-OUT-HS
DV2_DATA9 BIN0
DV-HREF AH9 DV_HREF MP-BOUT-1 G26 RGB_VSYNC J28 MP-OUT-VS
BIN1
AK28 33R 3LR0 DV3F-CLK MP-BOUT-2 G27 RGB_DE K26 MP-OUT-DE
DV3_CLK BIN2
AK30 33R 3LS1-2 DV3F-VALID MP-BOUT-3 G28
D DV3_VALID
AJ30 33R 3LR9-4 DV3F-DATA0_SOP
MP-BOUT-4 G29
G30
BIN3
BIN4 D
DV3_DATA0 MP-BOUT-5 BIN5
AH29 33R 3LR9-3 DV3F-DATA1_ERR MP-BOUT-6 H27
DV3_DATA1 BIN6
AG29 33R 3LS0-3 DV3F-DATA2_0 MP-BOUT-7 H28
DV3_DATA2 BIN7
AG30 33R 3LR9-1 DV3F-DATA3_1 MP-BOUT-8 H30
DV3_DATA3 BIN8
AH30 33R 3LS1-1 DV3F-DATA4_2 MP-BOUT-9 J26
DV3_DATA4 BIN9
AG28 33R 3LS0-2 DV3F-DATA5_3
DV3_DATA5
AH27 33R 3LR9-2 DV3F-DATA6_4
DV3_DATA6
AJ28 33R 3LS1-3 DV3F-DATA7_5
DV3_DATA7
AK29 33R 3LS1-4 DV3F-DATA8_6
DV3_DATA8
AH28 33R 3LS0-4 DV3F-DATA9_7
DV3_DATA9

E E

G_16290_031.eps
3104 313 6095.3 010206

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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 48

SSB: PNX2015: Tunnelbus


1 2 3 4 5 6
2L01 E5

B4C PNX 2015: TUNNELBUS B4C


2L06 F2
2L07 F3
2L08 F3
2L64 E2
3L10 B4
A A 3L11-1 C4
3L11-2 C5
7J00-1
PNX 2015 3L11-3 C4
Φ 3L11-4 B5
TUNNELBUS 3L12-1 B4
A1 TUNS_TX_BUSY R28 TUN-VIPER-RX-BUSY 3L12-2 B5
TUNN_TX_BUSY
D2 TUNS_TX_CLKN M30
TUNN_TX_CLKN 3L12-3 B4
C2 TUNS_TX_CLKP M29 3L10 33R TUN-VIPER-RX-CLKP
TUNN_TX_CLKP
3L12-4 B5
C4 TUNS_TX_D0 K28 3L12-2 33R TUN-VIPER-RX-DATA0 3L13-1 B5
TUNN_TX_D0
B4 TUNS_TX_D1 K27 3L12-1 33R TUN-VIPER-RX-DATA1
TUNN_TX_D1 3L13-2 B4
A4 TUNS_TX_D2 L30 3L13-4 33R TUN-VIPER-RX-DATA2
TUNN_TX_D2
F3 L28 3L13-3 33R 3L13-3 B4
B B3
TUNN_TX_D3
TUNN_TX_D4
TUNS_TX_D3
TUNS_TX_D4 K29 3L12-4 33R
TUN-VIPER-RX-DATA3
TUN-VIPER-RX-DATA4 B 3L13-4 B5
C3 TUNS_TX_D5 N26 3L13-2 33R TUN-VIPER-RX-DATA5
TUNN_TX_D5 3L14-1 B4
D3 TUNS_TX_D6 L27 3L13-1 33R TUN-VIPER-RX-DATA6
TUNN_TX_D6
E3
TUNN_TX_D7 TUNS_TX_D7 K30 3L12-3 33R TUN-VIPER-RX-DATA7 3L14-2 C5
F2 M27 3L14-4 33R TUN-VIPER-RX-DATA8
TUNN_TX_D8 TUNS_TX_D8 3L14-3 C4
A3 TUNS_TX_D9 N28 3L14-1 33R TUN-VIPER-RX-DATA9
TUNN_TX_D9 3L14-4 B5
F1 TUNS_TX_D10 N27 3L11-4 33R TUN-VIPER-RX-DATA10
TUNN_TX_D10
A2 TUNS_TX_D11 P28 3L11-3 33R TUN-VIPER-RX-DATA11 3L15 D4
TUNN_TX_D11
B1 P27 3L11-2 33R TUN-VIPER-RX-DATA12
TUNN_TX_D12 TUNS_TX_D12
3L14-3 33R
3L20 F3
C1 TUNS_TX_D13 N30 TUN-VIPER-RX-DATA13
TUNN_TX_D13 3L38 F3
D1 TUNS_TX_D14 N29 3L14-2 33R TUN-VIPER-RX-DATA14
TUNN_TX_D14
E1 TUNS_TX_D15 R29 3L11-1 33R TUN-VIPER-RX-DATA15 3L39 F3
TUNN_TX_D15
7J00-1 A3
D9 R27
C C9
TUNN_RX_D0
TUNN_RX_D1
TUNS_RX_D0
TUNS_RX_D1 P30
TUN-VIPER-TX-DATA0
TUN-VIPER-TX-DATA1 C 9LA8 D2
A9 TUNS_RX_D2 T27 TUN-VIPER-TX-DATA2 9LA9 D2
TUNN_RX_D2
D8 TUNS_RX_D3 R30 TUN-VIPER-TX-DATA3
B9
TUNN_RX_D3
T28
IL03 E3
TUNN_RX_D4 TUNS_RX_D4 TUN-VIPER-TX-DATA4
D7 TUNS_RX_D5 T29 TUN-VIPER-TX-DATA5 IL05 F4
TUNN_RX_D5
C8 TUNS_RX_D6 T30 TUN-VIPER-TX-DATA6
TUNN_RX_D6
A8 TUNS_RX_D7 U27 TUN-VIPER-TX-DATA7
TUNN_RX_D7
D6 TUNS_RX_D8 V27 TUN-VIPER-TX-DATA8
TUNN_RX_D8
C6 TUNS_RX_D9 V28 TUN-VIPER-TX-DATA9
TUNN_RX_D9
B6 TUNS_RX_D10 V29 TUN-VIPER-TX-DATA10
TUNN_RX_D10
A6 TUNS_RX_D11 V30 TUN-VIPER-TX-DATA11
TUNN_RX_D11
D5 TUNS_RX_D12 W26 TUN-VIPER-TX-DATA12
TUNN_RX_D12
C5 TUNS_RX_D13 W27 TUN-VIPER-TX-DATA13
TUNN_RX_D13
A5 W28
D E4
TUNN_RX_D14
TUNN_RX_D15
TUNS_RX_D14
TUNS_RX_D15 W29
TUN-VIPER-TX-DATA14
TUN-VIPER-TX-DATA15 D
D4 TUNS_RX_BUSY W30 3L15 33R TUN-VIPER-TX-BUSY
TUNN_RX_BUSY
9LA8 B7 TUNS_RX_CLKN U30 TUN-VIPER-TX-CLKN
TUNN_RX_CLKN
9LA9 C7 TUNS_RX_CLKP U28 TUN-VIPER-TX-CLKP
+2V5 TUNN_RX_CLKP
A7 TUNS_REF M28
TUNN_REF VREF-PNX
2L64

1n0

2L01

1n0

E E

IL03
+2V5
3L38

2L07

100n
1K0
RES
2L06

1u0

3L20 IL05
VREF-PNX
F 47R 1V3
F
3L39

2L08

100n
1K0

G_16290_032.eps
3104 313 6095.3 010206

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Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 49

SSB: PNX2015: DDR Interface


1 2 3 4 5 6 7 8 9 10
2L50 A8
2L51 A8
PNX 2015: DDR Interface
B4D B4D 2L52 A8
2L53 A9
2L54 A9
2L55 C6
2L56 A7
+2V5-DDRPNX +2V5-DDRPNX 2L57 A7
2L58 A7
7J00-3
A PNX 2015 A 2L59 C5

Φ 2L60 C6

2L56

100n
2L57

100n
2L58

100n

2L50

100n
2L51

100n
2L52

100n
2L53

100n
2L54

100n
2L61
2L61 A9

1n0
PNX-MA-0 3L40 C12 DDR INTERFACE
33R MA_0 2L62 E7
PNX-MA-1 3L41 D12
33R 3L42 D11 MA_1 2L63 E7
PNX-MA-2
3L43 33R C10 MA_2
PNX-MA-3
MA_3
3L40 A2
PNX-MA-4 33R 3L44 D21 D14 3L95 33R PNX-MBA0
33R C21 MA_4 MBA_0
C13
3L41 A1
PNX-MA-5 3L45 3L94 PNX-MBA1
MA_5 MBA_1 7L50 3L42 A2

18

33

15

55

61
PNX-MA-6 33R 3L46 D20 3L90 33R

9
3L47 33R D19 MA_6 C17 1K0 K4D261638F-LC40
PNX-MA-7 MCKE_0 PNX-MCKE 3L43 A1
33R 3L48 C19 MA_7 A16
PNX-MA-8 MCLK_N PNX-MCLK-N VDD VDDQ 14
3L44 B2
PNX-MA-9
PNX-MA-10
3L49 33R
33R 3L91
D18
D13
MA_8
MA_9 A17 3L51
100R
PNX-MCLK-P
PNX-MA-0
PNX-MA-1
29
30
0 Φ 17
19 3L45 B1
B PNX-MA-11 3L92 33R
33R 3L93
C18
D17
MA_10
MA_11
MCLK_P
MCS_0
C14 PNX-MCS-0 PNX-MA-2 31
32
1
2
DDR
SDRAM NC
25 B 3L46 B2
PNX-MA-12 PNX-MA-3 3 42 PNX-MA-12
33R MA_12 3L52 3L47 B1
MDQM_0
B15 PNX-MDQM-0 PNX-MA-4 35
4 128Mx16 43
PNX-MDATA-0 A11 D16 22R 3L99 PNX-MDQM-1 PNX-MA-5 36 50 3L48 B2
MD_0 MDQM_1 5 A
PNX-MDATA-1 B12 22R PNX-MA-6 37 53 3L49 B1
MD_1 6
PNX-MDATA-2 C11 A15 PNX-MDQS-0 PNX-MA-7 38
MD_2 MDQS_0 7 3L50 B9
PNX-MDATA-3 A12 B16 PNX-MDQS-1 PNX-MA-8 39 2 3L50 PNX-MDATA-0
MD_3 MDQS_1 8 0 22R
PNX-MDATA-4 A10 ILN1 PNX-MA-9 40
9 1
4 3L56 PNX-MDATA-1 3L51 B4
B13 MD_4 E21 28 5 3L57 22R
PNX-MDATA-5 Mem_DLL0 PNX-MA-10 10 2 PNX-MDATA-2 3L52 B4
MD_5

5L50
PNX-MDATA-6 B10 E10 VREF-DDRPNX PNX-MA-11 41 7 22R 3L58 PNX-MDATA-3
MD_6 Mem_DLL1 11 3 3L56 C9

2L60
PNX-MDATA-7 A13 8 3L59 22R PNX-MDATA-4

30R
MD_7 AP 4
PNX-MDATA-8 A18 C16 10 22R 3L60 PNX-MDATA-5 3L57 C9

100n
MD_8 MM_VREF 5
PNX-MDATA-9 B21 PNX-MBA0 26 11 3L61 22R PNX-MDATA-6
MD_9 3L98 0 6 22R 3L58 C9
PNX-MDATA-10 B18 A14 PNX-MRAS PNX-MBA1 27 BA 13 3L62 PNX-MDATA-7
C MD_10 MRAS 1 D 7
C 3L59 C9

2L59
A21 D15 3L97 33R 54 3L63 22R

1n0
PNX-MDATA-11 MCAS PNX-MCAS PNX-MDATA-8
MD_11 8 22R
PNX-MDATA-12 A19 C15 33R 3L96 PNX-MWE PNX-MDQM-0 20 56 3L64 PNX-MDATA-9 3L60 C9
MD_12 MWE L 9
PNX-MDATA-13 C20 33R PNX-MDQM-1 47 DM 57 3L65 22R PNX-MDATA-10
MD_13 U 10 22R 3L66
3L61 C9
PNX-MDATA-14 B19 VREF-DDRPNX 59 PNX-MDATA-11
MD_14 11 3L62 C9
PNX-MDATA-15 A20 49 60 3L67 22R PNX-MDATA-12
MD_15 2L55 1n0 VREF 12 22R
62 3L68 PNX-MDATA-13 3L63 C9
FLA9 13
PNX-MCLK-N 46 63 3L69 22R PNX-MDATA-14
CK 14 22R 3L70
3L64 C9
PNX-MCLK-P 45 65 PNX-MDATA-15
CK 15
PNX-MCKE 44 22R 3L65 C9
CKE 3L89
PNX-MCS-0 24 16 PNX-MDQS-0 3L66 C9
CS L 22R
+1V2 PNX-MRAS 23 DQS 51 3L71 PNX-MDQS-1
RAS U 3L67 C9
PNX-MCAS 22 22R
CAS
PNX-MWE 21 3L68 C9
WE
3L69 C9
D VSS VSSQ
D 3L70 D9

34

48

66

12

52

58

64
6
3L71 D9
3L89 D9
3L90 B4
3L91 B2
3L92 B1
IL04 IK01
3L93 B2
5L52 +2V5-DDRPNX 3L21
+2V5 +2V5-DDRPNX VREF-DDRPNX 3L94 B5
220R 560R 3L95 B4
5L51
3L96 C4

560R
3L22
E 220R E 3L97 C4
3L98 C5
2L62

2L63

100p
1n0

3L99 B5
5L50 C6
5L51 E7
5L52 E7
7J00-3 A3
G_16290_033.eps 7L50 B7
3104 313 6095.3 010206 FLA9 C6
IL04 E7
1 2 3 4 5 6 7 8 9 10
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 50

SSB: PNX2015: Standby & Control


1 2 3 4 5 6 7 8 9 10 11 12 13 14
1LA0 D9 3LK5 D6
2LA0 D9 3LK6 D6

B4E PNX 2015: STANDBY & CONTROL B4E 2LA1 D9


2LA2 G3
3LK7 D6
3LK8 D6
2LA4 I3 3LK9 E6
2LB0 C9 3LL0 E6
2LB1 G3 3LL1 E6
2LB3 B3 3LL2 E6
+3V3-STANDBY 7J00-5
2LB4 D3 3LL3 E6
A PNX 2015
Φ A 2Q70 C3 3LL4 E6
3LA0 10K ON-MODE ON-MODE 3LM0 100R P0.0 AK15
STANDBY PROCESSOR 2Q71 F3 3LL5 E6
P0_0
3LR4 10K POD-MODE POD-MODE 3LR3 100R AJ15 AJ25 +3V3-STANDBY +3V3-STANDBY 3L75 B6 3LL6 E6
P0_1 PWM1
3LA2 10K ENABLE-1V2 ENABLE-1V2 3LM2 100R P0.2 AH15 3L76 B2 3LL7 E6
P0_2 3LE1
3LA3 10K 3LM3 100R P0.3 AG15 AG25 ALE
P0_3 ALE 3LB7 3L77 C6 3LL8 G3
3LA4 10K ENABLE-3V3 ENABLE-3V3 3LM4 100R P0.4 AK16 100R ALE
P0_4 3LH7
3LA5 1K0 LAMP-ON LAMP-ON 3LM5 100R P0.5 AJ16 AF25 EA 10K 3L78 C2 3LL9 G3
100R P0_5 EA
3L76 10K P0_6 P0_6 3L75 AH16 3L79 C5 3LM0 A6
100R P0.7
P0_6 3LH2 100R 3LB8
3LA7 10K UART-SWITCH UART-SWITCH 3LM7 AG16 AK26 RESET-STBY EA
P0_7 MC_RESET 3L80 D6 3LM2 A6
RC 100R 10K
3LE2
3LC0 10K RC P50 3LG3 100R AK13
P1_0 SCL_MC
AH26 SCL-UP-VIP SCL-UP-VIP
3L81 D2 3LM3 A6
2LB3 1n0 3LG7 100R 3LE3
P50-HDMI AJ13 100R 3L82 E2 3LM4 B6
P1_1 3LF0
B 3LC2 10K P50-HDMI SUPPLY-FAULT 3LG5 100R AH13
P1_2 SDA_MC
AG26 SDA-UP-VIP 4K7 B 3L83 E2 3LM5 B6

3LB5
3LC3 10K 3LG6 100R

10K
SUPPLY-FAULT AG13 100R
P1_3 3LE4
3LC4 10K P50 POWER-OK-DISPLAY +3V3-STANDBY 3LD2 10K AK14
P1_4 SPI_CLK
AH10 SPI-CLK SDA-UP-VIP 3L84 E4 3LM7 B6
3LC5 100K POWER-OK-DISPLAY SCL-UP-SW 3LG8 100R AH14
P1_5 4K7 3L85 E5 3LN0 B6
3LC6 4K7 SCL-UP-SW SDA-UP-SW 3LH9 100R AG14 AG10 SPI-CSB SPI-SDI
P1_6 SPI_CSB 3LA0 A2 3LN1 C6
3LC7 4K7 SDA-UP-SW 3LH8 100R AF14
P1_7
ILC3 DETECT-1V2 ILC4 AJ10 SPI-SDI 3LA2 A2 3LN2 C6
SPI_SDI
3LA9 10K 3LN0 100R P2.0 AF16
3LN1 P2_0 3LA3 A2 3LN3 C6
3LC9 100R P2.1 AK17 AK10 SPI-SDO
P2_1 SPI_SDO 3LA4 B2 3LN4 C6
DETECT-3V3 DETECT-3V3 3LN2 100R P2.2 AH17
+3V3 P2_2 FLA0 5LA2
DETECT-5V ILC5 3LN3 100R P2.3 AG17 AK12 3LA5 B2 3LN5 C6
10K P2_3 XTAL_MC_VDD
DETECT-8V6 ILC6 3LN4 100R P2.4 AK18
P2_4 600R +1V2-STANDBY 3LA7 B2 3LN6 C6

2LB0
ILC7

100n
DETECT-12V 3LN5 100R P2.5 AJ18 AJ12
P2_5 XTALI_MC
3LD0 10K RESET-MIPS CTRL4-STBY 3LN6 100R P2.6 AH18 3LA8 E5 3LN7 C6
P2_6
C 3LD1 10K RESET-PNX2015
9P24 RES PROT-AUDIOSUPPLY
3LG2
100K
3LN7 100R P2.7 AG18
P2_7 XTALO_MC
AH12
C 3LA9 B2
3LB1 E5
3LQ6 C9
3LR2 C2
9P14 RES SDM RXD-UP 3LJ0 100R AK19 AG12
P3_0 XTAL_MC_VSS
2Q70 TXD-UP 3LJ1 100R AJ19 3LB2 E5 3LR3 A6
100p P3_2 P3_1 3LQ6 3LB9
3L78 10K P3_2 3L77 100R AH19 AH25 PSEN PSEN 3LB3 E6 3LR4 A2
P3_2 PSEN
3L79 10K 3LJ5 100R AG19 100R 10K
FLB7 RES P3_3 3LB4 E10 3LS2 D2
ILB9 SDM RESET-MIPS 3V2 3LJ6 100R AK20 AK25
P3_4 PWM0
3LR2 10K RESET-PNX2015 3V2 3LJ7 100R AH20 3LB5 B11 3LT5 G12
P3_5 2LA0 +3V3-STANDBY
SDM 3LJ8 100R AG20 3LB6 D9 3LT7 G13
3LD3 10K P3_6
LED2 LED2 3LJ9 100R AK21
P3_7 22p 3LB7 A10 3LT9 H13

3LB6

RES
1M0
3LD4 10K LED1 LED1
FLA5

1LA0

8
16M
3LD5 10K RESET-SYSTEM RESET-SYSTEM 3V2 3LK0 100R AJ21
P4_0 7LA7 3LB8 B10 3LU0 H12

100R
3LF2
RES
3LD6 10K RESET-AUDIO RESET-AUDIO 3LK1 100R AH21 M25P05-AVMN6
P4_1 2LA1 3LB9 C10 3LU1 I13
3LD7 10K DEBUG-BREAK DEBUG-BREAK 3LK2 100R AG21 VCC
Φ
P4_2 FLA1 3LC0 B2 3LU2 H12
D 3LD8 10K EJTAG-DETECT EJTAG-DETECT 3LK3 100R AF21 SPI-SDO 5 2
D

DSX840GA
P4_3 22p D Q
3L81 10K P4_4 P4_4 3L80 100R AK22
P4_4 FLA2 512K 3LC1 E2 3LU7 G10
3LE7 10K 3LK5 100R AJ22 SPI-CLK 6
AH22
P4_5 C FLASH 3LC2 B2 3LU8 G9
FLC2 P4_6 FLA3
3LE8 10K RESET-MAIN-NVM RESET-MAIN-NVM 3LK6 100R AG22 SPI-CSB 1 3LC3 B2 3LV7 G10
P4_7 S
3LE9 10K STBY-WP-NAND-FLASH STBY-WP-NAND-FLASH 3LK7 100R 3LC4 B2 3LV8 G9
FLA4
3LS2 680R KEYBOARD KEYBOARD 3LK8 100R AK23 BACKLIGHT-CONTROL SPI-WP 3
2LB4 100n ILB3 P5_0 W 3LC5 B2 5LA1 G3
LIGHT-SENSOR 3LK9 100R AH23
3LC1 P5_1 3LC6 B2 5LA2 C9
10K TEMP-SENSOR TEMP-SENSOR 3LL0 100R AG23 7
3LC8 3LL1 P5_2 HOLD
10K FRONT-DETECT FRONT-DETECT 100R AF23 ILB8 3LC7 B2 5LA3 H3
P5_3
3L82 10K 3LL2 100R AK24 VSS
P5_4 3LC8 E2 7J00-5 A8

3LF9
RES
3LL3 100R

10K
3L83 10K AJ24
P5_5
3LC9 C3 7J00-6 G4

3LB4
3LE5 10K 3LL4 100R

10K
AH24

4
P5_6
3LE6 10K 3LL7 100R AG24 3LD0 C2 7LA7 D10
P5_7
E 3LH5 10K SPI-PROG SPI-PROG
FJ40
3LL5 100R AK27
P6_4
E 3LD1 C2 7LB2-1 H13
3LH6 10K SPI-WP SPI-WP 3LL6 100R AJ27 3LD2 B6 7LB2-2 I12
P6_5
RES +3V3-STANDBY 3LD3 D2 7LB5 G12
RES

RES

RES
RES
10K RES

10K RES

9P25 +3V3-STANDBY
3LD4 D2 9J23 G10
RES
3LA8

3LB1

3LB2

3LB3
3LD5 D2 9LA0 H3
3L84

3L85

9P15
10K

10K

10K

SPI-PROG 10K
2Q71 3LD6 D2 9LA1 H3
3LD7 D2 9LA2 H3
100p
3LD8 D2 9LA3 H3
3LE1 A9 9P14 C3
3LE2 B9 9P15 E3
F F 3LE3 B10
3LE4 B10
9P24 C3
9P25 E3
3LE5 E2 ALB0 G3
+1V2 3LE6 E2 FJ40 E5
+3V3-STANDBY +1V2-STANDBY 3LE7 D2 FLA0 C9
3LE8 D2 FLA1 D10
3LU8 3V5
+5V DETECT-5V 3LE9 D2 FLA2 D10
600R
5LA1

ALB0 1K0 3LF0 B9 FLA3 D10

3LU7

2K2
M27-PNX
3LF2 D8 FLA4 D10

100K
3LT5

3LT7
10K
ILB6 7J00-6 3LF8 G6 FLA5 D11
3V3
330R
2LA2

3LL8

PNX 2015
10p

DETECT-1V2
3LF9 E8 FLA6 G6
G Φ 3LV8 3V2 ILD1 G 3LG2 C5 FLA7 G6
2LB1

100n

+12VSW DETECT-12V 7LB5


ILB5 CONTROL BC847BW
27K 3LG3 B6 FLB7 C3

3LV7

10K
Y29
3LG5 B6 FLC2 D3
XTAL_SYS_VDD FLA6
180R

3LG6 B6 ILB2 I6
3LL9

9J23
AF9 3LF8 100R SCL-DMA
SCL_COL +3V3
Y28 XTALI_SYS FLA7 +1V2 3LG7 B6 ILB3 D6
AG9 3LG9 100R SDA-DMA
SDA_COL 3LG8 B6 ILB5 G3
Y27 XTALO_SYS
JTAG-TCK DETECT-8V6 3LG9 G5 ILB6 G4
JTAG-TD-VIPER-PNX2015 3LJ3 Y26 XTAL_SYS_VSS C27 3LH0 100R SCL-DMA 3LH0 H5 ILB7 H3
+3V3 SCL_HD
7LB2-1
3LH1 H5 ILB8 E10
9LA2

AH11 JTAG_TCK B27 3LH1 100R SDA-DMA 6 BC847BS


10K SDA_HD
9LA0 AK11 JTAG_TDI ILD2 3LH2 B9 ILB9 C3
3LT9
H JTAG-TD-PNX2015-HDMI
JTAG-TMS
9LA1 AJ11
AG11
JTAG_TDO
JTAG_TMS
HD_EXINT1
HD_EXINT2
F4
F5 3LJ2 10K +3V3
IRQ-HIRATE
3LU0 ILD3
2
47K
+5V H 3LH3 H5 ILC3 B3
JTAG-TRST AF11 1 3LH4 I5 ILC4 B5
JTAG_TRSTN
RESET-MIPS 9LA3 C22 IRQ-HD1 10K 3LH5 E2 ILC5 C5
INT_HD1

3LU2

10K
RESET-PNX2015 AA27 D22 IRQ-HD2
RESET_IN INT_HD2 3LH6 E2 ILC6 C5
5LA3 ILB7
AD6 SDAC_VDDD G4 3LH3 100R SCL-DMA ILD4 3LH7 B9 ILC7 C5
+1V2 SCL_AVIP
AE6 SDAC_VSSD POWER-OK-DISPLAY 3 3LH8 B6 ILD1 G13
600R
G5 3LH4 100R SDA-DMA ILD5 3LU1
SDA_AVIP 7LB2-2 3LH9 B6 ILD2 H13
2LA4

100n

D10 NC_1 5 +1V2-STANDBY


Y1 A22 IRQ-AVIP BC847BS 3LJ0 C6 ILD3 H12
NC_3 INT_AVIP1 10K
Y30 NC_4 B22 ILB2 4 3LJ1 C6 ILD4 H12
INT_AVIP2
AJ1 NC_5
AJ2
3LJ2 H6 ILD5 I13
NC_6
3LJ3 H3
I +1V2 I 3LJ5 C6
3LJ6 C6
3LJ7 C6
3LJ8 D6
3LJ9 D6
3LK0 D6
G_16290_034.eps 3LK1 D6
3104 313 6095.3 010206 3LK2 D6
3LK3 D6
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 51

SSB: PNX2015: Supply


1 2 3 4 5 6 7 8
2L80 E1
PNX 2015: SUPPLY
B4F B4F 2L81 E1
2L82 E1
2L83 E1
2L84 E1
A 7J00-9 7J00-8 A 2L85 E1
PNX 2015 PNX 2015
+3V3
2L86 E2
Φ +1V2
Φ 2L87 E2
GND SUPPLY

47u 4V
2L88 E2

2LN2

2LN3

2LN4

2LN5

2LN6

2LN7

2LN8
+3V3

100n

100n

100n

100n

100n

100n
B2 R16
VSS_1 VSS_36
B5
VSS_2 VSS_37
R17 E9
C1V2_VDD_1 2L89 E2
B8 R18 E11 2L90 E2
VSS_3 VSS_38 C1V2_VDD_2
B11 E12 F25
VSS_4 C1V2_VDD_3 P3V3VDD_1 2L91 E3
B14 T13 E16 G25
VSS_5 VSS_40 C1V2_VDD_4 P3V3VDD_2
B17
VSS_6 VSS_41
T14 E17
C1V2_VDD_5 P3V3VDD_3
H26 2L92 E3
B20 T15 F9 M6
VSS_7 VSS_42 C1V2_VDD_6 P3V3VDD_4 +1V2 2LN2 A7
B29 T16 F10 N6
VSS_8 VSS_43 C1V2_VDD_7 P3V3VDD_5 2LN3 A7
C25 T17 F12 V6
VSS_9 VSS_44 C1V2_VDD_8 P3V3VDD_6

100u 4V
2LP0

2LP2

2LP3

2LP4
100n
100n

100n
D24 T18 F16 W6 2LN4 A7
B D26
VSS_10
VSS_11
VSS_45
VSS_46
J6 F17
C1V2_VDD_9
C1V2_VDD_10
P3V3VDD_7
P3V3VDD_8
AF8 B 2LN5 A8
E2 U6 AA6 AA26
VSS_12 VSS_47 C1V2_VDD_11 P3V3VDD_9
E23 U13 J25 2LN6 A8
VSS_13 VSS_48 C1V2_VDD_12
E26 U14 K25 AB26 2LN7 A8
VSS_14 VSS_49 C1V2_VDD_13 P3V3VDD_11
E29 U15 AB6 AC26
H29
VSS_15 VSS_50
U16 P6
C1V2_VDD_14 P3V3VDD_12
AD25
2LN8 A8
VSS_16 VSS_51 C1V2_VDD_15 P3V3VDD_13 +2V5
L29 U17 R6 AE7 2LP0 B7
VSS_17 VSS_52 C1V2_VDD_16 P3V3VDD_14
N13 U18 AB25 AE13 2LP2 B8
VSS_18 VSS_53 C1V2_VDD_17 P3V3VDD_15

100u 4V

2LR0
2LP7

2LP9
2LP8

100n
100n

100n
N14 U29 F22 AE14
VSS_19 VSS_54 C1V2_VDD_18 P3V3VDD_16 2LP3 B8
N15 V13 F21 AE24
VSS_20 VSS_55 C1V2_VDD_19 P3V3VDD_17
N16
VSS_21 VSS_56
V14 AA5
C1V2_VDD_20 P3V3VDD_18
AE25 +1V2-STANDBY 2LP4 B8
N17 V15 AE10 AF26 2LP7 C8
VSS_22 VSS_57 C1V2_VDD_21 P3V3VDD_19
N18 V16 AE12
VSS_23 VSS_58 C1V2_VDD_22 2LP8 C8
P13 V17 AF10 AE15
C P14
VSS_24
VSS_25
VSS_59
VSS_60
V18 AF12
C1V2_VDD_23
C1V2_VDD_24
SB1V2VDD_1
SB1V2VDD_2
AE16
+3V3
5LN0 ILN3
PLL-3V3
C 2LP9 C8
P15 AC29 AF13 AE17 2LR0 C8
VSS_26 VSS_61 C1V2_VDD_25 SB1V2VDD_3 600R
P16 AF29 E20 AE18
VSS_27 VSS_62 C1V2_VDD_26 SB1V2VDD_4 2LR2 C8

2LR2

100n
P17 AJ5 E22 AF15 +3V3-STANDBY
VSS_28 VSS_63 C1V2_VDD_27 SB1V2VDD_5
P18
VSS_29 VSS_64
AJ8 AA25
C1V2_VDD_28 SB1V2VDD_6
AF17 2LR4 D8
U26 AJ14 AF18 2LR5 D8
VSS_30 VSS_65 +2V5-DDRPNX SB1V2VDD_7
U25 AJ17 AE19
VSS_31 VSS_66 +2V5 SB3V3VDD_1 2LR6 D8
P29 AJ20 AE21 5LN1 ILN4
VSS_32 VSS_67 SB3V3VDD_2
R13
VSS_33 VSS_68
AJ23
SB3V3VDD_3
AE22
+1V2 PLL-1V2 2LR8 E8
R14 AJ26 E5 AF19
VSS_34 VSS_69 P2V5VDD_1 SB3V3VDD_4 600R 2LR9 E8
R15 AJ29 E6 AF20
VSS_35 VSS_70 P2V5VDD_2 SB3V3VDD_5 2LS5 E6

2LR4

100n
E7
P2V5VDD_3
E8 A23 5LN0 C7
P2V5VDD_4 VDD_LVDS_1
E13 A24
D E14
P2V5VDD_5
P2V5VDD_6
VDD_LVDS_2
VDD_LVDS_3
A26
LVDS-3V3
D 5LN1 D7
5LN2 D7
E15 B23 5LN2 ILN5
P2V5VDD_7 VDD_LVDS +3V3-STANDBY
E18 UP-3V3 5LN3 E7
P2V5VDD_8
E19 AE9
F6
P2V5VDD_9 VDDA_SYS_PLL
T25
PLL-1V2 600R 5LN4 E6
P2V5VDD_10 VCCA_LVDS_PLL LVDS-3V3

2LR5

2LR6
7J00-8 A5

100n

100n
F7 V25
P2V5VDD_11 VDDA_1_7_MCAB +3V3
F13 P26 7J00-9 A2
P2V5VDD_12 VCCA_U5PLL PLL-3V3
F14
P2V5VDD_13 ILN2 E6
F15 AF24
P2V5VDD_14 ADC_VSSA
F18
P2V5VDD_15 ADC3V3VDDA
AF22 UP-3V3 5LN3 ILN6 ILN3 C8
F19 LVDS-3V3 ILN4 D8
P2V5VDD_16 +3V3
2L87
2L80

2L81

2L82

2L83

2L84

100n
2L85

100n
2L86

100n

100n
2L88

100p

2L89

2L91
2L90

2L92

L26 V26
2u2

2u2

2u2

2u2

1n0

1n0

1n0

1n0

P2V5VDD_17 AVDD_MCAB +1V2 600R ILN5 D8


M25 W25
P2V5VDD_18 AVSS_MCAB

2LR8

2LR9
100n

100n
M26 ILN6 E8
E N25
P2V5VDD_19
P2V5VDD_20 SDAC_3V3
AK1
ILN2 5LN4
E
R26
P2V5VDD_21 600R
P25
P2V5VDD_22

2LS5

100n
T26
P2V5VDD_23
R25 P2V5VDD_24

F F

G_16290_035.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 52

SSB: PNX2015: Display Interface


1 2 3 4 5 6 7 8 9 10 11 12 13
1D50 C13 FJ12 F5
1G50 F12 FJ13 B5

B4G VIPER/PNX 2015: DISPLAY INTERFACE B4G


1P06 F13
2G35 D8
2J21 B12
FJ22 F5
FJ23 G11
FJ24 G11
2J22 B12 FJ25 G11
2J23 C12 FJ26 G11
+5V +3V3 2J24 C12 FJ27 H11

A A 2J25 D12
2J26 D12
FJ28 H11
FJ29 H11

3J40 RES

3J41 RES
2J27 E12 FJ30 H11
2J30 I11 FJ31 H11

4K7

10K
2J31 I11 FJ32 H11
IJ30
ANALOG OUTPUT 2J37 H4 FJ36 H11
2J38 H4 FJ37 H11
7J10 RES
BC847BW 2J40 F9 IJ14 C2
5J20 FJ01 2J41 F9 IJ15 D2
AV-ROUT
IJ31 120R 2J42 F9 IJ16 D3

100p
2J21
IJ32 2J43 G9 IJ18 G2
B 5J10 9J40 LAMP-ON
B
7J04
220R * +12VSW +12VSW LAMP-ON-OUT 5J21 FJ02
2J44 G9
2J45 G9
IJ20 G2
IJ23 H2
5J11 FJ13 AV-GOUT 2J46 H9 IJ30 A9
* VDISP
+12VSW
120R 2J47 H9 IJ31 B9

100p
2J22
220R

3J15

47K
2J48 H9 IJ32 B10
SI4835BDY
5J12

220R
* 2J71

100n
* 5J22 FJ03
2J49 I9 IJ68 D4
2J57 D4 IJ69 D4

3J17
6

10K
IJ76 AV-BOUT
IJ80 6J06 RES 1D50 2J61 D5 IJ70 D3
* 3J86 2J77 120R

100p
2J23
9J30 7J05-1 2
+5V BC847BPN 1 2J64 H5 IJ71 H2
4
1K0 SML-310 IJ75 3J16 IJ74 100p 2
1 2J69 H5 IJ72 D7
C +12VSW 9J31
* IJ14 7J08 RES RES BC847BPN
7J05-2 5
10K
7J06
IJ73
3J18 IJ82 BACKLIGHT-CONTROL
3J60 FJ04
3
4
5
C 2J71 B5
2J72 I9
IJ73 C9
IJ74 C9
3 BC847BW MP-OUT-HS
* 4K7 6
2J73 I9 IJ75 C8

3J19

RES
2K2
100R 7

100p
2J24
8 2J76 D2 IJ76 C7
3J92

47K
* SI3441BDV
9 2J77 C9 IJ80 C4
FJ05
B9B-PH-K 3J15 B7 IJ81 H3
6J01

BZX384-C5V6
* 2J61

1n0
* IJ72 9J21
RES
3J20

1K0
MP-OUT-VS
100R
3J61
3J16 C8
3J17 C8
IJ82 C9

100p
2J25
*
7J07

2G35

100n
3J22

3J21
RES
3J18 C9

1K0

15K
BC847BW
3J99

47R
* IJ15 2J76

1u0
* IJ70
3J25

47K
* IJ16 IJ68 IJ69
3J19 C9

D
3J28
* 3J94
* +3V3 D 3J20 D9

BACKLIGHT-CNTRL-OUT
3J62 FJ06
10K 10K BACKLIGHT CONTROL GLINK-TXD
100R
3J21 D8
3J22 D7

100n

100p
2J57

2J26
VDISP-SWITCH * 3J23 G2
3J25 D3
3J28 D4
3J30 H11
3J63 FJ07
GLINK-RXD 3J31 I11
100R 3J40 A9

100p
2J27
3J41 A9
3J42 F4
E E 3J43 F4
3J44 F5
+3V3 3J51 H2
3J52 H4
3J55 H2
3J56 I3
3J60 C12
LVDS
* * * * 3J61 D12
3J42

3J43

3J44

3J88
47R

47R

47R

47R

2J40
CONNECTOR 3J62 D12
3J63 E12
F FHP SDI
TXPNXA-
1
5J50 4 10p F 3J86 C4
3J88 F5
FJ12
CTRL-DISP1 IRQ RESET 3J91 G2
1G50 1P06
TXPNXA+ 3 2J41 3J92 C2
FJ22 PDWIN 2 DLW21S VDISP 1 1 3J94 D4
CTRL-DISP2 10p 2J42 2 2
3J99 D2
3 3
TXPNXB- 5J52 4 5J10 B4
FJ10 CPU-GO 10p 4 4
CTRL-DISP3 1 5 5 5J11 B4
6 6
FJ09 PDP-GO CTRL-DISP1 5J12 B4
7 7
CTRL-DISP4 TXPNXB+ 3 2J43 CTRL-DISP2 8 8 5J20 B12
2 DLW21S CTRL-DISP3 9 9 5J21 B12
G CTRL1-VIPER
IJ18 3J91
* 10p 2J44 CTRL-DISP4 10
11
10
11
G 5J22 C12
TXPNXC- 5J54 4 FJ23
47R 10p 12 12 5J50 F9
1 FJ24
13 13 5J52 G9
14 14
FJ25
15 15
5J54 G9
TXPNXC+ 3 FJ26 5J56 H9
CTRL4-VIPER
IJ20 3J23
* +3V3-STANDBY
2 DLW21S
2J45 16
17
16
17 5J58 H9
47R
* * * * 10p 2J46
FJ27
18 18
100p

100p

100p

100p
2J37

2J38

2J69

2J64

FJ28 19 19 5J60 I9
TXPNXCLK- 5J56 4 10p 20 20 6J01 D2
1 FJ29

* FJ30
21
22
21
22
6J06 C5
3J52

7J04 B3
4K7

23 23
H TXPNXCLK+
2 DLW21S
3 2J47
FJ31
FJ32
24 24 H 7J05-1 C7
CTRL4-STBY
IJ23 3J51

47R
* 10p 2J48
FJ36
25
26
27
25
26
27
7J05-2 C7
7J06 C9
IJ71 IJ81 TXPNXD- 5J58 4 FJ37
10p 28 28 7J07 D4
ON-MODE
3J55
* DISPLAY CONTROL 1 29 29
100K
7J09
SCL-I2C4
SDA-I2C4 ** 3J30
3J31
100R
100R
33
30
31
32
30
31
7J08 C3
7J09 I3
BC847BW TXPNXD+ 3 32
2J49 7J10 B10
100K
3J56

2 DLW21S 0-1453230-3

* * 10p 2J72
FI-WE31P-HFE-E1500 9J21 D7

* * 9J30 C1

100p

100p
5J60

2J31

2J30
TXPNXE- 4 10p 9J31 C1
1
I I 9J40 B9
FJ01 B13
TXPNXE+ 3 2J73
2 DLW21S
FJ02 B13
10p
FJ03 C13
FJ04 C13
FJ05 D13
FJ06 D13
G_16290_036.eps
3104 313 6095.3 010206
FJ07 E13
FJ09 G5
FJ10 G5
1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 53

SSB: Viper: Control


0H00 B10 1H00 B2 2H06 G10 3H04 B13 3H11 D1 3H24 G7 3H54 F4 3H70 E8 3H75 B2 3H80-4 C8 3H84 E8 3H90 B1 3H99 B4 3Q12 B4 3Q17 I7 3Q22 G13 3Q48 B4 6H01 F1 9H02 F3 9H07 D1 AH10 A8 FQ02 H15 FQ21 C1 FQ50 D4 IQ03 H10 IQ22 G6 IQ28 G7
0H02 B11 1H20 B10 2H07 G10 3H05 B13 3H16 C3 3H25 G7 3H55 E4 3H71 D1 3H79 A8 3H81-1 D8 3H85 E1 3H94 I7 3Q03 B2 3Q13 B4 3Q18 I8 3Q23 H10 3Q52 D4 6H03 G1 9H03 C4 9H08 D1 AH11 B2 FQ03 E4 FQ22 C1 FQ52 F4 IQ04 H10 IQ23 G7 IQ30 F1
0H05 C10 1M00 A11 2H08 A1 3H06 A10 3H17 C3 3H31 F1 3H56 E4 3H72 E7 3H80-1 D8 3H81-2 C8 3H86 E8 3H95 I7 3Q04 B2 3Q14 B4 3Q19 F13 3Q24 F10 5H02 H11 6H07-1 G13 9H04 C1 9H13 D1 FH12 H7 FQ04 H14 FQ23 C1 FQ53 F4 IQ15 F10 IQ24 G7
0H09 C10 1M60 H15 2H09 B1 3H08 C3 3H22 C13 3H40 E1 3H57 D4 3H73 B8 3H80-2 C8 3H81-3 D8 3H88 F8 3H97 G1 3Q10 B4 3Q15 B4 3Q20 H11 3Q27 B1 5H03 G13 6H07-2 G12 9H05 F4 9H15 F3 FQ00 H15 FQ10 G1 FQ40 B2 IH09 D1 IQ16 F10 IQ25 H7
0H10 C10 1MM3 C11 2Q69 G14 3H10 D1 3H23 C13 3H41 F1 3H69 D3 3H74 B8 3H80-3 D8 3H82 B2 3H89 F10 3H98 C4 3Q11 B4 3Q16 H10 3Q21 H11 3Q29 F13 6H00 I7 7V00-5 A5 9H06 E3 9H16 C4 FQ01 H14 FQ19 C1 FQ41 B2 IH16 G6 IQ17 G13 IQ27 F7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B5A VIPER: CONTROL B5A


1M00
EMC HOLE
A A
7V00-5
VIPER REV C

2H08 3H79 AH10 3H06


C4 D28 PLL-OUT PLL-OUT
XTALI PLL_OUT
27p
CONTROL 22R
22R
DSX840GA 3H75 3H74
A2 D29 M135-CLK PCI-CLK-VPR
XTALO M135_CLK +3V3 +3V3
1H00

3H82
27M

1M0
100R C30 3H73 68R M27-PNX
3Q48 M27_CLK
RESET-SYSTEM AD4 22R
RESET_IN
100R
2H09 AK12
SDA-MM A25 I2C1_SDA PCI_AD0 NAND-CLE
100R 3Q11

3H05

3H04
AJ12

1K8

1K8
27p AH11 SCL-MM C25 I2C1_SCL PCI_AD1 NAND-ALE
100R 3Q10 AH12
B +3V3 SDA-DMA
SCL-DMA 100R
AF29
3Q13 AD26 I2C2_SDA
PCI_AD2
PCI_AD3
AG12
AJ11 SCL-DMA
B
100R 3Q12 I2C2_SCL PCI_AD4 AG11
3Q03 FQ40 PCI_AD5 AK10 0H00 1H20 0H02
+3V3 SCL-I2C4 SDA-UP-VIP AE27 I2C3_SDA PCI_AD6 SDA-DMA
SCL-UP-VIP 100R 3Q15 AG29 AJ10
4K7 100R 3Q14 I2C3_SCL PCI_AD7 +3V3 +3V3
3Q27

3H90

AG10
4K7

4K7

3Q04 FQ41 PCI_AD8 AK9


SDA-I2C4 SDA-I2C4 A3 I2C4_SDA PCI_AD9
SCL-I2C4 100R 3H99 B4 AJ9
4K7 100R 3H98 I2C4_SCL PCI_AD10 AH9
PCI_AD11

3H22

3H23
RES JTAG-TD-VIPER-PNX2015 9H03 AG9

4K7

4K7
JTAG-TD-VIPER-PNX2015 D2 JTAG_TDO PCI_AD12
9H04 JTAG-TD-CON-VIPER 9H16 AK8 +3V3 0H05
JTAG-TD-CON-VIPER C1
JTAG_TDI PCI_AD13 AG8
JTAG-TCK E4 JTAG_TCK PCI_AD14
JTAG-TMS JTAG-TMS D3 AK7 SCL-MM
JTAG_TMS PCI_AD15 AJ5
JTAG-TRST C2 NAND-D(8)
C FQ19 JTAG-TRST
EJTAG-TDO D25
JTAG_TRST PCI_AD16
PCI_AD17
AG5
AJ4
NAND-D(9)
NAND-D(10)
SDA-MM C

4K7

4K7

4K7
DBG_TDO PCI_AD18 AH4
JTAG-TD-CON-VIPER 4K7 EJTAG-TDI B27 NAND-D(11)
FQ21 DBG_TDI PCI_AD19 0H09 0H10
JTAG-TMS 4K7 3H08 EJTAG-TCK A28 AK3 NAND-D(12)
FQ22 DBG_TCK PCI_AD20
JTAG-TCK 4K7 3H16 EJTAG-TMS A29 AJ3 NAND-D(13)
FQ23 DBG_TMS PCI_AD21
3H17 AK2 NAND-D(14)

3H80-4

3H80-2

3H81-2
B5 PCI_AD22 AJ1
POWERDOWN-HDMI GPIO0 PCI_AD23 NAND-D(15) 1MM3
E5 AH2 NAND-AD(0) EMC HOLE
D4 GPIO1 PCI_AD24 AG2
GPIO2 PCI_AD25 NAND-AD(1)
3H71 B1 AG3 NAND-AD(2)

4K7
4K7

4K7

4K7
+3V3 3H69 FQ50 E7 GPIO3 PCI_AD26 AG4
4K7 NAND-AD(3)
+3V3 A5 GPIO4 PCI_AD27 AF1
IRQ-MPIF 9H08 NAND-AD(4)
10K GPIO5 PCI_AD28
IRQ-FE-MAIN 9H07 IRQ-MAIN IRQ-MAIN A26 AF2 NAND-AD(5)
GPIO6 PCI_AD29 AF4
IRQ-AVIP 9H13 B25 NAND-AD(6)

3H81-1
3H80-1

3H80-3

3H81-3
D D5
E26
GPIO7
GPIO8
PCI_AD30
PCI_AD31
AF5 NAND-AD(7) D
3H10 4K7 CTRL4-VIPER GPIO9 AH7
+3V3 CTRL4-VIPER D27 GPIO10 PCI_PAR
B29 AF7
3H11 4K7 GPIO11 PCI_PERR
DEBUG-BREAK DEBUG-BREAK 3Q52 B28 AK6
IH09 GPIO12 PCI_STOP
RES SOUND-ENABLE-VPR SOUND-ENABLE-VPR 100R C27 AH6
GPIO13 PCI_TRDY AG6
3H57 E25 GPIO14 PCI_IRDY
+3V3 AF6
10K D26 GPIO15 PCI_FRAME
AJ6
PCI_DEVSEL
F3 AJ2 3H72 100R NAND-D(8)
SC1_SCCK PCI_IDSEL
G4 AD2 PCI-CLK-VPR
SC1_OFFN PCI_CLK
E2 AH1
SC1_RST PCI_CBE3
G5 AK5 NAND-REn
SC1_CMD PCI_CBE2
F4 AJ7 NAND-WEn
E 10K 3H56 H4
SC1_DA PCI_CBE1
PCI_CBE0 AG7
AH10
E
3H85 +3V3 SC2_SCCK PCI_SERR
+3V3 RESET-FE-MAIN RESET-FE-MAIN F1 SC2_OFFN
10K 3H55 G3 AD1 PCI-INTA PCI-INTA 3H70 4K7 +3V3
4K7 +3V3 SC2_RST INTA
IRQ-HD2 9H06 F2 +3V3
3H40 SC2_CMD AE1
IRQ-HD2 E1 PCI-REQ PCI-REQ 3H84 4K7
+3V3 FQ03 SC2_DA PCI_REQ AE2
RESET-TM PCI-REQ-A PCI-REQ-A 3H86 4K7
BAS316

4K7 PCI_REQ_A
6H01

AE4 PCI-REQ-B PCI-REQ-B 3H88 4K7


PCI_REQ_B
AE28
QVCP2L_DATA_OUT0

3Q24
3H89
AD5

10K

10K
HPD-HIRATE AD27 QVCP2L_DATA_OUT1 PCI_GNT
10K 3H54 AF30 AE3
+3V3 QVCP2L_DATA_OUT2 PCI_GNT_A AE5
IQ30 3H31 AE29 QVCP2L_DATA_OUT3 PCI_GNT_B IQ27
IRQ-HIRATE IRQ-HIRATE AD28
+3V3 QVCP2L_DATA_OUT4
4K7 FQ52 AC27 AA3
F 3H41
IRQ-HD1
IRQ-HD1 9H05
FQ53
AE30
AD29
QVCP2L_DATA_OUT5
QVCP2L_DATA_OUT6
XIO_D8
XIO_D9 AA4
AB1
F
+3V3 QVCP2L_DATA_OUT7 XIO_D10
4K7 AD30 QVCP2L_DATA_OUT8 XIO_D11 AB2
HDMI-COAST 9H15 AB27 AB3 USB-BUS-PW IQ15
QVCP2L_DATA_OUT9 XIO_D12
CHDEC-CLK 9H02 AB28 AB4
QVCP2L_CLK_OUT XIO_D13 IQ16 56K 3Q19
XIO_D14 AC1 USB-OVERCUR +5V
AC4
XIO_D15 3Q29 0R4 +T

3Q22

100K
0V SOUND-ENABLE W3 NAND-RBY POLYSWITCH
XIO_ACK
XIO_A25 W4 IQ28
FQ10 AA2 IH16 3H24 100R NAND-SEL
6H03 XIO_SEL0
A-PLOP XIO_SEL1 AA1 5H03
BAS316 0V XIO_SEL2 Y4
Y2 IQ22 3H25 100R

470u 16V
XIO_SEL3 IQ17 220R

2Q69
3H97

4K7

W2
G XIO_SEL4
E24
IQ23

GLINK-TXD +5V
G
UA1_TX
UA1_RX B26 GLINK-RXD 2H07
USB-BUS-PW
UA2_TX F26 TXD-VIPER 1n0
E27 RXD-VIPER
UA2_RX USB-OVERCUR 2H06 6H07-2 6H07-1
UA2_RTSN C29 IQ24
UA2_CTSN B30 IQ25 1n0 5H02
IQ04 3Q21 DLW21S
USB1-DP BAV99S BAV99S
4 3 1M60
22R
FQ00 1
USB1_DM AJ28 USB1-DM IQ03 3Q20 FQ01 2
AH27 USB1-DP USB1-DM 1 2 FQ02 USB
H USB1_DP
USB2_DM AF26
AK29
22R FQ04
3
4 CONNECTOR H
USB2_DP
AJ29 USB-BUS-PW B4B-PH-K
USB_BUS_PWR
AG27 USB-OVERCUR
USB_OVRCUR

3Q23

3Q16
FH12
SYS_RSTN_OUT AD3 RESET-MIPS
SML-310
3H94

RES 4K7

3Q17

3Q18

15K

15K
6H00
3H95

330R

15K

15K

I
+3V3
G_16290_037.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 54

SSB: Viper: Main Memory


1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2H00 H9
2H02 H8

VIPER: MAIN MEMORY 2H03 H9

B5B B5B 2H10 G8


2H11 G9
2H12 G9
2Q01 B9
2Q03 B9
2Q21 B14
2Q23 B14
A A 2V00 D7
2V01 D14
2V02 C2
2V16 G11
2V17 G11
SD RAM1 SD RAM2 2V18 G11

2Q01

2Q03

2Q21

2Q23
2V36

2V37

2V38

2V39

2V40

2V41

2V42

2V43

2V44

2V45
100p

100p

100p

100p

100p

100p

100p

100p

100p

100p
7V00-2 2V19 G11

1u0

1u0

1u0

1u0
VIPER REV C +2V5-VPR +2V5-VPR +2V5-VPR +2V5-VPR
2V20 G12
2V21 G12
7V02 * 2V22 G12
B DDR INTERFACE *
7V01 MT46V32M16P-5BTR B 2V23 G12

18

33

15

55

61

61

55

15

33

18
MT46V32M16P-5BTR

1
14 14 2V24 G12
VDD VDDQ VDDQ VDD
MM_A0 B13 D19 MM_DATA_7
MM_A0
MM_A1
29
30
0 Φ 17
25
17
25
Φ 0
29
30
MM_A0
MM_A1
2V25 G13
MM_A1 D15
MM_ADDR0 MM_DATA0
B19 MM_DATA_3 MM_A2 31
1 DDR NC
43 43
NC DDR 1
31 MM_A2 2V26 G13
MM_ADDR1 MM_DATA1 2 SDRAM SDRAM 2
MM_A2 B14 C19 MM_DATA_5 MM_A3 32 53 53 32 MM_A3 2V27 G13
MM_ADDR2 MM_DATA2 3 3
MM_A3 A15 A21 MM_DATA_4 MM_A4 35 8Mx16 19 19 8Mx16 35 MM_A4 2V28 G13
MM_A4 MM_ADDR3 MM_DATA3 MM_DATA_1 4 DNU DNU 4
C15 D20 MM_A5 36 50 50 36 MM_A5
MM_ADDR4 MM_DATA4 5 A A 5 2V29 G14
MM_A5 B15 D21 MM_DATA_6 MM_A6 37 37 MM_A6
MM_ADDR5 MM_DATA5 6 6
MM_A6 A16
MM_ADDR6 MM_DATA6
B21 MM_DATA_2 MM_A7 38
7 0
2 3V00 22R MM_DATA_0 MM_DATA_16 3V01 22R 2
0 7
38 MM_A7 2V30 G14
MM_A7 D16 C21 MM_DATA_0 MM_A8 39 4 3V02 22R MM_DATA_1 MM_DATA_17 3V03 22R 4 39 MM_A8
MM_ADDR7 MM_DATA7 8 1 1 8 2V31 G14
MM_A8 B16 A24 MM_DATA_13 MM_A9 40 5 3V04 22R MM_DATA_2 MM_DATA_18 3V05 22R 5 40 MM_A9
MM_A9 MM_ADDR8 MM_DATA8 MM_DATA_12 9 2 2 9 2V35 G14
C16 B22 MM_A10 28 7 3V06 22R MM_DATA_3 MM_DATA_19 3V07 22R 7 28 MM_A10
MM_ADDR9 MM_DATA9 10 3 3 10
C MM_A10
MM_A11
D14
C18
MM_ADDR10 MM_DATA10
A22
D22
MM_DATA_10
MM_DATA_8
MM_A11
MM_A12
41
42
11 4
8
10 3V10 22R
3V08 22R MM_DATA_4
MM_DATA_5
MM_DATA_20
MM_DATA_21 3V11 22R
3V09 22R 8
10
4 11
41
42
MM_A11
MM_A12
C 2V36 B9
2V37 B10
MM_A12 MM_ADDR11 MM_DATA11 MM_DATA_11 12 5 5 12
B17 C24 11 3V12 22R MM_DATA_6 MM_DATA_22 3V13 22R 11
MM_ADDR12 MM_DATA12 AP 6 6 AP 2V38 B10
C22 MM_DATA_14 MM_BA0 26 13 3V14 22R MM_DATA_7 MM_DATA_23 3V15 22R 13 26 MM_BA0
VREF-VPRDDR MM_DATA13 0 D 7 7 D 0
2V02 C12 B24 MM_DATA_15 MM_BA1 27 BA 54 3V16 22R MM_DATA_8 MM_DATA_24 3V17 22R 54 BA 27 MM_BA1 2V39 B10
MM_AVREF MM_DATA14 MM_DATA_9 1 8 8 1
1n0 D23 56 3V18 22R MM_DATA_9 MM_DATA_25 3V19 22R 56
MM_DATA15 MM_DATA_21 MM_DQM_0 9 MM_DATA_10 MM_DATA_26 9 MM_DQM_2
2V40 B10
MM_BA0 D13 C6 20 57 3V20 22R 3V21 22R 57 20
MM_BA0 MM_DATA16 MM_DATA_17 L 10 10 L 2V41 B11
MM_BA1 A13 B6 MM_DQM_1 47 DM 59 3V22 22R MM_DATA_11 MM_DATA_27 3V23 22R 59 DM 47 MM_DQM_3
MM_BA1 MM_DATA17 MM_DATA_23 2V00 1n0 U 11 11 U
D7 60 3V32 22R MM_DATA_12 MM_DATA_28 3V33 22R 60 2V01 1n0 2V42 B12
MM_DATA18 VREFD-VPRDDR 12 12 VREFD-VPRDDR
MM_CS0 B12 C7 MM_DATA_16 49 62 3V34 22R MM_DATA_13 MM_DATA_29 3V35 22R 62 49
D17 MM_CS0 MM_DATA19
B7 MM_DATA_20 MM_CLK_N
VREF 13
63 3V36 22R MM_DATA_14 MM_DATA_30 3V37 22R 63
13 VREF
MM_CLK_N
2V43 B12
IH20 MM_CS1 MM_DATA20 14 14
C9 MM_DATA_22 3V24 46 65 3V38 22R MM_DATA_15 MM_DATA_31 3V39 22R 65 46 3V25 2V44 B12
MM_DATA21 CK 15 15 CK
MM_DQM_0 A19 D8 MM_DATA_19 MM_CLK_P 220R 45 45 220R MM_CLK_P 2V45 B12
MM_DQM_0 MM_DATA22 MM_DATA_18 CK CK
MM_DQM_1 D24 A7 MM_CKE 44 44 MM_CKE
MM_DQM_1 MM_DATA23 CKE CKE 3H50 G8
D MM_DQM_2
MM_DQM_3
D6
B11 MM_DQM_2 MM_DATA24
A8
B9
MM_DATA_24
MM_DATA_26
MM_CS0
MM_RAS
24
23
CS
DQS
L
16
51
3V42
3V40
22R
22R
MM_DQS0
MM_DQS1
MM_DQS2
MM_DQS3
3V43
3V41
22R
22R
16
51
L
DQS
CS
24
23
MM_CS0
MM_RAS
D 3H51 H8
MM_DQM_3 MM_DATA25 MM_DATA_27 RAS U U RAS
D10 MM_CAS 22 22 MM_CAS 3H52 F8
MM_DATA26 MM_DATA_28 CAS CAS
MM_DQS0 B20 A9 MM_WE 21 21 MM_WE
MM_DQS1 A23
MM_DQS_0 MM_DATA27
D9 MM_DATA_30 WE WE 3H53 G8
MM_DQS_1 MM_DATA28 VSS VSSQ VSSQ VSS
MM_DQS2 A6 C10 MM_DATA_29 3V00 C10
MM_DQS_2 MM_DATA29 MM_DATA_31

34

48

66

12

52

58

64

64

58

52

12

66

48

34
MM_DQS3 B10 A10 3V01 C12
MM_DQS_3 MM_DATA30 MM_DATA_25
D11
MM_DATA31 3V02 C9
MM_RAS C13
MM_CAS A12 MM_RAS 3V03 C11
MM_WE D12 MM_CAS
MM_WE 3V04 C10
MM_CKE D18 3V05 C12
MM_CKE
MM_CLK_N A18
MM_CLK_N
3V06 C9
E MM_CLK_P B18
MM_CLK_P E 3V07 C11
RES 3V08 C10
3V44
3V09 C12
3V78

1K0

100R 3V10 C9
3V11 C11
3V12 C10
3V13 C12
3V14 C9
3V15 C11
+2V5-VPR 3V16 C10
F 3V17 C12

3H52

560R
3V18 C9
3V19 C11
IQ13 3V20 C10
1V3 VREFD-VPRDDR
3V21 C12
3V22 D9

3H53

560R
2H10

2H11

2H12
100n

100p

1u0
3V23 D11
3V24 D7
3V25 D14
3V32 D10
+2V5-VPR
+2V5-VPR 3V33 D12
G G 3V34 D9

3H50

560R
3V35 D11
3V36 D10

47u 4V
2V16

2V17

2V18

2V19

2V20

2V21

2V22

2V23

2V24

2V25

2V26

2V27

2V28

2V29

2V30

2V31

2V35
100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n

100n
IQ14 3V37 D12
1V3 VREF-VPRDDR
3V38 D9
3V39 D11

3H51

560R
2H02

2H00

2H03
100n

100p

1u0
3V40 D9
3V41 D11
3V42 D9
3V43 D11
H H 3V44 E3
3V78 E3
7V00-2 B4
7V01 B7
7V02 B12
IH20 D3
IQ13 F9
IQ14 G9

G_16290_038.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 55

SSB: Viper: A/V + Tunnelbus


1 2 3 4 5 6 7 8 9 10 11 12 13
2H01 I6

VIPER: A/V + TUNNELBUS 3H02 C9

B5C 7V00-1
VIPER REV C
B5C 3H07 E8
3H18 C3
3H19 C9
3H20 D9
3H21 C9
DV1F-DATA0 AG13 DV1_DATA0
AUDIO/VIDEO QVCP5L_DATA_OUT0 J28 68R 3Q28-4 DV-BOUT-0 3H28 A3
DV1F-DATA1 AH13 J27 68R 3Q28-3 DV-BOUT-1
DV1_DATA1 QVCP5L_DATA_OUT1 3H32 B3
DV1F-DATA2 AJ13 H30 68R 3Q28-2 DV-BOUT-2
A DV1F-DATA3
DV1F-DATA4
AK13
AG14
DV1_DATA2
DV1_DATA3
QVCP5L_DATA_OUT2
QVCP5L_DATA_OUT3 H27
G30
68R 3Q28-1
68R 3Q34-4
DV-BOUT-3
DV-BOUT-4
A 3Q02-1 C9
3Q02-2 C9
DV1_DATA4 QVCP5L_DATA_OUT4 68R 3Q34-3
+3V3 DV1F-DATA5 AJ14 G29 DV-BOUT-5 3Q02-3 C9
DV1_DATA5 QVCP5L_DATA_OUT5 68R 3Q34-2
DV1F-DATA6 AG15 G28 DV-BOUT-6
DV1_DATA6 QVCP5L_DATA_OUT6 68R 3Q34-1 3Q02-4 C8
DV1F-DATA7 AH15 G27 DV-BOUT-7
DV1_DATA7 QVCP5L_DATA_OUT7 68R 3Q26-4
DV1F-DATA8_ERR AJ15 DV1_DATA8 QVCP5L_DATA_OUT8 F30 DV-BOUT-8 3Q05-1 C9
DV1F-DATA9_SOP AK15 F29 68R 3Q26-3 DV-BOUT-9
3H28 DV1_DATA9 QVCP5L_DATA_OUT9 68R 3Q25-2
3Q05-2 C8
DV1F-VALID DV1F-VALID AG16 M28 DV-GOUT-0
DV1_VALID QVCP5L_DATA_OUT10 68R 3Q25-1 3Q05-3 C9
DV1F-CLK AH16 M27 DV-GOUT-1
4K7 DV1_CLK QVCP5L_DATA_OUT11 68R 3Q44-4
QVCP5L_DATA_OUT12 L29 DV-GOUT-2 3Q05-4 B9
AJ16 L27 68R 3Q44-3 DV-GOUT-3
DV2_DATA0 QVCP5L_DATA_OUT13 68R 3Q44-2
3Q07-1 B8
AK16 DV2_DATA1 QVCP5L_DATA_OUT14 K30 DV-GOUT-4
AJ17 K29 68R 3Q44-1 DV-GOUT-5 3Q07-2 B9
DV2_DATA2 QVCP5L_DATA_OUT15 68R 3Q08-4
AG17 K28 DV-GOUT-6 3Q07-3 B9
B AK18
AJ18
DV2_DATA3
DV2_DATA4
QVCP5L_DATA_OUT16
QVCP5L_DATA_OUT17
K27
J30
68R 3Q08-3
68R 3Q08-2
DV-GOUT-7 B 3Q07-4 B8
DV2_DATA5 QVCP5L_DATA_OUT18 DV-GOUT-8
AH18 J29 68R 3Q08-1 DV-GOUT-9 3Q08-1 B9
DV2_DATA6 QVCP5L_DATA_OUT19 68R 3Q07-4
3H32 AG19 DV2_DATA7 QVCP5L_DATA_OUT20 R28 DV-ROUT-0 3Q08-2 B9
DV2A-VALID DV2A-VALID AK19 R27 68R 3Q07-3 DV-ROUT-1
DV2_VALID QVCP5L_DATA_OUT21 68R 3Q07-2 3Q08-3 B8
DV2A-CLK AH19 DV2_CLK QVCP5L_DATA_OUT22 P29 DV-ROUT-2
4K7 68R 3Q07-1 3Q08-4 B9
AJ19 DV2_ERR QVCP5L_DATA_OUT23 P27 DV-ROUT-3
AG18 N30 68R 3Q05-4 DV-ROUT-4 3Q09 E8
DV2_SOP QVCP5L_DATA_OUT24 68R 3Q05-3
N29 DV-ROUT-5
DV3F-DATA2_0
QVCP5L_DATA_OUT25 68R 3Q05-2 3Q25-1 B8
AK24 DV3_DATA0 QVCP5L_DATA_OUT26 N28 DV-ROUT-6
DV3F-DATA3_1 AJ24 QVCP5L_DATA_OUT27 N27 68R 3Q05-1 DV-ROUT-7 3Q25-2 A9
DV3F-DATA4_2 DV3_DATA1 68R 3Q25-4
AK25 DV3_DATA2 QVCP5L_DATA_OUT28 M30 DV-ROUT-8 3Q25-3 C8
DV3F-DATA5_3 AG23 M29 68R 3Q25-3 DV-ROUT-9
DV3_DATA3 QVCP5L_DATA_OUT29 3Q25-4 C9
DV3F-DATA6_4 AH24 E30 68R 3H02 DV-CLKIN
C DV3F-DATA7_5
DV3F-DATA8_6
AJ25
AK26
DV3_DATA4
DV3_DATA5
QVCP5L_CLK_OUT
QVCP5L_VSYNC F28
F27 68R 3Q02-4
68R 3Q02-3 DV-OUT-VS C 3Q26-3 A9
DV3_DATA6 QVCP5L_HSYNC DV-OUT-HS 3Q26-4 A8
3H18 DV3F-DATA9_7 AG24 G26 68R 3Q02-1 DV-OUT-FFIELD
DV3_DATA7 QVCP5L_AUX1 3Q28-1 A9
DV3F-VALID DV3F-VALID AJ26 E29 68R 3Q02-2 DV-OUT-DE
DV3_VALID QVCP5L_AUX2
DV3F-CLK AG25 3Q28-2 A8
4K7 DV3F-DATA1_ERR DV3_CLK
AF24 AH30 IH08 3H19 1K0
DV3F-DATA0_SOP DV3_ERR DAC_IRSET IH07
3Q28-3 A9
AH25 AF27 3H21 39R
DV3_SOP DAC_RDUMPY 3Q28-4 A9
AH29 IH06 3H20 39R
DAC_RDUMPC
IH10 AG26 DV_FREF DAC_CVBS AG28 3Q34-1 A9
IH11 AK28 AJ30
DV_VREF DAC_CHROMA 3Q34-2 A9
IH15 AJ27 DV_HREF 3Q34-3 A8
TS_DATA0 AJ22
AA30 I2S_IN1_SD TS_DATA1 AG21 3Q34-4 A9
IH01 AA29 AK22
D IH03
AA28
AB30
I2S_IN1_WS
I2S_IN1_SCK
TS_DATA2
TS_DATA3 AH21
AJ21
D 3Q35-1 H6
3Q35-2 H5
I2S_IN1_OSCLK TS_DATA4
TS_DATA5 AK21 3Q35-3 H6
I2S-MAIN-ND W28 AG20
I2S_IN2_SD TS_DATA6 3Q35-4 H6
W27 I2S_IN2_WS TS_DATA7 AJ20
Y29 AK23 3Q36-1 H5
I2S_IN2_SCK TS_VALID
IH00 Y27 AH22 3Q36-2 H6
I2S_IN2_OSCLK TS_SOP 3Q09
AG22 CHDEC-CLK
TS_CLK 3Q36-3 H6
SPDIF-HDMI AA27 33R
SPDIF_IN2
AC30 U27 I2S-SUB-D 3Q36-4 H5
SPDIF_IN1 I2S_OUT1_SD0
V30 3H07 22R BACKLIGHT-CONTROL 3Q37-1 H5
I2S_OUT1_SD1
I2S_OUT1_SD2 V29 CTRL1-VIPER
V28
3Q37-2 H6
I2S_OUT1_SD3
V27 3Q37-3 H5
E I2S_OUT1_WS
I2S_OUT1_SCK W30
W29
E 3Q37-4 H6
I2S_OUT1_OSCLK IH04 3Q38-1 I5
I2S_OUT2_SD0 T28 I2S-MCH-LR 3Q38-2 I6
I2S_OUT2_SD1 T27 I2S-MCH-CSW 3Q38-3 H6
I2S_OUT2_SD2 R30 I2S-MCH-SLR
R29 I2S-MAIN-D 3Q38-4 H6
I2S_OUT2_SD3
I2S_OUT2_WS T29 I2S-WS-MAIN 3Q39 I6
I2S_OUT2_SCK T30 I2S-BCLK-MAIN 3Q40 I6
I2S_OUT2_OSCLK U29 IH05 3Q41 I9
SPDIF_OUT AB29 SPDIF-OUT1 3Q44-1 B9
3Q44-2 B8
F F 3Q44-3 B9
3Q44-4 B9
7V00-1 A6
7V00-4 G7
IH00 D4
IH01 D4
IH03 D4
IH04 E8
IH05 F8
IH06 D9
IH07 C9
G G IH08 C9
7V00-4 IH10 D4
VIPER REV C
IH11 D4
IH15 D4
TUNNELBUS
TUN-VIPER-TX-DATA0 3Q36-4 33R N2 G2 TUN-VIPER-RX-DATA0
N1 TUN_TX_DATA0 TUN_RX_DATA0 G1 TUN-VIPER-RX-DATA1
TUN-VIPER-TX-DATA1 3Q36-3 33R
P4 TUN_TX_DATA1 TUN_RX_DATA1 J4 TUN-VIPER-RX-DATA2
TUN-VIPER-TX-DATA2 3Q36-2 33R
P2 TUN_TX_DATA2 TUN_RX_DATA2 J3 TUN-VIPER-RX-DATA3
TUN-VIPER-TX-DATA3 3Q36-1 33R
R1 TUN_TX_DATA3 TUN_RX_DATA3 H1 TUN-VIPER-RX-DATA4
TUN-VIPER-TX-DATA4 3Q35-4 33R
R2 TUN_TX_DATA4 TUN_RX_DATA4 K4 TUN-VIPER-RX-DATA5
TUN-VIPER-TX-DATA5 3Q35-3 33R
R3 TUN_TX_DATA5 TUN_RX_DATA5 J2 TUN-VIPER-RX-DATA6
TUN-VIPER-TX-DATA6 3Q35-2 33R
H TUN-VIPER-TX-DATA7
TUN-VIPER-TX-DATA8
3Q35-1 33R
3Q37-4 33R
R4
T3
TUN_TX_DATA6
TUN_TX_DATA7
TUN_RX_DATA6
TUN_RX_DATA7
J1
K1
TUN-VIPER-RX-DATA7
TUN-VIPER-RX-DATA8
H
T4 TUN_TX_DATA8 TUN_RX_DATA8 L4 TUN-VIPER-RX-DATA9
TUN-VIPER-TX-DATA9 3Q37-3 33R
U2 TUN_TX_DATA9 TUN_RX_DATA9 L2 TUN-VIPER-RX-DATA10
TUN-VIPER-TX-DATA10 3Q37-2 33R
U4 TUN_TX_DATA10 TUN_RX_DATA10 M4 TUN-VIPER-RX-DATA11
TUN-VIPER-TX-DATA11 3Q38-4 33R
V1 TUN_TX_DATA11 TUN_RX_DATA11 M3 TUN-VIPER-RX-DATA12
TUN-VIPER-TX-DATA12 3Q37-1 33R
V2 TUN_TX_DATA12 TUN_RX_DATA12 M2 TUN-VIPER-RX-DATA13
TUN-VIPER-TX-DATA13 3Q38-3 33R
V3 TUN_TX_DATA13 TUN_RX_DATA13 M1 TUN-VIPER-RX-DATA14
TUN-VIPER-TX-DATA14 3Q38-2 33R
V4 TUN_TX_DATA14 TUN_RX_DATA14 N4 TUN-VIPER-RX-DATA15
TUN-VIPER-TX-DATA15 3Q38-1 33R
TUN_TX_DATA15 TUN_RX_DATA15
TUN-VIPER-TX-CLKP 3Q39 33R T1 K3 TUN-VIPER-RX-CLKP
T2 TUN_TX_CLOCKP TUN_RX_CLOCKP
TUN-VIPER-TX-CLKN 3Q40 33R
W1 TUN_TX_CLOCKN N3 3Q41 TUN-VIPER-RX-BUSY
TUN-VIPER-TX-BUSY
TUN_TX_BUSY TUN_RX_BUSY

I VREF-PNX
K2
TUN_AVREF
33R
I
2H01

1n0

G_16290_039.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13
F
E
D
C
B
A

G
2Q04 D11
2Q02 D11
2Q00 D10

7V00-3

1
1

V18
VSSC_36
B5D

VIPER REV C
2Q07 D12
2Q06 D12
2Q05 D12

V17
VSSC_35
V16 M12
VSSC_34 VDDC_1

+1V2
V15 M13
VSSC_33 VDDC_2
V14 M14
VSSC_32 VDDC_3
V13 M15
VSSC_31 VDDC_4

3104 313 6095.3


U18 M16
VSSC_30 VDDC_5
U17 M17
VSSC_29 VDDC_6
U16 M18
2Q10 D13
2Q09 D13
2Q08 D12

VSSC_28 VDDC_7
U15 M19
VSSC_27 VDDC_8
U14 N12
VSSC_26 VDDC_9
U13 N19
VSSC_25 VDDC_10
T18 P12
VSSC_24 VDDC_11
T17 P19
VSSC_23 VDDC_12

2
2

T16 R12
VSSC_22 VDDC_13
SSB: Viper: Supply

T15 VDDC_14 R19


VSSC_21
2Q13 D14
2Q12 D13
2Q11 D13

T14 T12
VSSC_20 VDDC_15
T13 T19
VSSC_19 VDDC_16
R18 U12
VSSC_18 VDDC_17
R17 U19
VSSC_17 VDDC_18
R16 V12
VSSC_16 VDDC_19
R15 VSSC_15 V19
VDDC_20
R14 W12
VSSC_14 VDDC_21
R13 VSSC_13 W13
VDDC_22
2Q16 D14
2Q15 D14
2Q14 D14

P18 W14
VSSC_12 VDDC_23
P17 W15
VSSC_11 VDDC_24
P16 W16
VSSC_10 VDDC_25
P15 VDDC_26
W17
VSSC_9

3
3

P14 W18
VSSC_8 VDDC_27
P13 W19
VIPER: SUPPLY

VSSC_7 VDDC_28
N18
VSSC_6
N17
2Q19 D15
2Q18 D15
2Q17 D15

VSSC_5
N16
VSSC_4 J26
N15
VSSC_3 VDD_1 L26
+3V3

N14
VSSC_2 VDD_2 N26
N13
VSSC_1 VDD_3 R26
VDD_4 U26
M26 VSS_68 VDD_5 W26
AK30
VSS_67 VDD_6
2Q24 E11
2Q22 E11
2Q20 E10

AK17 AA5
VSS_66 VDD_7 AA26
AK11 VDD_8
VSS_65 AC5
AK4
VSS_64 VDD_9

4
4

AJ23 AC26
VSS_63 VDD_10 AF9
AH26
VSS_62 VDD_11 AF11
AH20
VSS_61 VDD_12 AF13
AH14
VSS_60 VDD_13 AF15
AH8
2Q28 E12
2Q27 E12
2Q26 E12

VSS_59 VDD_14 AF17


AH3
VSS_58 VDD_15 AF19
AG1
VSS_57 VDD_16 AF21
AF28
VSS_56 VDD_17 AF23
AF22
VSS_55 VDD_18 D1
AF20
VSS_54 VDD_19 Y3
AF18
VSS_53 VDD_20 AC2
AF16
VSS_52 VDD_21
Circuit Diagrams and PWB Layouts

2Q33 E13
2Q32 E13
2Q30 E12

AF14 AF3
VSS_51 VDD_22 AH5
AF12 VDD_23
VSS_50

5
5

AF10 AH11
VSS_49 VDD_24 AH17
AF8
VSS_48 VDD_25 AH23
AC29
SUPPLY

VSS_47 VDD_26 AJ8


AC3
VSS_46 VDD_27 AK1
AB26
VSS_45 VDD_28 AK14
AB5
2Q37 E14
2Q35 E14
2Q34 E13

VSS_44 VDD_29 AK20


Y28
VSS_43 VDD_30 AK27
Y26
VSS_42 VDD_31 H29
Y5
VSS_41 VDD_32 L28
Y1
VSS_40 VDD1_33 P30
V26
VSS_39 VDD1_34 U28
V5
VSS_38 VDD1_35 Y30
U30
VSS_37 VDD1_36 AC28
2Q39 E14
2Q38 E14

2Q40 D10

U3
VSS_36 VDD1_37

6
6

T26 AG30
VSS_35 VDD1_38 AH28
EP1.1U AA

T5
VSS_34 VDD1_39 E28
P28
VSS_33 VDD1_40 A4
P26
VSS_32 VDD2_41 A30
P5
VSS_31 VDD2_42 C3
P1 VSS_30 VDD2_43 C26
M5
VSS_29 VDD2_44
2Q44 D11
2Q43 D11
2Q42 D11

L30 E23
VSS_28 VDD2_45
L3 VSS_27
K26 E9
VSS_26 VDD_2V5_1 E11
K5 VDD_2V5_2
VSS_25 E13
+2V5-VPR

H28
7.

VSS_24 VDD_2V5_3 E15


H26 VDD_2V5_4
VSS_23 E17
H5 VDD_2V5_5
VSS_22
7

7
H2 E19
2Q47 D12
2Q46 D12
2Q45 D12

VSS_21 VDD_2V5_6 E21


E22 VSS_20 VDD_2V5_7
E20 J5
VSS_19 VDD_2V5_8 L5
E18 VSS_18 VDD_2V5_9 N5
E16 VSS_17 VDD_2V5_10 R5
E14 VSS_16 VDD_2V5_11 U5
E12 VSS_15 VDD_2V5_12 W5
E10 VSS_14 VDD_2V5_13
2Q50 D13
2Q49 D13
2Q48 D12

H3
EN 56

E8 VSS_13 2Q76
VDD_2V5_14 L1
E3
VSS_12 VDD_2V5_15 P3
D30 1n0
VSS_11 VDD_2V5_16 U1
C28
VSS_10 VDD_2V5_17 A11 2Q63
C23
VSS_9 VDD_2V5_18 A17
C17 5Q01
IQ09

VSS_8 VDD_2V5_19 100n


8

8
C11 B23
VSS_7 VDD_2V5_20 C8
+3V3

C5
2Q53 D14
2Q52 D13
2Q51 D13

VSS_6 VDD_2V5_21 C14 600R


B8
VSS_5 VDD_2V5_22 C20
A27 VDD_2V5_23 2Q64 5Q02
VSS_4
A20
VSS_3
+1V2

A14 VSS_2
F5 100n 600R
VDDA_3V3
A1 VSS_1 E6
VDDA_1V2
IQ10

B3 2Q77
VDDA_1_7_MCAB
B2 VSSA_1_7_MCAB AE26
VDD_DAC
2Q56 D14
2Q55 D14
2Q54 D14

AF25 1n0
VSS_DAC
2Q65 5Q03
+1V2

100n 600R
9

2Q78
IQ07
2Q59 D15
2Q58 D15
2Q57 D15

1n0
2Q67

1n0

2Q66 5Q04
IQ08
2Q62 F11
2Q61 F11
2Q60 F10

+3V3

100n 600R
+2V5

10
10

2Q20 2Q40 2Q00


2Q60
2Q65 C9
2Q64 C8
2Q63 C8

4u7 6.3V 47u 4V 4u7 6.3V


100n
2Q82 2Q81 2Q79

4u7 4u7 4u7


2Q22 2Q42 2Q02
RES
220R
220R
5Q08
5Q07

4u7 6.3V 4u7 6.3V 4u7 6.3V


2Q76 C8
2Q67 C9
2Q66 C10

2Q83 2Q43 2Q80


2Q61
11
11

4u7 4u7 6.3V 4u7


1n0
2Q62 2Q24 2Q44 2Q04
IQ11
+1V2
+3V3
2Q78 C9
2Q77 C9

100p 100n 100n 100n


2Q79 D10

+2V5-VPR

2Q26 2Q45 2Q05

100n 100n 100n


2Q46 2Q06
2Q27
100n 100n
2Q82 E10
2Q81 D10
2Q80 D11

100n
+2V5-VPR

2Q47 2Q07
12
12

2Q28
100n 100n
100n
2Q48 2Q08
2Q30
100n 100n
2Q85 F14
2Q84 F13
2Q83 E11

100n
2Q49 2Q09
2Q32
100n 100n
100n 2Q50 2Q10

2Q91 2Q33 100n 100n


2Q88 F14
2Q87 F14
2Q86 F14

13
13

10n 100n 2Q51 2Q11

2Q84 2Q34 100n 100n


2Q52 2Q12
10n 100n
100n 100n
2Q85 2Q35
2Q91 F13
2Q90 F15
2Q89 F15

2Q53 2Q13
10n 100n
100n 100n
2Q86 2Q37 2Q54 2Q14

10n 100n 100n 100n


5Q03 B9
5Q02 B8
5Q01 B8

14
14

2Q87 2Q38 2Q55 2Q15

1n0 100n 100n 100n

2Q88 2Q39 2Q56 2Q16

1n0 100n 10n 10n


5Q08 F11
5Q07 F11
5Q04 B10

2Q89 2Q57 2Q17

1n0 10n 10n


2Q58 2Q18
2Q90
10n 10n
15
15

1n0
IQ07 C9
IQ08 C10

2Q59 2Q19
7V00-3 C1

10n 10n
B5D
IQ10 B8
IQ09 C8

010206
G_16290_040.eps
IQ11 F11

F
E
D
C
B
A

G
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 57

SSB: Viper: EEPROM


1 2 3 4 5 6 7 8 9
2P35 C3

B5E VIPER: EEPROM B5E


2P80 C7
2P81 C8
3P37 A4
3P57 F3
+3V3-STANDBY
3P80 B8
IP10 3P81 C8
9P42
A RES A 3P82 F7
FP36 3P83 D2

3P37

100K
3P84 D2
3P85 D2
RESET-MAIN-NVM PDTA114EU 3P86 E2
7P18
3P88 E2
2P34
+3V3-STANDBY 7P14 B3
+3V3-STANDBY 7P15-1 D2
100n 7P15-2 D3
7P14

9P16
M24C64 7P15-3 E2

RES
8
Φ 7P15-4 E2
B (8Kx8) 7 +3V3
B 7P16 F1
MAIN NVM WC FP22
EEPROM FP34 3P80 7P17 F2
1 6 SCL-UP-VIP NAND-SEL
0 SCL 7P18 A3
2
1 ADR FP35 10K 7P80 C8
3 5 SDA-UP-VIP
2 SDA
9P16 B4

4
+3V3 3P81 9P17 C4

9P17
NAND-RBY
9P42 A3
2K2
2P80 2P81 FP22 B4
FP23 D1
100n 100n FP32 E2
C 7P80
C FP33 F1
FP34 B4

12

37
TC58DVM92F1TGI0

+5V2-STBY
VCC
Φ VCCQ FP35 B4
FP36 A3
EEPROM
2P35 IP10 A3
NAND-AD(0) 26
0
(32Mx16)
7P15-1 100n NAND-AD(1) 28
1 RE
8 NAND-REn IP11 E7
14

3P83 74HC4066PW NAND-AD(2) 30 9 NAND-SEL IP16 D8


2 CE
RXD 1 1 NAND-AD(3) 32 16 NAND-CLE
3 CLE
3P84 100R 1 2 RXD-UP NAND-AD(4) 40 17 NAND-ALE
FP23 4 ALE
13 NAND-AD(5) 42 18 NAND-WEn
X1 5 WE IP16
100R NAND-AD(6) 44 19 STBY-WP-NAND-FLASH
6 WP
7

NAND-AD(7) 46
D NAND-D(8)
NAND-D(9)
27
29
7
8
I/O
RY
7 NAND-RBY D
9 BY
7P15-2 NAND-D(10) 31
10
14

74HC4066PW NAND-D(11) 33
11
4 1 NAND-D(12) 41 1
12
3P85 1 3 RXD-VIPER NAND-D(13) 43 2
13
UART-SWITCHn 5 NAND-D(14) 45 3
X1 14
100R NAND-D(15) 47 4
15
7

5
3P86 23 10
TXD 24 NC 11
100R 7P15-3 34 14
14

74HC4066PW 35 15
+5V2-STBY NC
8 36 20
E 6
1
1 9 TXD-UP 38
39
21
22
E
X1
VSS
3P88

GND
10K

48
25
13
IP11
FP32
UART-SWITCHn 7P15-4
14

3P82

10K
74HC4066PW
11 1
UART-SWITCH 1 10 TXD-VIPER
12
FP33 X1
7

7P16
F PDTC114EU
10K F
3P57

7P17
PDTC114EU

G_16290_041.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 58

SSB: Miscellaneous
1 2 3 4 5 6 7 8
1M01 E7

B5F MISCELLANEOUS B5F


1M21 D7
2M80 E7
2M81 F6
2M82 E5
2M83 E5
A A 2M84 E5
2M85 D4
2M86 D3
2M87 D1
+5V2-STBY
+5V2-STBY 2M91 B2
7M05 7M06 2M92 B2
LD3985M33 LD3985M122
2M93 B5
+1V2-STANDBY
1 5 1 5 FM50 2M94 B5
IN OUT +3V3-STANDBY IN OUT
3M00 E2
3 4 3 4
INH BP INH BP 3M02 E2

B B 3M50 D4

2M91

2M92

2M93

2M94
COM COM

10n

10n

1u0
1u0
3M51 D5
2

2
3M52 E5
3M53 E5
3M54 E7
3M71 C2
3M72 D1
5M00 E6
6M10 C1
+5V2-STBY +3V3-STANDBY 7M01 E2
7M05 A1
C FM51 FM52
C 7M06 A4
BZX384-C3V9

7M11 D2
6M10

3M71

10K

9M09 D2
FM50 B5
FM53 0V
RESET-STBY FM51 C1
3
7M11 FM52 C2
FM54 IM09
9M09 1 FM53 C2
2M86

100n

FM54 D1
2 FM55 D4
2M87

3M72
100p

680R

PDTC144EU
FM56 D5
D D FM57 E6
FM58 E4
1M21 FM59 E4
FM55 3M50
LIGHT-SENSOR 1 FM60 E4
2M85 100R FM56 3M51 2 IM05 E2
100p
3
+5V2-STBY
100R
IM06 E2
3M52 4

2M84

100p
FM57 5M00 5 IM08 F2
100R +5V2-STBY 6 IM09 D2
220R
3M02

2M83

2M80
100p

100n
B6B-PH-K
10K

RC
FM58
LED2
E IM06
0V2 STANDBY LED1
FM59 3M53 E
100R

2M82

100p
+3V3-STANDBY 7M01
3M00 IM05 0V8 1M01
10K FM60 3M54 1
0V2 ON-MODE KEYBOARD
BC847BW IM08 2
10R 3

2M81

100p
B3B-PH-K

F F

G_16290_042.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 59

SSB: Video DAC


1 2 3 4 5 6 7 8 9 10 11 12 2G60 C5
2G61 C5

B6 VIDEO-DAC B6
2G62 C5
2G63 E6
2G64 E6
2G65 B3
2G67 B7
A A 2G68 B6
2G69 B3
3999 H3
3G70 E7
7G42 3G72 F6
LD3985M33
3G73 D7
+3V3 IG19 5G10 FG01 +3V3DAC +5V +3V3DAC
9G49 1 5 3G74 D7
IN OUT
120R IG21 3G75 E7
3G78 3 4
INH BP 3G76 E7

100u 4V
3G77 F7

2G65

2G69
100u
COM

RES
2R2

2G68

2G67
B B

10n

1u0
3G78 B2

2
3G79 E6
5G10 B3
7G40 C4
+3V3DAC 7G41 F6
7G42 A6
9G30 C3
9G31 C3
2G60
9G32 C3
9G33 C3
100n 9G34 C3
C 2G61 C 9G35 C3
100n 9G36 G5
2G62 IG16
9G37 G5
9G30

9G31

9G32

9G33

9G34

9G35
AV-ROUT
7G40 100n 9G38 D2
9G39 D3

3G73
IG02 ADV7123KSTZ140

RES

75R
RES
13 29 30 DV-CLKIN cG10 MP-CLKOUT 9G40 D3
VAA
DV-ROUT-0 9G38 39 R0 IOR 34 DV-OUT-HS cG11 MP-OUT-HS 9G41 D3
0
DV-ROUT-1
DV-ROUT-2
9G39
RES
IG03 40
41
R1
R2 1 Φ IOR IOR_ 33
DV-OUT-VS
DV-OUT-DE
cG12
cG13
MP-OUT-VS
MP-OUT-DE
9G42 E3
2 VIDEO DAC
DV-ROUT-3 42 R3
IG14 DV-OUT-FFIELD cG14 MP-OUT-FFIELD 9G43 E3
43 R4 3 IOG 32
DV-ROUT-4 4 AV-GOUT 9G47 G6
44 R5
D DV-ROUT-5
DV-ROUT-6 45 R6 5
6
R
IOG
IOG_ 31
DV-ROUT-0
DV-ROUT-1
cG15
cG16
MP-ROUT-0
MP-ROUT-1 D 9G48 F6

3G74
46 R7 9G49 B2

RES

75R
DV-ROUT-7 7
DV-ROUT-8 47 R8 IOB 28 DV-ROUT-2 cG17 MP-ROUT-2
8 FG01 B3
DV-ROUT-9 48 R9 DV-ROUT-3 cG18 MP-ROUT-3
9 IOB FG98 H3
RES IOB_ 27 DV-ROUT-4 cG19 MP-ROUT-4
DV-GOUT-0 9G40 IG04 1 G0 DV-ROUT-5 cG20 MP-ROUT-5 FG99 H2
IG05 2 G1 0
DV-GOUT-1 9G41 IG12 IG00 G6
RES 3 G2 1
DV-GOUT-2 AV-BOUT DV-ROUT-6 cG21 MP-ROUT-6
4 G3 2 IG01 F5
DV-GOUT-3 DV-ROUT-7 cG22 MP-ROUT-7
5 G4 3
DV-GOUT-4 4 IG08 DV-ROUT-8 cG23 MP-ROUT-8 IG02 C3

3G75
6 G5 38 PSAVE_

RES
G cG24

75R
DV-GOUT-5 5 PSAVE DV-ROUT-9 MP-ROUT-9 IG03 D3
DV-GOUT-6 7 G6
8 G7 6 37 RSET IG10 IG04 D3
DV-GOUT-7 DV-GOUT-0 cG25 MP-GOUT-0
9 G8 7 RSET
E DV-GOUT-8
DV-GOUT-9 10 G9 8
9 COMP
35 COMP
IG17 DV-GOUT-1 cG26 MP-GOUT-1
E IG05 D3
IG06 E3

3G79

470R
RES IG18 DV-GOUT-2 cG27 MP-GOUT-2
IG06 14 B0 36 VREF 3G70 +3V3DAC IG07 E3
DV-BOUT-0 9G42 DV-GOUT-3 cG28 MP-GOUT-3
15 B1 0 VREF 24 CLOCK
DV-BOUT-1 9G43 IG07 10K DV-GOUT-4 cG29 MP-GOUT-4 IG08 E6
1 CLOCK

2G63
16 B2 12 SYNC_

2G64
100n

100n
DV-BOUT-2 RES DV-GOUT-5 cG30 MP-GOUT-5
17 B3 2 SYNC 11 IG09 E7
DV-BOUT-3 3 BLANK IG20 IG09
18 B4 0V 3G76 cG31 IG10 E6
DV-BOUT-4 4 BLANK_ 7G41 ON-MODE DV-GOUT-6 MP-GOUT-6
19 B5 B BC847BW cG32
DV-BOUT-5 5 100K DV-GOUT-7 MP-GOUT-7 IG12 D7

3G72
20 B6 cG33

47R
DV-BOUT-6 DV-GOUT-8 MP-GOUT-8
6 IG14 D7

3G77
21 B7

100K
DV-BOUT-7 DV-GOUT-9 cG34 MP-GOUT-9
7
DV-BOUT-8 22 B8 IG16 C7
23 B9 8
DV-BOUT-9 DV-BOUT-0 cG35 MP-BOUT-0 IG17 E6
9 GND
25 26 DV-BOUT-1 cG36 MP-BOUT-1
IG18 E6
F +3V3DAC
DV-BOUT-2 cG37 MP-BOUT-2 F IG19 B2
DV-CLKIN DV-BOUT-3 cG38 MP-BOUT-3 IG20 E6
IG01 DV-BOUT-4 cG39 MP-BOUT-4
9G48 DV-OUT-VS DV-BOUT-5 cG40 MP-BOUT-5
IG21 B6
RES cG10 D10
DV-BOUT-6 cG41 MP-BOUT-6 cG11 D10
9G36

DV-BOUT-7 cG42 MP-BOUT-7


DV-BOUT-8 cG43 MP-BOUT-8
cG12 D10
DV-BOUT-9 cG44 MP-BOUT-9 cG13 D10
cG14 D10
cG15 D10
+3V3DAC 9G47 DV-OUT-DE cG16 D10
G 9G37 IG00 RES
G cG17 D10
cG18 D10
cG19 D10
cG20 D10
cG21 E10
cG22 E10
cG23 E10
cG24 E10
FG99 3999 FG98 cG25 E10
cG26 E10
100R
cG27 E10
H H cG28 E10
cG29 E10
cG30 E10
cG31 E10
cG32 F10
cG33 F10
cG34 F10
cG35 F10
cG36 F10
cG37 F10
I I cG38 F10
cG39 F10
cG40 F10
cG41 F10
G_16290_043.eps cG42 F10
3104 313 6095.3 010206 cG43 G10
cG44 G10

1 2 3 4 5 6 7 8 9 10 11 12
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 60

SSB: HDMI: Supply


1 2 3 4 5 6 7 8 9 10 11 12 13
1B00 C3
1B03 C4

B7A HDMI + SUPPLY B7A 1B04 C4


1B20 I5
1I06 B1
2B00 C4
A A 2B01 C5
2B03 I4
2B04 I6
2B10 B10
2B11 C9
2B12 C11
2B13 C11
2B14 C12
2B15 C12
2B16 C12
2B17 C12
B 1I06 B 2B18 E13
1 ARX2+ 5B17 FB17 2B19 E13
2 +3V3 3V3-APLL 2B20 E13
3 ARX2- 220R
4 ARX1+ 2B21 E13

2B10

100n
5 2B22 E11
6 ARX1-
ARX0+ ARX-DDC-SCL 2B23 E11
7
8 2B24 E12
ARX0- ARX-DDC-SDA
9 2B25 E12
10 ARXC+ 5B00
2B26 D10
11 AIN-5V 5B10 FB16
12 ARXC- 600R +3V3-AV 3V3-AVI 3V3-AVI 2B31 G9
9B00
C 13 FB09 P50-HDMI 220R
C 2B32 G10

1B00

1B03

1B04

2B00

2B01
100n

100n
14 RES

47u 4V
2B33 G11

2B11

2B12

2B13

2B14

2B15

2B16

2B17
100n

100n

100n

100n

100n

100n
FB10 ARX-DDC-SCL
15 3B02 IB02
FB11 ARX-DDC-SDA PARX-DDC-SCL 2B35 F12
16
17 100R 3B03 2B36 F12
FB12 IB11 PARX-DDC-SDA
18 AIN-5V
FB13 ARX-HOTPLUG 100R IB00
2B37 F12
19
21 20 2B38 F13
23 22 FB14 7B02 5B11 FB18 2B39 F13

3B04
M24C02-WDW6

10K
8
+3V3 3V3-PLL
Φ

3B05

3B06
1-1734011-2 2B40 I10

47K

47K
220R
(256x8) FB04 2B41 I10
DDC NVM

2B26

100n
7
WC 2B45 I9
EEPROM
HDMI CONNECTOR 1 HDMI 1 1 6
3B07
2B46 G10
D 2
0
1 ADR
SCL
100R 3B08
D 3B02 C6
3 5
2 SDA 3B03 C7
100R

4
5B12 FB19 3B04 D5
+3V3 3V3-DIG 3V3-DIG 3V3-DIG 3B05 D6
220R
3B06 D6

2B22

2B23

2B24

2B25

2B18

2B19

2B20

2B21
100n

100n

100n

100n

100n

100n

100n

100n
3B07 D5
3B08 D6
3B17 H5
3B18 I6
3B19 I4
E E 3B20 I4
5B00 C5
5B10 C9
5B11 D9
5B12 D9
5B17 B9
FB20
+1V8 5B18 F10
+1V8 +1V8
6B20 I4
6B21 I4

2B35

2B36

2B37

2B38

2B39
100n

100n

100n

100n

100n
7B02 D4
F 7B25
LD3985M18
F 7B20 I5
7B25 F9
5B18 FB21 7B45 H10
+3V3 1 5 1V8-PLL
IN OUT 9B00 C2
220R 9B38 H10
3 4
INH BP

2B32

2B33
100n

100n
FB04 D5
COM
FB09 C2

2B31

2B46
10n

1u0
FB10 C2

2
FB11 C2
FB12 C2
FB13 C2
G G FB14 D2
FB16 C10
FB17 B10
FB18 D10
FB19 D10
FB20 F10
FB21 F11
FB45 H10
IB00 C7
FB45 IB02 C6
9B38
H +3V3
RES H IB11 C5
IB19 H5
IB20 I6
7B45
LD1117DT33
3B17 IB19
ARX-HOTPLUG 3 2 +3V3-AV
+5V IN OUT
22R IB20 3B18
7B20 HPD-HIRATE COM

100u 4V

100u 4V
2B45

2B40

RES 2B41
BC847BW

1u0
PDZ24-B

BAS316

10K
3B19

6B21

6B20
3B20

100K
2B03

1B20
1K0

4n7

1
2B04

10n

RES
I AIN-5V I

G_16290_044.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 61

SSB: HDMI: I/O + Control


1 2 3 4 5 6 7 8 9 10 11 12 13
2B50 D1 IB63 G8
2B51 D1 IB64 G8

B7B HDMI: I/O + CONTROL B7B 2B52 D1


2B55 C3
IB67 C3
IB68 D3
2B56 D2 IB69 E3
2B57 D3 IB70 E3
2B58 D6 IB73 F3
2B59 D2 IB75 F3
A A 2B60 D3 IB81 G6
2B61 E3 IB82 G6
2B62 E2 IB83 C8
2B63 E3 IB84 G8
2B64 D6 IB85 C9
2B65 E2 IB86 G4
2B66 F3
2B67 F3
7B50-3
TDA9975HS/8/C1 2B68 F2

63 Φ 144
2B69 F3
AGND1 GND IGND1
B 7B50-1
69
74
AGND2 IGND2
150 B 2B70 D6
2B71 G2
AGND3
TDA9975HS/8/C1 76 4 2B72 G3
AGND4 OGND1
Φ 82
86
AGND5 OGND2
14
22 2B75 D3
IB57 VIDEO AGND6 OGND3
137
VPP
91
AGND7 OGND4
30 2B76 E3
CONVERTER 97
AGND8 OGND5
38
2B77 F3
133 INTERFACE 208 3B55 RES DV-VREF 100 46
CKEXT VREF AGND9 OGND6 2B78 D5
33R IB85 54
3B54 IB53 OGND7
HDMI-COAST 72 3B53 DV4-VALID 71 189 2B79 D5
BIAS 3V3-DIG AGNDB_Pb OGND8
M135-CLK 12K 124 1K0 99 197
COAST AGNDR_Pr OGND9 2B80 D6
125 84
GAIN IB83 AGNDG_Y 3B50 D1
126 5 HPD-HIRATE 61
CLAMP 0 HGND1

9B50
135 6 87 151 3B51 D1
MCLK 1 AGNDSOG_Y HGND2
C POWERDOWN-HDMI
116
115
OE 2
7
8
3B56-1 33R DV4-DATA0_SOP
DV4-DATA1_ERR 73
HGND3
155
160
C 3B52 D1
PD 3 AGNDBIAS HGND4 3B53 C8
9 3B56-3 33R 33R 3B56-2 DV4-DATA2_0 166
4 HGND5
93 10 DV4-DATA3_1 102 172 3B54 C5
R_Pr 5 AGNDPLL HGND6
78 VPA 15 3B59-1 33R 3B56-4 DV4-DATA4_2 178
65
G_Y REF 6
16 DV4-DATA5_3 12
HGND7 3B55 C8
B_Pb 7 33R CGND1
5B65
17 3B59-3 33R 3B59-2 DV4-DATA6_4 141 59 3B56-1 C8
3B65 IB67 2B55 8 CGND2 HGNDAPLL
10n

10n

10n

PR 96 18 33R DV4-DATA7_5 191 3B56-2 C9


1 9 CGND3
2B50

2B51

2B52

470R 2B58 95 19 3B57-1 33R 3B59-4 DV4-DATA8_6 136 119


1u0 10n 2 R_Pr 10 CGND|TCLK CGND|TST6 3B56-3 C8
2B56

3B66

10n 94 20 33R DV4-DATA9_7 105 120


1K0
1p5

10p

3 11 CGND|TST0 CGND|TST7
81 3B57-2 111 121 3B56-4 C9
2B57

1 33R
CGND|TST2 CGND|TST8
2B64 80 23 112 122 3B57-1 D8
2 G_Y 0 CGND|TST3 CGND|TST9
10n 79 24 113 123
3 1 DV5-DATA0_SOP CGND|TST4 CGND|TST10 3B57-2 D9
68 25 3B57-3 114 134
1 2 CGND|TST5 CGND|TST11
D 3B57-4 DV5-DATA1_ERR
D 3B57-3 D8
3B50

3B51

3B52

5B67 IB68 2B75 2B70 10n 67 26 33R


3B67 2 B_Pb 3 DV5-DATA2_0
PR1 66 27 3B62-1 33R 3B57-4 D9
3 4
28 33R 3B62-2 DV5-DATA3_1
39R

39R

39R

470R 1u0 10n 2B78 5 3B58-1 D8


3B68

90 VPB 31 3B62-3 DV5-DATA4_2


1K0

Y 1 6 33R
2B59

10n 2B80 89 32 3B62-4 DV5-DATA5_3 3B58-2 E8


1p5

10p

2 G_Y 7 33R
Y1 2B79 10n 88 33 3B58-1 33R DV5-DATA6_4
3B58-3 E8
2B60

3 8 DV5-DATA7_5
10n 34 33R
9 DV5-DATA8_6 3B58-4 E8
130 35 3B58-3 3B58-2 33R
1 10 DV5-DATA9_7
H-SYNC-VGA 131
2 H_C_SYNC 11
36 33R 3B59-1 C8
IB69 2B61 132 3B58-4 33R
3B69 5B69 3 3B59-2 C9
Y 127 39
1 0 3B59-3 C8
V-SYNC-VGA 128 40
470R 1u0 10n 2 VSYNC 1
2B62

3B70

129 41 3B59-4 D9
1K0
1p5

10p

3 2

3V3-DIG
42
3 3B60 H4
E E
2B63

IB58 117 43
3V3-DIG HE 4 3B61 H5
44
5
ARX0- 167 VPC 47 3B62-1 D8
- 6
IB70 ARX0+ 168 RXA0 48
3B71 5B71 2B76 + 7 3B62-2 D9
Y1 49
8
470R ARX1- 173 50 3B62-3 D8
1u0 10n - 9

3B83
2B65

3B72

10K
174 RXA1 51
1K0
1p5

10p

ARX1+ + 10 3B62-4 D9
52
2B66

179
11 3B65 C2
ARX2- -
ARX2+ 180 RXA2 2 FB84 3B84 DV4-CLK 3B66 D3
+ VCLK
206 FB83 15R IRQ-HIRATE 3B67 D2
VAI
2B67 165
3B73 5B73 IB73 - 3B68 D3
PB 164 RXB0 203 IB59
+ R_V
470R 1u0
OR G_Y
205 IB60 3B69 E2
F 10n
F
2B68

3B74

171 204 IB61


1K0
1p5

10p

- B_U 3B70 E3
170 RXB1
2B69

+ 3B71 E2
192
0
177
- 1
193 3B72 E3
176 RXB2 CTL 194
+ 2 3B73 F2
195
3B75 5B75 IB75 3 3B74 F3
PB1 2B77 ARXC- 161
-
470R 1u0
10n ARXC+ 162
+
RXAC1
HREF
1 3B85 33R DV-HREF 3B75 F2
2B71

3B76

+3V3 207 RES DV-FREF


1K0
1p5

10p

FREF 3B86 3B76 G3


33R
2B72

159
- IB62 3B80 G6
158 RXBC 198
+ PL IB63
199 3B81 G5
3B80 IB81 DE
153 200 3B87 33R DV-HREF
A HS 3B82 G6
3B81

1K0 IB82 152 RRX 201 3B88 DV-VREF


10K

JTAG-TD-PNX2015-HDMI B VS 33R
G FB80
3B82
CS
202
IB64 G 3B83 E8
9B51

1K0 109 182


RES

JTAG-TD-HDMI-CON TCK WS 3B84 F8


9B52 110
3B89 IB86 9B53 55
TDI
183
IB84
9B54
3B85 G8
JTAG-TD-HDMI-CON TDO 0 SPDIF-HDMI
JTAG-TMS 22R 108 184 3B86 G9
TMS 1
JTAG-TRST 107 AP 185 3B87 G8
TRST 2
JTAG-TCK 186 7B50-2
138
3
TDA9975HS/8/C1 3B88 G8
DIS

SCL-MM 3B60
118
143
A0 ACLK
187
Φ 60 1V8-PLL
3B89 G4
5B65 C3
3B61 SCL VDD VDDH1_18
SDA-MM 100R 142 56 1V8-PLL 103 154
100R SDA 0 VDDA10_18 VDDH3_18 5B67 D3
57 156 +1V8
X 1 VDDH4_18
PARX-DDC-SDA 145
HSDAA 2
58 11
VDDC1_18
5B69 E3
PARX-DDC-SCL 146 +1V8 140 62 3V3-APLL 5B71 E3
HSCLA VDDC2_18 VDDH2_33
H 148
190
VDDC3_18 VDDH5_33
157
163
H 5B73 F3
HSDAB VDDH6_33
149
HSCLB 3V3-DIG 106
VDDI|TST1 VDDH7_33
169 3V3-DIG 5B75 F3
147 175
VDDI_33 VDDH8_33 7B50-1 B7
139 181
NC VDDH9_33 7B50-2 G11
64
VDDA1_33
70
VDDA2_33 VDDO1_33
3 7B50-3 B11
75 13
VDDA3_33 VDDO2_33 9B50 C5
77 21
VDDA4_33 VDDO3_33 9B51 G4
3V3-AVI 83 29
VDDA5_33 VDDO4_33
85 37 3V3-DIG 9B52 G5
VDDA6_33 VDDO5_33
92 45
98
VDDA7_33 VDDO6_33
53
9B53 G5
VDDA8_33 VDDO7_33 9B54 G9
101 188
VDDA9_33 VDDO8_33
I 3V3-PLL 104
VDDA11_33 VDDO9_33
196
I FB80 G4
FB83 F8
FB84 F8
IB53 C6
IB57 B6
IB58 E6
G_16290_045.eps IB59 F8
3104 313 6095.3 010206 IB60 F8
IB61 F8
IB62 G8
1 2 3 4 5 6 7 8 9 10 11 12 13
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 62

SSB: Analog I/O


1 2 3 4 5 6 7 8 9 10 11 12 13 14 1I00 G9 II01 B5
1I01 C9 II02 D5

B7C ANALOG I/O B7C


1I02 E9
1I03-1 C1
1I03-2 E1
II03 G5
II05 G6
II06 E6
1I03-3 G1 II07 E4
1I04-1 B8 II08 F12
1I04-2 E8 II0C B4
1I04-3 G8 II0D D4
A A 1I07 G7 II10 G4
1I08 F7 II11 G4
1I09 G7 II12 C4
1I0A C7 II13 F12
1I0B E7 II14 F13
1I0E F2 II15 G13
1I0F G2 II16 H13
1I0G F10 II17 C5
1I0H D2
1I0I G2
1I0J C2
B +12VSW +12VSW
+12VSW
B 1I0K E2
1I0L C10
1I0M E10
PDZ24-B

PDZ24-B

PDZ24-B
1I0N H10

6I09

6I0T
6I0N

FI0I II0C II01 FI04


1I04-1 1I0P G10
3I0M 3I06 GREEN
Y Y1 1 AV2_C 1I17 D7
100R 100R C FI0J 2I05 G6
YELLOW 2I06 F6

1I0A
3I0L

1I0L
3 2

75R
3I01

75R

3I0N
75R
1I0J

1I01 2I07 F3
YLC21-3020N YKF51-5564
Y / CVBS
2I08 G4
C 1I03-1
1 GREEN
+12VSW +12VSW 2 4 3 1
FI0K C 2I09 F11
2I0E H12
2I0F G12
2 3 YELLOW 2I53 F12

PDZ24-B
PDZ24-B

6I11
6I0J

YLC21-3020N
3I00 G6
FI0F 3I0G II12 II17 3I12 FI12
AV1_CVBS AV7_Y-CVBS 3I01 C6
100R 100R 3I02 E6

V_NOM
3I03 G6
1I0H

3I0F

3I13

1I17
75R

75R
5 3I04 D6

+12VSW
SVHS 3I06 C6
D +12VSW
FI0P
+12VSW D 3I07 G6
3I08 E6
3I09 G6
PDZ24-B

PDZ24-B

PDZ24-B
3I0A F6
6I0P

6I0A

6I0V
FI0H II0D II02 FI05
3I0B E3
3I0K 3I04
PB PB1 AV2_Y-CVBS 3I0C F3
100R 100R 3I0D G3
1I03-2
1I0K

BLUE

1I0M
3I0E G3

1I0B

3I0P
4
3I0J

75R

75R
3I02

75R
1I04-2
BLUE 4 3I0F D3
5 6 RED 3I0G D3
+12VSW 3I0H G3
E YLC21-3020N +12VSW RED6 5 E 3I0I G3
YLC21-3020N 3I0J E3
+12VSW 3I0K D3
PDZ24-B

PDZ24-B
6I0D

6I02
1I02
3I0L C3
FI0C 3I0B II07 II06 3I08
AUDIO-IN1-R AUDIO-IN4-R 3 YELLOW 3I0M C3

PDZ24-B
6I0H
100R 100R FI01 3I0N C11
FI0E 5I02 II08 3I68 II13 2I53 II14 3I0P E11
BLACK
100K

100K
100p

100p
3I0C
1I0E

3I0A
SPDIF-OUT1
2I07

2I06

1I08
2 1
220R
3I0Q G12
120R 100n
YKC21-4374 3I12 D6

120R
1I0G

2I09

3I69
12p
3I13 D6
F +12VSW F 3I60 H12
3I66 G12
+12VSW
+12VSW 3I67 H12
3I68 F12
PDZ24-B
6I0L

PDZ24-B
6I08 3I69 F12

PDZ24-B
1I03-3 1I04-3 5I02 F11
II10 II03

6I10
FI0G FI03 RED 7
7 RED 3I0I
PR PR1
3I03
II15 6I00 G7
FI0N 3I0Q
100R 100R AUDIO-IN2-R 6I02 E7
+12VSW +12VSW
1I0I

WHITE 9 100R
WHITE 6I08 F7
3I0H

8 9 1I09 8
75R

3I00

75R

100K
100p
1I0P
6I09 B7

2I0F

3I66
YLC21-3020N YLC21-3020N 1I00
G 3 RED G 6I0A D7
PDZ24-B

PDZ24-B

6I0D E2
6I0F

6I00

II11 II05 +12VSW 6I0F G2


FI0D 3I0D 3I07 FI00
AUDIO-IN1-L AUDIO-IN4-L 2 1 WHITE
6I0H F10
100R 100R
6I0J C2
1I0F

YKC21-4374

PDZ24-B
100K

100K
100p

100p
3I0E

6I0Y
2I08

2I05

3I09

1I07

6I0L F2
FI0M 3I60 II16 6I0N B2
AUDIO-IN2-L
100R
6I0P D2
6I0T B11

100K
100p
1I0N
AV1 AV3

3I67
2I0E
H AV2 H
6I0V D11
6I0Y G11
6I10 G11
6I11 C7
FI00 G7
FI01 F7
FI03 G7
FI04 C7
FI05 D7
FI0C E2
FI0D G2
FI0E F10
I I FI0F D2
FI0G G2
FI0H D2
FI0I C2
FI0J C9
FI0K C10
FI0M H10
G_16290_046.eps
3104 313 6095.3 010206
FI0N G10
FI0P D9
FI12 D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 63

SSB: UART
1 2 3 Personal Notes:
1I10 B2

B7D UART B7D 1I11 A2


1M16 A3
2I02 A3
2I03 B3
6I01-1 3I10 A2
1 2 3I11 B2
+3V3-STANDBY

BAV99S
6I01-1 A1

A 6 A 6I01-2 B1
FI10 B2
FI11 A2

100p
1I11

2I02
1M16
3I10 FI11
TXD UART
1
3I11 100R FI10 2 SERVICE
RXD 3
100R 5 4
CONNECTOR

100p
1I10

2I03
S3B-PH-SM4-TB

B B
3

BAV99S

+3V3-STANDBY
4 5
6I01-2

C C

D D

E E

G_16290_047.eps
3104 313 6095.3 010206

1 2 3
E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 64

SSB: Audio: Amplifier


1DM1 H8 2D22 H14 2D36 G9 2D45 H3 2D54 F14 2D63 C6 3D13 B2 3D22 C5 3D39-1 G4 3D43 E1 3D56 G2 3D69 H10 3D78 E12 3D88 C10 5D15 G15 7D10-4 B3 7D17 G4 7D23-2 G12 9D03-2 F6 FD27 G10 ID15 F12 ID28 G4 ID37 G11 ID46 H3 ID57 C3 ID70 B8 ID81 F1 cD04 D15
2D11 B2 2D23 E14 2D37 G6 2D46 H10 2D55 F2 2D64 E9 3D14 B2 3D23 D4 3D39-2 E4 3D44 F5 3D57 G9 3D70 H11 3D79 G12 3D89 B4 5D16 G2 7D11-1 B5 7D18-1 E5 7D24 E2 9D03-3 G6 FD49 B3 ID16 F6 ID29 G12 ID38 G10 ID47 H11 ID60 B4 ID71 C10 ID82 F5 cD05 E15
2D14 E7 2D26 F2 2D38 H2 2D47 H2 2D56 F6 2D65 F9 3D15 B4 3D24 C4 3D39-3 G3 3D45 F12 3D58 G11 3D71 H3 3D81 G4 3D90 E9 5D18 F6 7D11-2 C5 7D18-2 G5 7D25-1 C8 9D03-4 G6 FD54 B3 ID17 F13 ID30 C7 ID39 G2 ID48 B5 ID61 C4 ID72 C10 ID83 F5
2D15 E7 2D27 F9 2D39 G13 2D48 H3 2D57 F14 2D66 F9 3D16 B5 3D25 C3 3D39-4 E5 3D46 F6 3D60 F6 3D72 H11 3D82 C7 3D91 E9 5D19 F14 7D12-1 D4 7D19 F11 7D25-2 B9 9D04-1 F13 FD73 C9 ID20 F2 ID31 B8 ID40 G7 ID50 B4 ID62 F1 ID74 F9 ID86 F4
2D17 E15 2D28 H7 2D40 G13 2D49 H10 2D58 G14 2D70 C4 3D17 B2 3D26 D3 3D40-1 G11 3D47 F13 3D61 F13 3D73 H3 3D83 C7 5D10 E7 6D10 B4 7D12-2 C3 7D20 E12 7D26-1 C9 9D04-2 F13 ID10 E7 ID21 F11 ID32 G5 ID41 G15 ID51 B4 ID63 C7 ID75 F11 ID87 F4
2D18 E15 2D30 F3 2D41 H7 2D50 H10 2D59 G6 2D71 G1 3D18 B2 3D34 E3 3D40-2 G11 3D49 E1 3D64 G4 3D74 H10 3D84 B8 5D11 E15 6D11 C4 7D14 F4 7D21-1 F12 7D26-2 B10 9D04-3 F13 ID11 E15 ID22 F12 ID33 G12 ID42 G3 ID52 B2 ID64 F14 ID76 F11 ID91 C10
2D19 F2 2D31 F11 2D42 H7 2D51 C8 2D60 H9 2D72 F10 3D19 C4 3D35 E4 3D40-3 E11 3D50 F1 3D65 G11 3D75 B9 3D85 B8 5D12 F6 7D10-1 B3 7D15 E5 7D21-2 F12 7D30 F6 9D04-4 G13 ID12 E11 ID23 F4 ID34 G3 ID43 G10 ID53 B4 ID65 F6 ID77 F14 ID92 E6
2D20 F7 2D32 F6 2D43 H14 2D52 E6 2D61 H9 3D10 A3 3D20 C5 3D37 E10 3D40-4 E13 3D51 F9 3D67 H3 3D76 G5 3D86 C9 5D13 F14 7D10-2 F3 7D16-1 F5 7D22 G12 7D31 F13 9D48 E2 ID13 E4 ID24 F9 ID35 G5 ID44 H2 ID55 C5 ID66 F9 ID78 F13 ID93 E6
2D21 G14 2D35 G2 2D44 H15 2D53 F7 2D62 H9 3D12 A4 3D21 C2 3D38 E11 3D42 C3 3D54 F1 3D68 H3 3D77 E6 3D87 C10 5D14 G7 7D10-3 F10 7D16-2 F4 7D23-1 E12 9D03-1 F6 FD26 F2 ID14 F5 ID25 F1 ID36 G4 ID45 G13 ID56 C4 ID67 E9 ID80 E1 cD01 D15

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

B8A AUDIO: AMPLIFIER overcurrent


** = protection B8A
DIVERSITY LIST

SOUND-ENABLE
A A

PROT-AUDIOSUPPLY
+12_20V
POS 2x8W (8 ohm) 2x15W (8 ohm )
+3V3-STANDBY 2D15 100uF/16V ------------
2D18 100uF/16V ------------
2D22 ------------ 100uF/25V

3D10
VP 2D23 ------------ 100uF/25V

47K
+12_20V

3D12
2D26 100nF/16V 100nF/25V

5K6
3 7D10-1 2D27 100nF/16V 100nF/25V
3D13 ------------
9 LM339P 2D28 100uF/25V
3D89 100uF/16V
FD49 14 ID60 +3V3-STANDBY 2D42 ------------
3D14 2K7 0V
LEFT-SPEAKER GND-D 8 2D44 100uF/16V ------------
22K ID50
12 2D48 2n2 1n5
220K

3D85
2D50 2n2 1n5

47K
BAS316

6D10
3D15

3D16
2D52 ------------

47K

2K2
100uF/25V
B VN VP
ID70
4
BC847BPN
2D53
2D54
------------
------------
470nF/25V
470nF/25V
B
ID48 7D25-2
ID52 3 6 5 4 2D55 ------------ 1n5
3D17 7D10-4 0V7
RIGHT-SPEAKER 7 LM339P BC847BPN 2D56 2n2 ------------
ID53

3D84

3D75
FD54 1 2 3 7D26-2 5 2D57 2n2 ------------

47K

47K
220K 7D11-1
3D18 6 BC847BS 2D58
ID51 2n2 ------------
12
2D11

1 3 2D59 2n2 ------------


2u2

47K ID31

3D19

3D20
+12_20V +12_20V 3D25 2K2 1K0

47K

22K
-17V4 ID91
3D21

3 6 3D35 1K2 1K0


2K7

VN ID30 INV-MUTE 3D38 1K2 1K0


GND-D 3D82 FD73

BZX384-C18
7D11-2 5 ID55 2 7D25-1 3D49 ------------ 15K
* ID71
3D25

3D86

3D87
100K
BC847BS BC847BPN 3D50 10K 3K9
2K2

47K
GND-D * 6D11
4
47K
1 6
-18V4
3D51 10K 3K9

3D22

2D63

3D83

2D51
3D54 ------------ 47K

10K

47K
10n

1n0
C GND-D
18V4
ID56
ID63 7D26-1
BC847BPN
2 ID72 3D64
3D65
1K2
1K2
1K0
1K0
C
1 3D90 ------------
3D42

3D88
3D91 1K2
47K

33K
3D24

5D12 33uH
10K

------------
7D12-2 5D13 ------------ 33uH
ID57
3 BC847BS
2D70 ** 5D18 BEAD 0805 220 E 100MHz ------------
ID61 5D19 BEAD 0805 220 E 100MHz ------------
1n0
5 6 7D12-1 6D11 BZX384-C18 BZX384-C27
7D18 SI4532 SI4559

-12_20V
3D23
4 2 7D23 SI4532 SI4559
-12_20V
3D26

7D24 ------------ BC817-25W


2K2
U-VOLT-DETECT

U-VOLT-DETECT

U-VOLT-DETECT
2K2

SOUND-ENABLE
1 9D48 JMP ------------
BC847BS
D D
CPROT

MUTE
-12_20V

cD01 cD04
MUTE

FEEDBACK-LR

CPROT

LEFT-SPEAKER

FEEDBACK

MUTE

FEEDBACK-RL

CPROT

RIGHT-SPEAKER
+12_20V
-12_20V
GND-DR
cD05

5D10

220R
ID92
GND-D GND-DL

3D90

2K2
E 9D48
* ID10 ID11 5D11
+12_20V E
2D64 ID67 220R
**
4

5 3D40-4 4
INV-MUTE

100u 25V
3D43 ID80
* *
3D39-4

7D24
3D34

3D77

2D52

3D37
* *
3K3

1K2

22K

22K

3K3

1K2

22K
* *

100u 16V

100u 25V

100u 16V
*
3D35

+12_20V
*

3D38
2p2

2D14

2D15

3D78

2D23

2D17

2D18
100n

100n
22K
7D20
10R
*

3D91
7D18-1

33K
7D15
*
5

3D39-2 3D40-3 ID12


3

ID13 ID93
3D49

2 7 3 6
*
15K

BC807-25W FEEDBACK 7D23-1


BC817-25W 22K
4 7D30
BC857BW
** GND-DL 22K
7D31
BC857BW
**
ID81 ID14 5D18
* BC807-25W ID77 5D19 *
5
6

SI4532ADY GND-DL GND-DL 2D65 GND-DR GND-DR GND-DR


ID20 6 FEEDBACK-LR ID66 6 ID15
220R SI4532ADY 220R
* * VP ID82 3D60 ** 5D12
* 2p2 3D61 ** 5D13
*
3D54

2D55

2 2
47K

7D16-1 7D21-1
1n5

2D66 ID21

2D72
BC847BPN BC847BPN

2p2
ID16 33u FEEDBACK-RL ID17
F 0R1 0R1 33u
F
2D19

3D46

2D20
100n

220n
1 1
6R8

* * 2p2 -17V4 ** * *
2D56

2D53

3D47

2D54

2D57
470n

470n
-17V4 9D04-1

6R8
7D14 7D19
2n2

2n2
BC847BW VP BC847BW 1 8
-12_20V ID23 ID22
ID83 ** **
330R

3D44

9D03-1 9D04-2
ID87 ID78

330R

3D45
1 8 ID76 2 7
ID25 * ID62 2D26 * FD26 GND-D 3 7D10-2
-16V9 7D16-2 **
9D03-2
ID65
ID24 3D51 * ID74 2D27 3 7D10-3
7D21-2
BC847BPN **
9D04-3
ID64

2D39
3D50

*
2D32

11 LM339P 4 2 7 5 LM339P 4 3 6
1n5

ADAC1 13
2D30 ID86
1
3D39-1
8 * **
9D03-3 * GND-DL
ADAC2 2
2D31 ID75
1
3D40-1
8 **
9D04-4
2n2

1n5

2n2
FD27
10K 1u0 7D18-2 10K 1u0 7D23-2 * 2D58
7
8

2D59
1n5

10 5 3 6 4 5 4 5
10n 22K ** 10n 22K ID29
2D35

3D57

2D36
ID28
3D56

9D03-4 7 8
15K

15K

1n5
12 BC847BPN GND-DL ID35 GND-DR
12 ID45
3D81

680R

3D58

680R
ID34 3 2 4 5 3 ID33 2
2D71
FEEDBACK ID32 1
1

7D17 7D22 2D40 GND-DR


2D37

SI4532ADY SI4532ADY
1n5

2p2 3D39-3 ID36 3D40-2 ID37


3 6 VN 2 7 GND-DR
G 22K
GND-DL
22K
1n5
G
3D76

2D21

220n
22K

* BC817-25W ID38 * BC817-25W

3D79
3D65
1K2

1K2

22K
3D64

5D16 ID39
-12_20V VN ID40 5D14 ID41 5D15
220R -12_20V -12_20V
3D67 ID42 3D68 220R 3D69 ID43 3D70 220R
25V 100u

16V 100u

25V 100u

16V 100u
100n

ID44
2D38

* * * *
2D28

2D41

2D42

2D22

2D43

2D44
100n

100n
3K9 100K 3K9 100K
2D60
2D45

2D46
* *
1u0

1u0
2D47

2D48

2D49

2D50
1n5

2n2

1n5

2n2
1DM1 100n
GND-D ID46 EMC HOLE ID47

H 3D71 GND-DL GND-DL GND-DL 2D61 GND-DR 3D72 GND-DR GND-DR GND-DR
H
10K 100n 10K
3D73

560R

3D74

560R
2D62 GND-DL

100n

GND-D G_16290_048.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 65

SSB: Audio: Connectors


1 2 3 4 5 6 7
0M98 C6

B8B AUDIO: CONNECTORS B8B


0M99 C6
1740 C1
1M02 A1
1MM2 D6
2M10 A3
2M11 A3
2M12 B3
2M13 B3
-12-16V-NF
2M14 B2
A 2M10
A 2M15 C3
+12-16V-NF 2M16 C3
1M02
FM10 1n0 5M10 IM10 2M17 C3
-12_20V 2x8W (8 ohm) 2x15W (8 ohm) 2M18 C3
1
FM11
2 220R 3M04 B3
2M11 5M11 2M11 ---------- 1nF
3
FM12 2M13 ---------- 1nF 5M02 C4
4
5 1n0 220R
2M14 ---------- 1nF 5M03 C4
6 2M12 5M12 3M04 ---------- 100E
GND-D ---------- 5M09 B4
7
5M09 220E 100MHz
FM13 1n0 IM11 5M11 ---------- 220E 100MHz 5M10 A4
220R
B7B-PH-K +12_20V 5M11 A4
FM14 5M09 5M12 B4
B FM15
2M13
220R
B FM10 A2
1n0 FM11 A3
3M04 0V7 FM12 B2
PROT-AUDIOSUPPLY
2M14 100R IM12
FM13 B2
FM14 B2
1n0 FM15 B2
FM16 C2
FM17 C2
2M17 IM15 2M15
FM18 C2
1740 2n2 5M02 IM10 A4
2n2
C 1
2
FM16
FM17 220R IM13
LEFT-SPEAKER 0M98 0M99
C IM11 B4
IM16 2M16 IM12 B3
3 2M18
4 IM13 C4
GND-D 2n2 2n2 5M03 RIGHT-SPEAKER IM14 C4
B4B-EH-A
FM18 220R IM14
IM15 C3
IM16 C3

1MM2
EMC HOLE
D D

G_16290_049.eps
3104 313 6095.3 010206

1 2 3 4 5 6 7
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 66

SSB: SRP List Part 1

SRP List: Not available at the time of writing. As soon as it becomes available,
a Service Info or Service Manual update will be issued via the appropriate channels.

G_16290_096.eps
3104 313 6095.3 030206
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 67

SSB: SRP List Part 2

SRP List: Not available at the time of writing. As soon as it becomes available,
a Service Info or Service Manual update will be issued via the appropriate channels.

G_16290_096.eps
3104 313 6095.3 030206
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 68

Layout SSB (Top Side Overview)

1C51 A2 2C14 A3 2P20 F1 2TM7 A1 3A73 A2 3L51 C4 3P11 G1 3TH4 A1 3V01 D3 6B22 B1 7U13 G2 9T11 B1
1C52 A3 2C15 A3 2P22 G1 2TM8 A1 3A74 A2 3L52 B3 3P12 F1 3TH5 A1 3V02 E3 6B23 B1 7U14 G4 9TG2 A1
1C61 A3 2C16 B3 2P23 G1 2TN0 B1 3A75 A2 3L56 B3 3P13 G1 3TH6 B1 3V03 D3 6C51 A3 7U15 G2 9TG3 A1
1C62 A3 2C17 B3 2P24 F2 2TN1 A1 3A76 A2 3L57 B3 3P14 G1 3TH7 B1 3V04 E3 6C52 A3 7U17 G3 9U01 F3
1E41 A4 2C18 B3 2P25 G2 2TN3 A1 3A77 A4 3L58 B3 3P15 G1 3TH9 A1 3V05 D3 6C59 A3 7U18 G3 9U02 F3
1P02 G1 2C19 B3 2P31 F2 2TN4 B1 3A80 B2 3L59 B3 3P16 G1 3TJ0 B1 3V06 E3 6H07 C3 7U19 G3 9U03 G3
1T41 A2 2C20 B3 2P32 G1 2U08 G2 3A81 B2 3L60 B3 3P17 G1 3TJ1 B1 3V07 D3 6H08 D3 7U20 F2 9U07 F3
1T44 A1 2C22 B3 2P33 G1 2U09 G3 3A82 B2 3L61 B3 3P18 G1 3TJ2 A1 3V08 E3 6H09 D3 7U21 F2 9U13 F2
Part 1 1T55 A2 2C23 B3 2P34 F1 2U10 G3 3A83 B2 3L62 B3 3P19 G1 3TJ3 B1 3V09 D3 6J01 C4 7U22 F2 9U14 F2
1TG0 A1 2C27 B3 2P35 F1 2U11 G3 3A84 B2 3L63 C3 3P20 G1 3TJ4 A1 3V10 E3 6J06 C4 7U24 G2 9U15 F3
G_16290_050a.eps 1TG1 B1 2C28 B3 2P40 F1 2U12 G2 3A85 B2 3L64 C3 3P21 F2 3TJ5 A1 3V11 D3 6L00 C4 7U27 G4 9U16 F2
1U02 F3 2C31 A3 2P41 F1 2U13 G3 3A86 B4 3L65 C3 3P22 F2 3TJ6 B1 3V12 E3 6L01 C4 7U28 G4 9Z47 E1
1Z55 E1 2C35 A3 2P50 F1 2U14 G2 3AA3 A4 3L66 C3 3P23 F2 3TJ7 B1 3V13 D3 6L02 C3 7U29 G3
2A01 B4 2C36 A3 2P51 G2 2U15 G3 3B00 C1 3L67 C3 3P24 F2 3U00 G3 3V14 E3 6M10 A2 7V00 E3
2A25 B4 2C39 A3 2P76 F1 2U16 G3 3B01 C1 3L68 C3 3P25 F2 3U01 G3 3V15 D3 6M11 A2 7Z00 E1
2A29 A4 2C40 B3 2P77 F1 2U18 G3 3B02 C1 3L69 C3 3P26 F2 3U02 G3 3V16 E3 6P00 F1 7Z02 E1
2A33 A4 2C41 A3 2P80 F1 2U19 G3 3B03 C1 3L70 C3 3P27 G2 3U03 G3 3V17 D3 6U00 G2 7Z10 D1
2A34 A4 2C44 B3 2P81 F1 2U20 G3 3B04 C1 3L71 C3 3P28 G2 3U04 G3 3V18 E3 6U01 G2 7Z11 D1
2A35 A4 2C45 A3 2P82 F1 2U21 G3 3B05 C1 3L89 B3 3P29 G2 3U05 G3 3V19 E3 6U12 G3 7Z12 D1
2A36 A4 2C46 A3 2Q60 D2 2U23 G3 3B06 C1 3L99 C3 3P30 G2 3U06 G3 3V20 E3 6U17 G3 9A08 A4
2A37 A4 2C50 A3 2Q61 D2 2U26 G3 3B07 C1 3LA9 C2 3P31 G2 3U07 G3 3V21 D3 6U21 G3 9A19 A4
2A38 A4 2C55 A3 2Q62 D2 2U31 G3 3B08 C1 3LE1 C2 3P32 F1 3U08 G3 3V22 E3 6U22 G4 9A29 A4
2A39 A4 2C57 A3 2Q67 D3 2U32 G3 3B23 C1 3LG2 C2 3P33 G1 3U09 G2 3V23 E3 6U23 G4 9A75 B4
2A40 A4 2C58 A3 2Q68 E2 2U33 G4 3B40 B1 3LH2 C2 3P35 F1 3U10 G3 3V32 E3 7A01 B4 9A77 B4
2A41 B4 2C60 A3 2Q76 E4 2U37 G2 3B60 C1 3LH7 C2 3P36 F1 3U11 G3 3V33 D3 7A02 B3 9A78 B4
2A42 B4 2C63 A3 2Q85 E4 2U38 G3 3B61 B1 3LK9 C2 3P37 F1 3U12 G3 3V34 E3 7A04 A2 9A79 B3
2A43 B4 2C65 A3 2Q86 D4 2U39 G4 3B90 B1 3LM0 B2 3P38 F1 3U13 G3 3V35 E3 7A06 B2 9A82 A2
2A44 B4 2C67 A3 2Q91 F4 2U40 G3 3B92 B1 3LM1 B1 3P40 F1 3U14 G3 3V36 E3 7A10 A2 9A83 A2
2A45 B4 2C68 A3 2Q92 F3 2U41 G3 3B93 B1 3LM2 B2 3P43 G1 3U15 G3 3V37 D3 7A12 A2 9A86 B2
2A46 B4 2C70 A3 2T01 A1 2U43 G2 3B99 B1 3LM3 B1 3P45 F1 3U16 G3 3V38 E3 7A13 B3 9A90 B2
2A47 B4 2C72 A3 2T02 A1 2U44 G2 3C30 A3 3LM4 B2 3P50 G1 3U17 G3 3V39 E3 7A14 B2 9B03 C1
2A48 A4 2C78 A3 2T04 A1 2U47 G3 3C32 A3 3LM5 B1 3P51 G1 3U18 G3 3V40 E3 7A20 B4 9B30 B1
2A49 A4 2C79 A3 2T05 A1 2U55 G3 3C34 A3 3LM6 B1 3P52 G1 3U19 G2 3V41 D3 7A21 B4 9B31 B1
2A50 A4 2C83 A3 2T06 A1 2U60 F2 3C39 B3 3LM7 B2 3P53 G1 3U22 G3 3V42 E3 7B00 C1 9B38 B1
2A51 A4 2H00 D2 2T07 A1 2U61 F2 3C40 B3 3LN0 C1 3P57 F1 3U23 G3 3V43 D3 7B01 C1 9C46 B4
2A52 A4 2H02 D3 2T08 A2 2U63 F2 3C41 B3 3LN1 C2 3P60 F2 3U24 G3 3V47 E3 7B02 C1 9C50 A3
2A53 A4 2H03 D2 2T09 A1 2U64 F2 3C45 A3 3LN2 C2 3P61 F2 3U26 G3 3V48 E3 7B11 B1 9C51 A3
2A54 A4 2H11 E2 2T10 A1 2U65 F3 3C50 A3 3LN3 C2 3P62 G1 3U27 G3 3Z00 E1 7B30 B1 9C52 A3
2A55 A4 2H12 E2 2T11 A1 2U66 F3 3C53 A3 3LN4 C2 3P63 G1 3U28 G3 3Z10 E1 7B31 B1 9C53 A3
2A56 A4 2H13 E2 2T12 A1 2U71 G4 3C55 A3 3LN5 C2 3P73 F1 3U29 G3 3Z11 E1 7B38 B1 9C54 A3
2A57 A4 2J30 B4 2T13 A1 2U72 G3 3C56 A3 3LN6 C2 3P74 G1 3U30 G3 3Z47 E1 7C31 A3 9C56 A3
2A58 A4 2J31 B4 2T14 A1 2U73 G3 3C57 A3 3LN7 C2 3P75 G1 3U31 G3 3Z48 E1 7C53 A3 9C57 A3
2A59 A4 2J32 B4 2T15 A1 2U85 G3 3C58 A3 3LQ6 C2 3P76 F1 3U32 G3 3Z53 D1 7C54 A3 9C58 A3
2A60 A4 2J33 B4 2T16 A1 2V00 E3 3C59 A3 3LR0 C2 3P77 F1 3U33 G3 5A01 A4 7C55 A3 9C59 A3
2A61 A4 2J34 B3 2T17 A1 2V01 D3 3C60 A3 3LR1 C2 3P78 F1 3U34 G4 5A02 A4 7G04 F4 9C60 A3
2A62 A4 2J35 B3 2T18 A2 2V16 D3 3C61 A3 3LR3 C2 3P79 F1 3U35 G4 5A03 A4 7H01 F4 9C61 A3
2A63 A4 2J40 C4 2T19 A1 2V17 D3 3C65 A3 3LR4 C2 3P80 F1 3U36 G3 5A04 A4 7H02 D3 9H14 E2
2A64 A4 2J41 C4 2T20 A1 2V18 E3 3C66 A3 3LR5 C2 3P81 F1 3U37 G3 5A05 A4 7J00 C2 9H40 D3
2A65 A4 2J42 C4 2T21 A1 2V19 D4 3C67 A3 3LR6 C2 3P82 F1 3U38 G3 5A08 B4 7J06 C4 9J18 C4
2A66 A4 2J43 C4 2T23 A1 2V20 D3 3C71 A3 3LR7 C2 3P83 F1 3U39 G2 5A10 B4 7J07 C4 9J20 B3
2A67 A4 2J44 C4 2T24 A1 2V21 E4 3G08 F4 3LR8 C2 3P84 F1 3U41 G3 5B00 C1 7J08 C2 9J21 B3
2A68 A4 2J45 C4 2T25 A1 2V22 E3 3G09 F4 3LR9 C2 3P85 F2 3U42 G3 5B02 C1 7J10 B4 9LA5 B1
2A69 B4 2J46 C4 2T27 A1 2V23 D3 3G10 F4 3LS0 C2 3P86 F2 3U43 G4 5B20 B1 7J11 B4 9M00 A2
2A70 B4 2J47 C4 2T28 A1 2V24 E3 3G11 F4 3LS1 C2 3P88 F1 3U45 G3 5C01 B3 7J12 B3 9M01 B2
2A71 B4 2J48 C4 2T30 A1 2V25 E4 3G15 F4 3LS3 B1 3Q01 E2 3U46 G3 5C03 B3 7J13 B4 9M02 B1
2A72 B4 2J49 C4 2T31 B1 2V26 D3 3G16 F4 3LS4 B1 3Q02 F4 3U52 G4 5C33 A3 7LA2 B1 9M04 B1
2A73 B4 2J57 C4 2T32 B1 2V27 D3 3G17 F4 3LS5 B1 3Q10 F2 3U53 G4 5C35 B3 7LB0 C4 9M05 B2
2A74 B4 2J66 C4 2T33 B1 2V28 E3 3G18 F4 3LS6 B1 3Q16 D4 3U54 G2 5C36 B3 7LB1 C4 9M06 A2
2A75 A4 2J71 C4 2T34 B1 2V29 E3 3G57 F4 3LS7 B1 3Q20 D3 3U55 G2 5C57 A3 7LB2 C3 9P01 F1
2A76 A4 2J72 C4 2T35 A1 2V30 D3 3G58 F4 3LT3 B4 3Q21 D3 3U56 G2 5H02 D3 7LB4 B4 9P05 F1
2A77 A4 2J73 C4 2T43 A1 2V31 E3 3G59 F4 3LT4 B4 3Q23 D3 3U57 G2 5H03 D3 7LB5 B4 9P06 F1
2A78 A4 2J74 B4 2T45 A1 2V39 E3 3G60 F4 3LT5 B4 3Q24 D3 3U60 G2 5H04 D3 7M01 A2 9P07 F1
2A79 B2 2J76 C4 2T48 A1 2V40 E3 3G77 F3 3LT6 B4 3Q29 E4 3U61 G2 5H05 D2 7M03 A2 9P08 F1
2A81 A2 2K40 A3 2T51 A1 2V41 E4 3G78 F3 3LT7 B4 3Q30 E4 3U62 G3 5J08 B4 7M04 A2 9P09 F1
2A82 A4 2K41 A3 2T53 A1 2Z20 E1 3H04 E2 3LT8 B4 3Q31 F3 3U63 G3 5J09 B4 7M05 B2 9P10 G1
2A83 A2 2K43 A3 2T55 A2 2Z22 E1 3H05 E2 3LU4 C3 3Q32 F3 3U64 G3 5J13 C2 7M06 A1 9P16 F1
2A84 A2 2K45 A3 2T56 A2 2Z26 E1 3H24 D2 3LU5 C3 3Q42 D4 3U65 G3 5J15 B4 7M07 A2 9P17 F1
2A89 A2 2K46 A3 2T58 A1 2Z28 E1 3H25 D2 3LU6 C3 3Q62 E1 3U66 G3 5J16 B4 7M10 A2 9P18 F1
2A90 B2 2K47 A3 2T98 A1 3A03 A4 3H26 D2 3LU7 C3 3Q64 E2 3U67 G3 5P02 F1 7M11 A2 9P19 F2
2A92 A4 2K64 A3 2TG0 B1 3A07 B3 3H40 D3 3LU8 C3 3Q95 E4 3U68 G3 5P08 F1 7M12 A2 9P30 G1
2A93 A2 2K65 A3 2TG1 A1 3A08 B3 3H41 D3 3LU9 C4 3Q97 F3 3U69 G3 5Q06 E2 7N00 C1 9P31 G1
2A97 A4 2L50 C3 2TG2 A1 3A09 B3 3H50 D2 3LV0 C4 3Q98 F3 3U70 G3 5Q07 D2 7O00 D1 9P32 G1
2A98 A2 2L51 C3 2TG3 A1 3A10 B3 3H51 D3 3LV1 C4 3T02 A1 3U71 G3 5Q08 D2 7P00 F1 9P33 F2
2A99 A2 2L52 B3 2TG4 B1 3A11 B3 3H89 D3 3LV2 C4 3T03 A1 3U72 F2 5Q11 D4 7P03 G1 9P34 F2
2AA3 B3 2L53 B3 2TG5 A1 3A12 B3 3H92 E2 3LV3 C4 3T04 A1 3U73 F2 5Q12 D4 7P10 G2 9P35 G1
Part 2 2AA5 B2
2AA6 B2
2L54
2L55
B3
C4
2TG6 B1
2TG7 A1
3A14 B2
3A20 A2
3J02
3J05
C3
C3
3LV4
3LV5
C4
C4
3T05
3T06
A1
A1
3U74
3U75
F2
F2
5Q13
5T10
D4
A1
7P13
7P14
F2
F1
9P36
9P37
F2
F2
G_16290_050b.eps 2AA8 B4
2AA9 B4
2L56
2L57
B3
B3
2TG8 B1
2TG9 B1
3A21 A2
3A22 A2
3J06
3J14
C2
C2
3LV6
3LV7
C4
C4
3T07
3T08
A1
A1
3U76
3U77
F2
F2
5T11
5T42
B1
A2
7P15
7P16
F1
F1
9P38
9P39
F1
F1
2AAA B4 2LT1 B4 2TJ0 A1 3A23 A2 3J25 C4 3LV8 C4 3T09 B1 3U80 G3 5T44 A1 7P17 F1 9P40 F1
2AAB B4 2LT3 C3 2TJ1 A1 3A24 B2 3J26 C4 3M00 A2 3T10 A1 3U82 G3 5T45 A1 7P18 F1 9P41 F1
2AB1 B2 2LT4 C4 2TJ2 A1 3A25 B2 3J28 C4 3M01 A2 3T11 A1 3U83 G3 5T46 A1 7P31 F2 9P42 F1
2AB2 A2 2LT5 C4 2TJ3 B1 3A26 A2 3J49 C4 3M02 A2 3T12 B1 3U85 G2 5T47 A1 7P32 G1 9P45 F1
2AB3 B2 2LT6 C2 2TJ4 A1 3A27 A2 3J60 B4 3M03 A2 3T13 B1 3U86 G2 5T48 A1 7P34 G2 9P46 F1
2AB5 A3 2LT7 C3 2TJ5 A1 3A29 A2 3J61 B4 3M04 A2 3T14 B1 3U87 G2 5T49 A1 7P74 G1 9P47 F1
2AB6 B4 2M90 B2 2TJ6 A1 3A30 A2 3J62 B4 3M05 A2 3T15 A1 3U88 G2 5T50 A1 7P76 F1 9P48 F1
2AB8 A3 2M91 B2 2TJ7 A1 3A37 A2 3J63 B4 3M09 A2 3T16 A1 3U89 G2 5T51 A1 7P77 F1 9P49 F1
2B00 C1 2M92 B2 2TJ8 A1 3A38 A2 3J64 B4 3M14 A2 3T17 A1 3U90 F3 5T53 A1 7P80 F1 9P50 F1
2B01 C1 2M93 A2 2TJ9 A1 3A41 A2 3J65 B4 3M70 A2 3T18 A1 3U91 F3 5T55 A2 7P81 F1 9P51 F1
2B02 C1 2M94 A1 2TK0 A1 3A42 B2 3J66 B4 3M71 A2 3T19 B1 3U92 F3 5TG0 A1 7Q01 D3 9P52 F1
2B37 B1 2N05 C1 2TK1 A1 3A43 A2 3J67 B4 3M72 A2 3T20 B1 3U93 G2 5TG1 A1 7Q05 F3 9P53 F1
2B38 B1 2N06 C1 2TK2 A1 3A44 B2 3J68 B4 3M73 B2 3T21 B1 3U94 G2 5TG2 A1 7T00 A2 9P54 F1
2BA0 B1 2N08 C1 2TK3 A1 3A45 B2 3J69 B3 3M74 A2 3T22 B1 3U95 G2 5TG3 A1 7T10 B1 9P55 F1
2BA2 B1 2N10 C1 2TK4 B1 3A56 A2 3J70 B4 3M75 B2 3T23 B1 3U96 G3 5TG4 A1 7T11 A1 9P56 F1
2BA3 B1 2N11 C1 2TK5 A1 3A59 A2 3J71 B4 3M76 A2 3T24 B1 3U97 G3 5TG5 A1 7T12 B1 9P79 F1
2BA8 B1 2P02 F1 2TK6 A1 3A60 A3 3J72 B3 3M77 A2 3T25 A1 3U98 F3 5TG6 A1 7T41 A1 9Q13 D3
2C03 A3 2P03 G1 2TK7 A1 3A61 A3 3J73 B3 3M78 B2 3T26 B1 3U99 F2 5TG7 B1 7T43 A1 9Q14 D3
2C04 A3 2P04 G1 2TK8 A1 3A62 A2 3J74 B4 3M79 A2 3TG2 A1 3UA1 G3 5TG8 A1 7TG0 B1 9Q15 D3
2C05 A3 2P06 F1 2TK9 A1 3A63 A2 3J75 B3 3M80 B2 3TG3 A1 3UA2 G3 5U10 G4 7TG1 A1 9Q16 D3
2C06 A3 2P07 F1 2TL0 A1 3A64 A2 3J76 B3 3M81 B2 3TG4 A1 3UA3 G3 5U11 G4 7TG3 A1 9Q17 D3
2C07 A3 2P09 G1 2TL7 A1 3A65 A2 3J77 B3 3M82 B2 3TG5 A1 3UA4 G3 5U12 G4 7TG4 A1 9Q18 C3
2C08 A3 2P10 F1 2TL9 B1 3A67 A2 3J86 C4 3M85 B1 3TG6 A1 3UA5 G3 5U13 G4 7U00 G3 9Q20 E4
2C09 A3 2P15 G1 2TM2 A1 3A68 A2 3J92 C4 3M86 B1 3TG8 B1 3UA6 G2 5U14 G4 7U05 G3 9Q62 F3
2C11 A3 2P16 F1 2TM3 A1 3A69 A2 3J99 C4 3N20 C1 3TG9 B1 3UA8 G4 6A00 A2 7U07 G4 9Q63 F3
2C12 A3 2P18 G1 2TM4 A1 3A71 A2 3L06 C2 3N25 C1 3TH0 A1 3UA9 G4 6A01 A2 7U10 G3 9T04 A1
G_16290_050.eps
3104 313 6095.3 270106
2C13 A3 2P19 G1 2TM5 A1 3A72 A2 3L50 B3 3P10 G1 3TH3 A1 3V00 E3 6A10 A4 7U11 G3 9T10 B1
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 69

Layout SSB (Top Side Part 1)

Part 1

G_16290_050a.eps
270106
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 70

Layout SSB (Top Side Part 2)

Part 2

G_16290_050b.eps
270106
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 71

Layout SSB (Overview Bottom Side)


1A10 A3 2D50 F1 2U64 E2 3D45 F1 3LN2 B2 3U93 F2 7D26 F2
1T01 A3 2D51 F2 2U65 E2 3D49 F1 3LN3 C2 3U94 F2 7D30 E2
1T11 A2 2D55 F1 2U66 E2 3D50 E1 3LN4 C2 3U95 F2 7D31 F2
1U02 E2 2D63 E2 2U72 F3 3D51 F1 3LN5 C2 3U96 F3 7J00 C2
2A01 A3 2D64 E2 2U73 F3 3D54 F1 3LN6 C2 3U97 F3 7J01 B3
2A02 A3 2D65 E2 2U85 F3 3D56 E1 3LN7 C2 3U98 E3 7J02 B3
2A10 A4 2D66 E2 2V00 D3 3D57 F1 3LQ6 C2 3U99 E2 7J05 E4
2A11 A4 2D70 F2 2V01 C3 3D58 F1 3LR3 B2 3UA1 F3 7J06 E3
2A12 A4 2D71 E1 2V16 C3 3D64 E1 3LR4 B2 3UA2 F3 7P15 E1
2A13 A4 2D72 F2 2V17 C3 3D65 F1 3LU7 C2 3UA3 F3 7P16 E1
2A14 A4 2G35 E4 2V18 D3 3D67 E1 3LU8 C2 3UA4 F3 7P17 E1
2A15 A4 2H07 D1 2V20 D3 3D68 E1 3LV7 C2 3UA5 F3 7T10 A1
2A16 A4 2H10 D3 2V21 D4 3D69 F1 3LV8 C2 3UA8 F3 7T12 A2
2A17 A4 2H11 D3 2V22 D3 3D70 F1 3M04 F4 3UA9 F3 7T13 A3
2A18 A4 2H12 D3 2V23 C3 3D71 E1 3P57 E1 3V00 D3 7T22 A3
2A20 A4 2J40 C4 2V24 D3 3D72 F1 3P80 D1 3V01 C3 7T23 A3
2A21 A4 2J41 C4 2V25 D4 3D73 E1 3P81 D1 3V02 D3 7U00 F3
2A26 A4 2J42 C4 2V26 C3 3D74 F1 3P82 D1 3V03 C3 7U05 F3
2A27 A4 2J43 C4 2V27 C3 3D75 F2 3P83 E1 3V04 D3 7U07 F3
2A30 A4 2J44 C4 2V28 D3 3D76 E1 3P84 E1 3V05 C3 7U10 F3
2A31 A4 2J45 C4 2V29 D3 3D77 E1 3P85 E1 3V06 D3 7U13 F2
2A32 A3 2J46 C4 2V30 D3 3D78 F1 3P86 E1 3V07 C3 7U15 F2
2A33 A3 2J47 C4 2V31 D3 3D79 F1 3P88 E1 3V08 D3 7U20 E2
2A34 A3 2J48 C4 3999 F3 3D81 E1 3Q12 D1 3V09 C3 7U21 E2
2A35 A4 2J49 C4 3A04 A4 3D82 F2 3Q13 D1 3V10 D3 7U22 E2
2A38 A4 2J72 C4 3A10 A4 3D83 F2 3Q17 D1 3V11 C3 7U27 F3
2A39 A4 2J73 C4 3A11 A4 3D84 F2 3Q27 C1 3V12 D3 7U28 F4
2A40 A4 2J77 E3 3A12 A4 3D85 F2 3T10 A1 3V13 C3 7U29 F3
2A41 A4 2L50 B3 3A13 A4 3D86 F2 3T15 A2 3V14 D3 7V00 D2
2A43 A4 2L51 B3 3A14 A4 3D87 F2 3T18 A2 3V15 C3 9A01 A3
2A44 A4 2L52 B3 3A15 A4 3D88 F2 3T20 A1 3V16 D3 9A02 B3
2A45 A4 2L53 B3 3A16 A4 3D89 F1 3T21 A2 3V17 D3 9A10 A4
2A51 A4 2L54 B3 3A17 A3 3D90 E2 3T22 A2 3V18 D3 9A15 A4
2A55 A3 2L55 B4 3A18 A4 3D91 E2 3T23 A2 3V19 D3 9A19 A3
2A60 A3 2L56 B3 3A19 A4 3H04 D1 3T25 A2 3V20 D3 9B38 A2
2A61 A3 2L57 B3 3A23 A4 3H05 D1 3T27 A2 3V21 D3 9B50 A2
Part 1 2A62
2A63
A3
A3
2LA2
2LT0
C2
B3
3A24
3A25
A4
A4
3H52
3H53
D3
D3
3T28
3T29
A2
A2
3V22
3V23
D3
D3
9B51
9B52
A2
A2
G_16290_051a.eps 2A64
2A65
A3
A3
2M10
2M11
F4
F4
3A26
3A27
A4
A3
3H71
3H90
C3
C3
3T31
3T35
A3
A3
3V24
3V25
D3
D3
9B53
9B54
A2
A1
2A66 A3 2M12 F4 3A28 A3 3H97 E3 3T36 A3 3V32 D3 9D03 E1
2A67 A3 2M13 F4 3A29 A3 3I69 E1 3T37 A3 3V33 D3 9D04 F1
2A68 A3 2M14 F4 3A33 A3 3J15 E4 3T38 A3 3V34 D3 9D48 F1
2A69 A3 2M15 F4 3A34 A3 3J16 E4 3T39 A3 3V35 D3 9H03 C3
2A71 A4 2M17 F4 3A35 A4 3J17 E4 3T40 A2 3V36 D3 9H04 C3
2A73 A4 2P35 E1 3A60 A4 3J18 E4 3T41 A3 3V37 D3 9H07 C3
2A76 A4 2P80 C1 3A61 A4 3J19 E3 3T43 A2 3V38 D3 9H08 C3
2A97 A4 2P81 D1 3A62 A4 3J20 E4 3T44 A3 3V39 D3 9H13 C3
2B12 A2 2T10 A1 3A63 A4 3J21 E4 3T48 A3 3V40 D3 9H16 C3
2B13 A2 2T11 A1 3B50 A2 3J22 E4 3T51 A3 3V41 D3 9J21 E4
2B14 A2 2T12 A2 3B51 A2 3L00 B3 3T52 A3 3V42 D3 9J23 C2
2B15 A2 2T13 A1 3B52 A2 3L01 B3 3T53 A3 3V43 C3 9LA0 B2
2B16 A2 2T14 A1 3B53 A1 3L02 B4 3T54 A3 5A11 A3 9LA1 B2
2B17 A2 2T15 A2 3B54 A2 3L03 B3 3T55 A3 5A12 A4 9LA2 B2
2B18 A1 2T16 A3 3B55 A1 3L21 B3 3T56 A3 5A13 A4 9P24 B4
2B19 A1 2T17 A3 3B56 A1 3L22 B3 3T57 A3 5A14 A4 9P25 B4
2B20 A2 2T18 A1 3B57 A1 3L50 B3 3T58 A3 5A15 A4 9T10 A3
2B21 A2 2T19 A3 3B58 A2 3L51 B4 3U00 F2 5A18 A2 9T11 A3
2B22 A2 2T20 A3 3B59 A1 3L52 B3 3U01 F2 5A64 A4 9T12 A3
2B23 A2 2T21 A3 3B60 A1 3L56 B3 3U02 F3 5A65 A4 9T13 A3
2B24 A1 2T22 A3 3B61 A1 3L57 B3 3U03 F2 5B10 A2 9U01 E2
2B25 A1 2T23 A2 3B62 A2 3L58 B3 3U04 F2 5B65 A2 9U02 E2
2B35 A1 2T24 A1 3B65 A2 3L59 B3 3U05 F3 5B67 A2 9U03 F3
2B36 A1 2T25 A1 3B66 A2 3L60 B3 3U06 F3 5B69 A2 9U07 E2
2B37 A1 2T26 A2 3B67 A2 3L61 B3 3U07 F3 5B71 A2 9U13 E2
2B38 A1 2T27 A1 3B68 A2 3L62 B3 3U08 F3 5B73 A2 9U14 E2
2B39 A1 2T30 A3 3B69 A2 3L63 B3 3U09 F2 5B75 A2 9U15 E2
Part 2 2B45
2B50
A2
A2
2T31
2T37
A3
A3
3B70
3B71
A2
A2
3L64
3L65
C3
B3
3U10
3U11
F2
F3
5D16
5M02
F1
F4
9U16 E2

G_16290_051b.eps 2B51
2B52
A2
A2
2T39
2T40
A3
A3
3B72
3B73
A2
A2
3L66
3L67
C3
B3
3U12
3U13
F3
F3
5M09
5M10
F4
F4
2B55 A2 2T41 A3 3B74 A2 3L68 C3 3U14 F3 5M11 F4
2B56 A2 2T42 A2 3B75 A2 3L69 B3 3U15 F3 5M12 F4
2B57 A2 2T43 A2 3B76 A2 3L70 C3 3U16 F3 5T11 A1
2B58 A2 2T45 A3 3B80 A1 3L71 B4 3U17 F3 6A11 A4
2B59 A2 2T46 A2 3B81 A2 3L75 B1 3U18 F3 6D10 E2
2B60 A2 2T47 A3 3B82 A1 3L76 B1 3U19 F2 6D11 E2
2B61 A2 2T48 A3 3B83 A1 3L83 C2 3U22 F3 6H01 E3
2B62 A2 2T49 A2 3B84 A1 3L85 C1 3U23 F3 6H03 E3
2B63 A2 2T50 A2 3B85 A1 3L89 B4 3U24 F3 6H07 D4
2B64 A2 2T52 A2 3B86 A1 3L99 B3 3U26 F3 6J07 B4
2B65 A2 2T53 A2 3B87 A1 3LA0 B2 3U27 F3 6J08 B4
2B66 A2 2T54 A2 3B88 A1 3LA2 B2 3U28 F3 6U11 F2
2B67 A2 2T60 A2 3B89 A2 3LA3 B2 3U29 F3 6U21 F3
2B68 A2 2T61 A2 3D10 F2 3LA4 B2 3U30 F3 6U22 F3
2B69 A2 2T65 A3 3D12 E2 3LA5 B2 3U31 F3 6U23 F3
2B70 A2 2T66 A3 3D13 F2 3LA7 B1 3U32 F3 6U25 F4
2B71 A2 2T67 A3 3D14 F2 3LA9 B2 3U33 F3 7A08 A4
2B72 A2 2U09 F2 3D15 E2 3LB7 C2 3U37 F2 7A10 A4
2B75 A2 2U10 F3 3D16 E2 3LB8 C2 3U38 F2 7A11 A3
2B76 A2 2U11 F3 3D17 F2 3LB9 C2 3U54 F2 7A14 A3
2B77 A2 2U12 F2 3D18 F2 3LC9 B2 3U55 F2 7A15 A3
2B78 A2 2U13 F3 3D19 E2 3LD2 B2 3U56 F2 7A16 A3
2B79 A2 2U14 F2 3D20 E2 3LE1 C2 3U72 E2 7A20 A4
2B80 A2 2U15 F3 3D21 F2 3LG2 C2 3U73 E2 7B45 A2
2D11 F2 2U16 F3 3D22 E2 3LH2 C2 3U74 E2 7B50 A1
2D19 F1 2U18 F3 3D23 F2 3LH7 C2 3U75 E2 7D10 F2
2D26 E1 2U19 F3 3D24 E2 3LK9 C2 3U76 E2 7D11 E2
2D27 F1 2U20 F3 3D25 F2 3LL3 C2 3U77 E2 7D12 F2
2D30 E1 2U21 F3 3D26 F2 3LL8 C2 3U82 F3 7D14 E1
2D31 F1 2U23 F3 3D34 E1 3LL9 C2 3U83 F3 7D15 E1
2D35 E1 2U26 F3 3D35 E1 3LM0 B2 3U85 F2 7D16 E1
2D36 F1 2U31 F2 3D37 F1 3LM2 B2 3U86 F2 7D17 E1
2D38 F1 2U32 F3 3D38 F1 3LM3 B2 3U87 F2 7D19 F1
2D45 E1 2U37 F2 3D39 E1 3LM4 B2 3U88 F2 7D20 F1
2D46 F1 2U41 E2 3D40 F1 3LM5 B2 3U89 F2 7D21 F1
2D47 E1 2U52 E4 3D42 F2 3LM7 B2 3U90 E3 7D22 F1
G_16290_051.eps 2D48 E1 2U60 E2 3D43 F1 3LN0 B2 3U91 E3 7D24 F1
3104 313 6095.3 270106 2D49 F1 2U63 E2 3D44 E1 3LN1 B2 3U92 E2 7D25 F2
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 72

Layout SSB (Bottom Side Part 1)

Part 1

G_16290_051a.eps
270106
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 73

Layout SSB (Bottom Side Part 2)

Part 2

G_16290_051b.eps
270106
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 74

Side I/O Panel: (42” & 50”)


1 2 3 4 5 6 7 8 9 1001 B2 9012 A6
1002-1 B1 9013 A6

D SIDE I/O (37”, 42”, & 50”) JAGUAR ONLY D 1002-2 C1


1002-3 D1
F001 A2
F002 A2
F012 5000 F013 1005 A8 F003 B2
1010 E1 F004 C2

PDZ6.8-B
F001 220R
C

100u 6.3V
6000
1050 A7 F005 C2

1101

3000

1112
75R
2012 1101 A3 F006 D2
Y / CVBS I004
A A 1102 B3 F007 E2

PDZ6.8-B
1106 C3 F008 E2

6001
2 4 3 1 F002
1M60 1H01 1005 1108 D3 F009 E2
TO 1H01 1
9012
1
2
F014 1050 F015 1
USB 1109 E3 F010 F8
2 2
9013 3 1110 F3 F011 F9
F016 F017
F020
3
4
4
5 6
3
4 CONNECTOR 1111 E3 F012 A6
DLW31S
VIPER B4B-PH-K 6 5 1112 A7 F013 A7

PDZ6.8-B
1H01 A6 F014 A6

1102

6002
1001 1M36 B8 F015 A7
5
1M37 B8 F016 A6

3004

75R
B I009 B
1M60 A5 F017 A7
TO 1M36

PDZ6.8-B
F003 1M65 D8 F018 F7

6003
2003 C5 F019 F2
1
1002-1 1M36 1M37 2004 C3 F020 B4
YELLOW
1 1 SSB EMGT 2005 C4 F021 C6
2 2 2 2006 D3 F022 C6
3009 F022 3
4
3
4
OR 2007 D4 F023 C6
1K0 5 5 2008 F2 F024 E6
4
TO 1M36
PDZ6.8-B
F004 F021 6 6
1002-2
1106

2004

680p

3010

2005

100p
6004

33K
WHITE GND_AUD 7 7 2009 F5 F025 E6
C F005 8 8 C 2010 E2 I001 C2
5 6 9004 9 9

3011

3008

RES 2003

9003
3K9

2K2
2011 E5 I002 C3

1u0
I002 F023
I001
10
11
13
SCART 3 EMGT
10
11 2012 A7 I003 D2
PDZ6.8-B

GND_AUD GND_AUD GNDB 12


6005

B11B-PH-SM4-TBT(LF) OR 3000 A4
3004 B3
I004 A3
I005 F4

7 F006 GND_AUD 3012 TO 1M36 3008 C5 I006 F4


3009 C4 I007 E4
9005

1002-3 1K0
RED
PDZ6.8-B

3010 C4 I008 E4
1108

2006

3013

2007

100p
680p
6006

33K
8 9 I003 SSB JAGUAR 3011 C5
3012 D4
I009 B3
I010 D3
D D
I010 3013 D4 I011 F7
1M65
PDZ6.8-B

GND_AUD GND_AUD 3016 F5 I012 F8


6007

1 3020 E5 I013 F3
2
3 3999 F9 I014 E3
5 4
GND_AUD 5000 A6
F007
F024 6000 A3
6001 A3
1109

6002 B3
GNDB 6003 B3
E GNDB E
I008 F025 6004 C3
9011
1010 5 6005 C3
PDZ6.8-B

I007
2010

1111

4 6006 D3
22n

6010
3020

2011

2 9010
10K

F008
10n

6007 D3
F009 I014
3 GNDB GNDB 6008 F3
7
PDZ6.8-B

F019 6009 F3
6011

8
1 GNDB GNDB 6010 E3
GNDB 6011 F3
GNDB I006
9009 9003 C6
F I005 9006 9007 3999 F 9004 C2
PDZ6.8-B
2008

1110

3016

2009
10K
22n

10n

6008
9008 I011 150R 9005 D2
I012
I013 F018
GNDB GNDB GNDB GNDB 9006 F7
PDZ6.8-B

GNDB GND_AUD F010 F011 9007 F8


6009 9008 F4
9009 F4
GNDB
G_16290_055.eps 9010 E4
3104 313 6137.1 010206 9011 E4
1 2 3 4 5 6 7 8 9
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 75

Layout Side I/O Panel: (42” & 50”) (Top Side) Layout Side I/O Panel: (42” & 50”) (Bottom Side)

1001 B1 2003 A1
1002 A1 2004 A1
1005 A1 2005 A1
1010 A1 2006 A1
1050 A1 2007 A1
1H01 A1 2008 A1
1M36 B1 2009 A1
1M37 B1 2010 A1
1M60 A1 2011 A1
1M65 A1 3000 B1
2012 A1 3004 B1
5000 A1 3008 A1
3009 A1
3010 A1
3011 A1
3012 A1
3013 A1
3016 A1
3020 A1
3999 B1
6000 B1
6001 B1
6002 B1
6003 B1
6004 A1
6005 A1
6006 A1
6007 A1
6008 A1
6009 A1
6010 A1
6011 A1
9003 A1
9004 A1
9005 A1
9006 A1
9007 B1
9008 A1
9009 A1
9010 A1
9011 A1
9012 A1
9013 A1

G_16290_056.eps G_16290_057.eps
3104 313 6137.1 300106 3104 313 6137.1 300106
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 76

Control Panel (42” & 50”)


1701 A1 1704 A2 1M01 A4 3004 C1 3007 C1 3999 C4 9003 C2 F003 C4 I007 C1 I010 C2 I102 B1 I105 B3
1702 A1 1705 A1 3002 C2 3005 C1 3008 C1 9001 C3 F001 A4 F004 C4 I008 C1 I100 B1 I103 B2 Personal Notes:
1703 A2 1706 A3 3003 C2 3006 C1 3009 C2 9002 C1 F002 A4 I006 C1 I009 C2 I101 B1 I104 B2

1 2 3 4

CONTROL BOARD
E E
To 1M01

1M01
F001 LED PANEL
KEYBOARD
F002 1
OR
2
A 3
TO 1K02
A
SSB LC4.x
OR
SKQNAB

SKQNAB

SKQNAB

SKQNAB

SKQNAB

SKQNAB
1701

1702

1705

1704

CHANNEL+ 1703

1706
TO 1M01
CHANNEL-
VOLUME-
VOLUME+

MENU

ON / OFF
EXTERNALS

B I100 I101 I102 I103 I104 I105 B


3005

3004

3002
3006

3003

* * * * *
I006 I007 I008 I009 I010

F003 F004
C 3999
C
9002

3007

3008

3009

9003

9001

10K
* * * *

D D

F_15890_053.eps
3104 313 6129.1 071105

1 2 3 4

E_06532_012.eps
131004
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 77

Layout Control Panel (42” & 50”) (Top Side)

3104 313 6129.1


F_15890_057.eps
071105

Layout Control Panel (42” & 50”) (Bottom Side)

3104 313 6129.1


F_15890_058.eps
071105
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 78

LED Panel (42” ME5FL)


1 2 3 4 5 6 7 8 9 10 11 12 13 14
0001 A10 9119 E2
0002 A11 9120 B10

J LED PANEL J
0345 D2
1040 F9
1M01 C2
9121 B11
9122 F11
F010 A3
1M20 A2 F011 A3
0001 0002
EMC HOLE EMC HOLE 2014 C4 F012 A3
A 1M20
F010
9015 KEYBOARD "RED" A 2030 G5 F013 B3

STATUS-POWER

LED1
TO 1M20 2040 F9 F014 B3
1 F011 3011
"BLUE" or 2070 F12 F015 A3

+5V2-STBY
2 COM-SND
2071 G12 F016 B3
3 100R

+8V
SSB 4
JL2.x / LC4.x 5
6
F012
F015
9016

9017
LED1

RC
"GREEN" 3011 A4
3030 G4
3031 G5
F017 B3
F018 B2
F021 C3
OR

+5V2-STBY
TO 1M20 7 F017 3032 G5 F038 B12

9120

9121
8 LIGHT-SENSOR
3033 G5 F039 B12
9 F013

+8V
10 +8V 3034 G6 F083 D3

330R

560R
(RES)
3051

3052
EXTERNALS 11 F014 3035 G6 F084 D3

9064
FTx2.x / Bx2.x 12 3036 G7 F086 E3
B 13 14
F016
9012 LED2 B 3037 G7 F089 E3
3040 F9 I010 F2
F018 F038 3999 F039

330R

560R
3061

3062
I053 3041 G9 I011 G2
+5V2-STBY 10K 3042 F9 I012 E3

9065

SML512BC4T
3051 B8 I013 E4

1
OPT_LED
3052 B8 I026 F12
3053 C8 I033 G4

6051
I062
3054 C8 I037 G7

2
3055 C8 I038 G6
9053
3056 D6 I039 G4
7062 7051
TO 1M01 BC857B
I065 3061 B6 I040 G5
BC847BW
1M01 3062 B6 I041 G9
C C

9011

9052
1 F021
3063 D5 I042 G9
2 KEYBOARD 3064 D5 I043 F9
CONTROL
3 I052 3070 G11 I044 F9
BOARD 4 5 I095 3071 F12 I045 F9

100n

SML512BC4T
2014 3072 G13 I046 E9

100R
3053

3054

3055
10K

10K
6060
3073 G13 I047 G4
(RES) 3074 F13 I048 G5
I063 3075 F14 I049 G7
9063
3076 G14 I051 D8
I061 7061
BC847BW 3077 G12 I052 C8
7052

(RES)
100R
3063

3064

9062
3078 G11 I053 B9

10K
BC847BW

9066
D D 3091 G2 I054 D7

9054
3092 F2 I061 D6
9083 3093 F3 I062 C6
+5V2-STBY
I054 3094 F2 I063 D7

(RES)
3056

9056
I051

10K
I064
0345
F083 3096 G3 I064 D5
9110 9111 LIGHT-SENSOR 3999 B12 I065 C9
TO 0345 1
9112 F084 9113 KEYBOARD
2 6030 G4 I071 F11
9114 I012 9115 RC
3 6031 G4 I072 F14

LED1

LED1

LED2
9116 F086 9117 I013 BLACKLIGHT-TC
4 9081 6051 C8 I073 G12
TOP CONTROL 9118 LED1
5 9082 F089
9119
6 LED2 6060 C6 I074 G12
7 8 6070 G11 I075 F12

RC

LIGHT-SENSOR

LIGHT-SENSOR
+5V2-STBY
7030 G6 I076 F13
E E 7031 G7 I093 F2
7032 G4 I094 F3
7051 C8 I095 C6
I046 7052 D8

+5V2-STBY
7061 D6
+5V2-STBY

7062 C6

330R
3040
7070-1 F12
2070 I026 7070-2 G13
I044 7092 F2
3092

10K

470n 9011 C6
I094

+5V2-STBY
9012 B4

+5V2-STBY
+5V2-STBY

3071 3074 I072 9015 A4

9041

9043

9122

9070
F F

100u 16V
3042

2040
9016 A4

6K8
I010 3094 I093 4M7 +8V 10K
3093

10K

COM-SND 7092 9017 A4


BC847BW 1040
10K I043 9031 G4

4
9071
VS I045 I071 9040 G9

8
I075 2 5 I076
"LED DIMMING" OUT
1 7 3075 9041 F9

6070
LM358P

TEMD5000
3030

3035

3036

3037
3 6 9042 G9

2R2

2R2
4K7

4K7

8
7070-1 7070-2 4K7
+8V LM358P 9043 F9

4
GND
TSOP34836YA1 I042 9052 C9
I073 +8V 3073 9053 C8
9093

3041
9031

10K
I038 I049 I074
3034 9054 D9

9040

9042
I011 3096 I037 3K3

3076
9056 D7

3K3
STATUS-POWER

10u 16V
6030 I047 3031 I040 3033 I048 1K0
I039

3078

9072

3070

2071

3077

3072
2M2

4M7
G G

3K3

1K0
10K BC857BW BCP53 9062 D7
7030 7031
3091

10K

BAS316 100K 1K0 9063 D6


6031 I033 3032
BLACKLIGHT-TC
9064 B7
10u 16V

I041
9065 B7
2030

7032 180K
BC847BW BAS316 9066 D7
9070 F11
9071 F11
9072 G11
9081 E4
"IR RECEIVER" "LIGHT SENSOR" 9082 E3
9083 D3
9093 G2
H H 9110 D2
9111 D4
9112 D2
9113 D4
9114 E2
F_15400_070.eps 9115 E4
3104 313 6074.3 090505 9116 E2
9117 E4
9118 E2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 79

Layout LED Panel (42” ME5FL) (Top and Bottom Side)


0345 --
1040 --
1M01 --
Personal Notes:
3031 --
3032 -- 1M20 --
3033 -- 2014 --
3055 -- 2030 --
3056 -- 2040 --
3070 -- 2070 --
6030 -- 2071 --
6031 -- 3011 --
6051 -- 3030 --
6060 -- 3034 --
6070 -- 3035 --
7030 -- 3036 --
7031 -- 3037 --
7052 -- 3040 --
7062 -- 3041 --
9011 -- 3042 --
9031 -- 3051 --
9054 -- 3052 --
9056 -- 3053 --
9066 -- 3054 --
9110 -- 3061 --
9112 -- 3062 --
9114 -- 3063 --
9116 -- 3064 --
9118 -- 3071 --
9119 -- 3072 --
9120 -- 3073 --
3074 --
3075 --
3076 --
3077 --
3078 --
3091 --
3092 --
3093 --
3094 --
3096 --
3999 --
7032 --
7051 --
7061 --
7070 --
7092 --
9012 --
9015 --
9016 --
9017 --
9040 --
9041 --
9042 --
9043 --
9052 --
9053 --
9062 --
9063 --
9064 --
9065 --
9070 --
9071 --
9072 --
9081 --
9082 --
9083 --
9093 --
9111 --
9113 --
9115 --
9117 --
9121 --
9122 --
E_06532_012.eps
131004
F_15400_071.eps
3104 313 6074.3 090505
Circuit Diagrams and PWB Layouts EP1.1U AA 7. EN 80

Front IR / LED Panel (42” & 50” ME6) Layout Front IR / LED Panel (42” & 50” ME6) (Top Side)
1870 A1 6801 A1 7802 A1 7808 A1
1870 B1 3802 A4 3808 E3 4806 E4 6801-2 B4 7802 C3 7808 E4 F805 C1 I804 C4 I811 E4
2801 D4 3803 C4 3809 E4 4807 E3 6802 E4 7803 B4 F801 C1 F806 B1 I805 A4
2802 D4 3804 B3 3810 E4 4808 D3 6803 C3 7804 C4 F802 C1 I801 B3 I806 B4
2803 E3 3805 C4 3811 E4 4809 D4 6809 D3 7805 B3 F803 B1 I802 B4 I809 E3
3801 B3 3807 E2 3812 D4 6801-1 B4 7801 B4 7807 E3 F804 B1 I803 B3 I810 E4

1 2 3 4

J IR/LED/LIGHT-SENSOR (32”, 37”, & 42”) J


+3V3STBY

A A
3802
330R

I805
7805
BC847B
7801
7803
I801 BC857B BC847B

B I803 B

I802
3

1
6801-2
TO 1K00 OF SSB BD

6801-1
1870 3801 3804 GREEN
3K3 0R SPR-325MVW RED
1 F806 LIGHT-SENDOR-SDM
SPR-325MVW

2
2 I806
F803 IR
3 F804
4 F805 LED_SEL
5 F802 +3V3STBY
G_16290_065.eps
6 F801 PC-TV-LED 3139 123 6171.1 300106

+3V3STBY 7804 3805


6803 BC847B 0R
BZX384-C3V9
C 3803
C
220R Layout Front IR / LED Panel (42” & 50” ME6) (Bottom Side)
2801 A1 3801 A1 3804 A1 3808 A1 3811 A1 4807 A1 4815 A1 6809 A1 7804 A1
I804 2802 A1 3802 A1 3805 A1 3809 A1 3812 A1 4808 A1 6802 A1 7801 A1 7805 A1
7802 2803 A1 3803 A1 3807 A1 3810 A1 4806 A1 4809 A1 6803 A1 7803 A1 7807 A1
3V5 3
VS
2801 2802
3V5 1 10u 10u
OUT 6.3V
6809
2
GND +3V3STBY
RES TSOP34836LLIB

D D
(ITV ONLY)
4808

4809

+3V3STBY

3812 220R
I810
TSAL4400-MS21

(ITV ONLY)
(ITV ONLY)

3808 3810
6808

7808
RES BPW34 RES
7807
RES 4806
E I809 6802 E
I811
3807
RES
RES
2803 3809 3811
1u0 2M2 RES
4807

G_16290_064.eps
3139 123 6171.1 300106

1 2 3 4

G_16290_066.eps
3139 123 6171.1 300106
Alignments EP1.1U 8. EN 81

8. Alignments
Index of this chapter: 8.3 Software Alignments
8.1 General Alignment Conditions
8.2 Hardware Alignments
Put the set in SAM mode (see the "Service Modes, Error Codes
8.3 Software Alignments
and Fault Finding" section). The SAM menu will now appear on
8.4 Option Settings the screen. Select ALIGNMENTS and go to one of the sub
menus. The alignments are explained below.
8.1 General Alignment Conditions
Notes:
• All changes must be stored manually.
8.1.1 Start Conditions
• If an empty EAROM (permanent memory) is detected, all
settings are set to pre-programmed default values.
Perform all electrical adjustments under the following
conditions:
8.3.1 General
• Power supply voltage: 120 VAC / 60 Hz (± 10%).
• Connect the set to the AC Power via an isolation
transformer with low internal resistance. For the next alignments, supply the following test signals via a
• Allow the set to warm up for approximately 15 minutes. video generator to the RF input: NTSC M/N TV-signal with a
• Measure voltages and waveforms in relation to chassis signal strength of at least 1 mV and a frequency of 61.25 MHz
ground (with the exception of the voltages on the primary (channel 3).
side of the power supply).
Caution: It is not allowed to use heatsinks as ground. Tuner AGC
• Test probe: Ri > 10 Mohm, Ci < 20 pF. Purpose: To keep the tuner output signal constant as the input
• Use an isolated trimmer/screwdriver to perform signal amplitude varies.
alignments.
For this chassis, no alignment is necessary, as the AGC
8.1.2 Initial Settings alignment is done automatically (standard value: “32”).

Perform all electrical adjustments with the following initial 8.3.2 White Point
settings (via the "Active Control" button on the RC):
1. To avoid the working of the lightsensor, set ACTIVE • Set ACTIVE CONTROL to OFF.
CONTROL to OFF. • In the [MENU] -> PICTURE user menu, set:
2. Set SMART PICTURE to NATURAL/ECO. – DYNAMIC CONTRAST to OFF.
– COLOUR ENHANCEMENT to OFF.
8.1.3 Alignment Sequence – COLOUR to "0".
– CONTRAST to "100".
• First, set the correct options: – BRIGHTNESS to "50".
– In SAM, select (SERVICE) OPTIONS -> OPT. NO, • Go to the SAM and select ALIGNMENTS -> WHITE
– Fill in the option settings according to the set sticker POINT.
(see also paragraph "Option Settings"),
– Select STORE OPTIONS and push OK on the remote Method 1 (with color analyzer):
control, • Use a 100% white screen as input signal and set the
– After storing, the set must be restarted! following values:
• Warming up (>10 minutes). – COLOR TEMPERATURE: "Tint to be aligned".
• White point alignment. – All WHITE POINT values to: "127".
– RED BL OFFSET value to: "9".
– GREEN BL OFFSET value to: "8".
8.2 Hardware Alignments • Measure with a calibrated (phosphor- independent) color
analyzer in the centre of the screen. Consequently, the
For the specific PDP screen alignments, see the measurement needs to be done in a dark environment.
• Adjust, by means of decreasing the value of one or two
white points, the correct x,y coordinates (see table "White
D alignment values"). Tolerance: dx,dy: ± 0.004.
• Repeat this step for the other Color Temperatures that
need to be aligned.
• When finished press STORE (in the SAM root menu) to
store the aligned values to the NVM.
• Restore the initial picture settings after the alignments.

Table 8-1 White D alignment values

Color Temp. Cool Normal Warm


(degr. K) (11000) (9100) (6500)
x 0.276 0.285 0.313
y 0.282 0.293 0.329

When such equipment is not available, use “method 2”.


EN 82 8. EP1.1U Alignments

Method 2 (without color analyzer):


If you do not have a color analyzer, you can use the default
values. This is the next best solution. The default values are
average values coming from production (statistics).
1. Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
2. Set the RED, GREEN and BLUE default values according
to the values in the "Tint settings" table.
3. When finished press STORE (in the SAM root menu) to
store the aligned values to the NVM.
4. Restore the initial picture settings after the alignments.

Table 8-2 Tint settings

Colour Temp. R G B
Cool 125 120 91
Normal 127 121 74
Warm 124 78 35
Alignments EP1.1U 8. EN 83

8.4 Option Settings which ICs to address. The presence / absence of these specific
ICs (or functions) is made known via the option codes.
8.4.1 Introduction
Notes:
2
• After changing the option(s), save them via “STORE”.
The microprocessor communicates with a large number of I C
• The new option setting is only active after the TV is
ICs in the set. To ensure good communication and to make switched "off" and "on" again with the Mains switch (the
digital diagnosis possible, the microprocessor has to know
EAROM is then read again).

8.4.2 Dealer Options

Table 8-3 Dealer options

Menu item Subjects Options Description


Personal Options Picture Mute On Picture mute active in case no picture detected
Off Noise in case of no picture detected
Virgin Mode On TV starts up (once) with a language selection menu after the Mains switch is turned "on" for the first time (virgin mode)
Off TV does not start up (once) with a language selection menu after the Mains switch is turned "on" for the first time (virgin
mode)
2CS Korea (only for AP On
region) Off

8.4.3 (Service) Options

Select the sub menu's to set the initialization codes (options).

Table 8-4 Service options

Menu-item Subjects Options Description


PIP/DS Dual Screen None / 1 tuner / 2 tuners no DS / DS with one tuner / DS with two tuners
Data EPG On / Off Feature present / not present
RRT Yes / No Parental control is enabled via the Regional Rating Table (RRT)
Display Screen “Value” Used screen size, type, and resolution (see table “Display code overview” in chapter “Service
Modes”for the values)
Scanning Backlight On / Off Feature present / not present
Dimming Backlight On / Off Feature present / not present
Video Repro Picture Processing Spider / No Spider Feature present / not present
Combfilter None / 2D / 3D Only selectable with Columbus in set: No/without RAM/with RAM
Ambient Light None / Mono / Stereo Inverter not present / two inverters mono / two inverters stereo
MOP On / Off Feature present / not present (for sets with AmbiLight this is “on”)
Source Selection HDMI 1 None / Audio / No Audio No HDMI / HDMI with analog audio / HDMI without analog audio
HDMI 2 None / Audio / No Audio No HDMI / HDMI with analog audio / HDMI without analog audio
USB version None / 1.1 / 2.0 + CR No USB / USB 1.1 in side I/O panel / USB 2.0 in cardreader panel
IEEE1394 Yes / No Connector present / not present
Ethernet Yes / No Connector present / not present
S/PDIF inputs None / 1 conn. / 2 conn. None / 1 connector present (in)/ 2 connectors present (in/out)
Audio Repro Subw. Internal Present Yes / No Internal sub woofer present / not present
Acoustic System (Cabinet design, None n.a.
used for setting dynamic audio Entry ME5 15W e.g. 32/37PF7320A
parameters).
(Soft) Wrap n.a.
Top e.g. 42PF9830A
Entry+ e.g. 32PF9630A, 42PF9730A
Eco ME5 5W e.g. 26PF5321D
Eco ME5 15W e.g. 32/37/42PF5321D
Eco ME6 5W e.g.
Others n.a.
Miscellaneous Alternative Tuner Philips / Alps Tuner brand
Tuner Type TD1336S Tuner type
Opt. no. Group 1 xxxxx xxxxx xxxxx xxxxx (see set sticker)
Group 2 xxxxx xxxxx xxxxx xxxxx (see set sticker)

8.4.4 Opt. No. (Option numbers)

Select this sub menu to set all options at once (expressed in Example: The options sticker gives the following option
two long strings of numbers). numbers (depending on the model):
An option number (or "option byte") represents a number of • 00016 00006 00033 14979
different options. When you change these numbers directly, • 01035 00000 04768 00000
you can set all options very quickly. All options are controlled The first line (group 1) indicates hardware options 1 to 4, the
via eight option numbers. second line (group 2) indicates software options 5 to 8.
When the EAROM is replaced, all options will require resetting. Every 5-digit number represents 16 bits (so the maximum value
To be certain that the factory settings are reproduced exactly, will be 65536 if all options are set).
you must set both option number lines. You can find the correct When all the correct options are set, the sum of the decimal
option numbers on a sticker inside the TV set. values of each Option Byte (OB) will give the option number.
EN 84 8. EP1.1U Alignments

Table 8-5 Option code overview

Byte Bit (dec. value) Subject Options Settings (in decimal values) Remarks
1 0 (1) Video Repro Picture Processing 0= No Spider, 1= Spider Spider availability, influences,
digital options.
1 (2)
2 (4)
3 (8) Comb Filter 0= None, 8= 2D Comb (Columbus without DRAM),
16= 3D Comb (Columbus with DRAM)
4 (16)
5 (32) Ambient Light 0= None, 32=Ambi-light Stereo, 64= Ambi-light Mono
6 (64)
7 (128)
8 (256) Dual Screen 0= None, 256= One Tuner DS, 512= Two Tuner DS
9 (512)
10 (1024) MOP 0= Off, 1024= On Matrix Output Processor (or EBILD)
11 (2048) JOP 0= Off, 2048= On Jaguar Output Processor (or EBILD)
Reserved for future use
12 (4096) POD 0= Off, 4096= On
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
2 0 (1) Sound Repro Acoustic System (Cabinet) 0= None, 1= Entry_ ME5_5W, 2= Entry_ME5_15W, 3= (Soft)Wrap, 4= Top, Cabinet design, used for setting dy-
5= Entry+, 15= Others namic audio parameters.
1 (2)
2 (4)
3 (8)
4 (16) Aux Headphone Sound 0= Off, 16= On Dual AC3 sound in Aux available.
5 (32) n.a.
6 (64) n.a.
7 (128) n.a.
8 (256) n.a.
9 (512) Sub woofer Internal 0= Not Present, 512= Present
10 (1024) Centre Mode Support 0= Not Supported, 1024= Supported
11 (2048) n.a.
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
3 0 (1) Source Select HDMI1 0= None, 1= With analog audio, 2= Without analog audio
1 (2)
2 (4) HDMI2 0= None, 4= With analog audio, 8= Without analog audio
3 (8)
4 (16) n.a.
5 (32) USB Version 0= None, 32= USB 1.1, 64= USB 2.0 + Card reader USB support.
6 (64)
7 (128) IEEE1394 0= Not Present, 128= Present
8 (256) Ethernet 0= LAN not present, 256= LAN present
9 (512) RRT 0= Off, 512= On Regional Rating Table (RRT)
10 (1024) S/PDIF Inputs 0= None, 1024= 1 Connector, 2048= 2 Connectors
11 (2048)
12 (4096) LCOS I/O 0= Not Present, 4096= Present
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
4 0 (1) Region Region 0= EU, 1= AP-P, 2= AP-N, 3= US, 4= Latam
1 (2)
2 (4)
3 (8) Interconnect China IF 0= Off, 8= On
4 (16) Alternative Tuner 0= Philips, 16= Alps Tuner make.
5 (32) Tuner Type 0= TD1336s (B-Chassis US), 32= TD1331(J-Chassis US), Tuner type
64= UV1318 (Analogue EU), 96= TD1316 (Hybrid EU) (B-chassis US is e.g "BP2.3U").
6 (64)
7 (128) Source Select n.a.
8 (256) AV1 0= CVBS/RGB, 256= CVBS/YC/LR, 512= CVBS/YC/YPbPr/HV/LR Input type.
9 (512)
10 (1024) AV2 0= CVBS/YC/RGB/P50, 1024= CVBS/YC/LR Input type.
11 (2048)
12 (4096) AV3 0= Not Available, 4096= CVBS, 8192= YPbPr Input type.
13 (8192)
14 (16384) AV4 0= Not Available, 16384= YPbPr Input type.
15 (32768)
Alignments EP1.1U 8. EN 85

Byte Bit (dec. value) Subject Options Settings (in decimal values) Remarks
5 0 (1) Display Screen See table “Display code overview” in chapter “Service Modes”for the values. Screen size, type, and resolution.
1 (2)
2 (4)
3 (8)
4 (16)
5 (32)
6 (64)
7 (128)
8 (256) n.a.
9 (512) n.a.
10 (1024) Dimming Backlight 0= Off, 1024= On
11 (2048) Scanning Backlight 0= Off, 2048= On
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
6 0 (1) Miscellaneous Monitor 0= Off, 2= On Reserved for future use
1 (2) n.a.
2 (4) Stand Alone 0= Off, 4= On Reserved for future use
3 (8) n.a.
4 (16) n.a.
5 (32) n.a.
6 (64) Proximity Sensor 0= Off, 64= On
7 (128) n.a.
8 (256) Touch Pad 0= Off, 256= On Reserved for future use
9 (512) n.a.
10 (1024) n.a.
11 (2048) n.a.
12 (4096) n.a.
13 (8192) n.a.
14 (16384) n.a.
15 (32768) n.a.
7 0 (1) Personal Self Learning TV 0= Off, 1= On Reserved for future use
1 (2) Auto Store Mode 0= None, 2= PDC/VPS, 4= TXT Page, 6= PDC/VPS/TXT Page Fixed to: "None" in the AP-N and
US versions.
2 (4)
3 (8) 2CS Korea 0= Off, 8= On, 16= Auto
4 (16)
5 (32) Picture Mute 0= Off, 32= On
6 (64) n.a.
7 (128) Virgin Mode 0= Off, 128= On
8 (256) Hotel Mode 0= Off, 256= On
9 (512) Content Browser 0= Not Present, 512= Present
10 (1024) Connected Planet 0= Off, 1024= Full Connected Planet + logo support
11 (2048)
12 (4096) n.a.
13 (8192) EPG 0= None, 8192= TXT Guide only, 16384= NextView 2C3, 24576 = NexTView 2
14 (16384)
15 (32768) TV Guide USA (Gemstar) 0= Off, 32768= On
8 0 (1) n.a. n.a.
1 (2) n.a. n.a.
2 (4) n.a. n.a.
3 (8) n.a. n.a.
4 (16) n.a. n.a.
5 (32) n.a. n.a.
6 (64) n.a. n.a.
7 (128) n.a. n.a.
8 (256) n.a. n.a.
9 (512) n.a. n.a.
10 (1024) n.a. n.a.
11 (2048) n.a. n.a.
12 (4096) n.a. n.a.
13 (8192) n.a. n.a.
14 (16384) n.a. n.a.
15 (32768) n.a. n.a.
EN 86 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets


Index of this chapter: When the input channel is a digital channel, it is processed via
9.1 Introduction the QAM demodulator and then passed to the multi-media
9.2 Abbreviation List processor (VIPER), which handles the synchronization and
9.3 IC Data Sheets display of audio-visual material.

Notes: Signal Processing


• Only new circuits (circuits that are not published recently) The AVIP together with the MPIF device is used to perform the
are described. For other descriptions see the BP2.xU input decoding of a single stream of analog audio and video
manual (3122 785 15540). broadcast signals. In addition, the AVIP is used for decoding
• Figures can deviate slightly from the actual situation, due and presentation of audio output streams. The main data
to different set executions. connection between MPIF and AVIP is done via an I2D bus.
• For a good understanding of the following circuit The AVIP converts the incoming video data to ITU-656 format
descriptions, please use the wiring, block (chapter 6) and for communication to the VIPER IC.
circuit diagrams (chapter 7). Where necessary, you will find The audio data is transferred between the AVIP and VIPER
a separate drawing for clarification. using I2S.
The AVIP IC is controlled by the VIPER via the I2C bus.
The key part in the system, the VIPER, performs almost all key
9.1 Introduction features, like video quality enhancement, motion
compensation, picture-in-picture processing, and others. It is a
This chassis is specifically developed for ATSC reception completely digital IC with a TriMedia DSP (Digital Signal
without CableCARDTM, and is in fact derived from the BL2.xU/ Processor) core and a MIPS microcontroller core. The DSP
BP2.xU chassis. The key components are: and some additional cores are used to do the video feature
• MPIF (PNX3000). processing and some auxiliary sound feature processing. The
• AVIP/COLUMBUS (PNX2015). MIPS microcontroller core is used for all internal and external
• VIPER 2 (PNX8550). controlling tasks including a system wide I2C bus.
The VIPER provides a primary digital (YUV or RGB) output to
Some delta’s with respect to the BL2.xU/BP2.xU chassis: the LVDS transmitter.
• No POD, so only unscrambled ATSC channels.
• Audio Amplifier is integrated on the SSB.
• I/O’s are integrated on the SSB.
• One HDMI connector (i.o. two).
• One USB1.1 connector (i.o. USB2.0).
• No card reader.
• No MOP (EPLD), due to the fact that these sets do not
come with AmbiLight.

9.1.1 Features

The main features for this chassis are:


• The move from the analog world to the digital world. W.o.w.
from signal processing via "hardware circuits" to signal
processing via "software algorithms". This means: no
software = no picture and sound!
• Fit for both analog and digital signal processing, this by
converting analog signals into digital transport streams and
allowing seamless zapping between all possible signal
sources. This makes the chassis applicable for e.g.
receiving ATSC in an integrated product form.
• The internal digital processing allows new "Multi-Media"
applications such as Content Browser, Memory Card Slot,
Local Area Network support and all kinds of streaming
applications.
• The chassis can be upgraded in the future with internal
functionality such as Personal Video Recording, DVD/RW.

9.1.2 Chassis Block Diagram

Description below refers to the block diagrams in chapter 6


“Block Diagrams, Test Point Overview, and Waveforms”.

Analog Reception
The TV receives multimedia information by tuning the Hybrid
tuner (for analog and digital reception) to one of many 6 MHz
input channels available via a cable connection. When the
input channel is an analog channel, the signal is processed via
the NTSC decoder and the VBI data decoder of the MPIF.

Digital Reception
The TV receives multimedia information by tuning to one of
many 6 MHz input channels available via a cable connection.
Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 87

SSB Cell Layout

Figure 9-1 SSB top view

Figure 9-2 SSB bottom view


EN 88 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.2 Abbreviation List CVBS Composite Video Blanking and


Synchronization
0/6/12 SCART switch control signal on A/V DAC Digital to Analogue Converter
board. 0 = loop through (AUX to TV), 6 DBE Dynamic Bass Enhancement: extra
= play 16:9 format, 12 = play 4:3 low frequency amplification
format DDC See "E-DDC"
2DNR Spatial (2D) Noise Reduction D/K Monochrome TV system. Sound
3DNR Temporal (3D) Noise Reduction carrier distance is 6.5 MHz
AARA Automatic Aspect Ratio Adaptation: DFU Directions For Use: owner's manual
algorithm that adapts aspect ratio to DMR Digital Media Reader: card reader
remove horizontal black bars; keeps DNR Digital Noise Reduction: noise
the original aspect ratio reduction feature of the set
ACI Automatic Channel Installation: DRAM Dynamic RAM
algorithm that installs TV channels DRM Digital Rights Management
directly from a cable network by DSP Digital Signal Processing
means of a predefined TXT page DST Dealer Service Tool: special remote
ADC Analogue to Digital Converter control designed for service
AFC Automatic Frequency Control: control technicians
signal used to tune to the correct DTCP Digital Transmission Content
frequency Protection; A protocol for protecting
AGC Automatic Gain Control: algorithm that digital audio/video content that is
controls the video input of the feature traversing a high speed serial bus,
box such as IEEE-1394
AM Amplitude Modulation DVD Digital Versatile Disc
ANR Automatic Noise Reduction: one of the DVI(-d) Digital Visual Interface (d= digital only)
algorithms of Auto TV EAS Emergency Alert Signalling; A cable
AP Asia Pacific TV standard (SCTE18) to signal
AR Aspect Ratio: 4 by 3 or 16 by 9 emergency information to digital
ASF Auto Screen Fit: algorithm that adapts terminal devices
aspect ratio to remove horizontal black ECM Entitlement Control Message
bars without discarding video E-DDC Enhanced Display Data Channel
information (VESA standard for communication
ATSC Advanced Television Systems channel and display). Using E-DDC,
Committee, the digital TV standard in the video source can read the EDID
the USA information form the display.
ATV See Auto TV EDID Extended Display Identification Data
Auto TV A hardware and software control (VESA standard)
system that measures picture content, EEPROM Electrically Erasable and
and adapts image parameters in a Programmable Read Only Memory
dynamic way EMI Electro Magnetic Interference
AV External Audio Video EMM Entitlement Management Message
AVIP Audio Video Input Processor EPLD Erasable Programmable Logic Device
B/G Monochrome TV system. Sound EU Europe
carrier distance is 5.5 MHz EXT EXTernal (source), entering the set by
BTSC Broadcast Television Standard SCART or by cinches (jacks)
Committee. Multiplex FM stereo sound FAT Forward Application Transport
system, originating from the USA and channel
used e.g. in LATAM and AP-NTSC FBL Fast BLanking: DC signal
countries accompanying RGB signals
B-TXT Blue TeleteXT FDC
C Centre channel (audio) FDS Full Dual Screen (same as FDW)
CA(M) Conditional Access (Module) FDW Full Dual Window (same as FDS)
CEC Consumer Electronics Control bus: FLASH FLASH memory
remote control bus on HDMI FM Field Memory or Frequency
connections Modulation
CIS Card Information Structure: Protocol FTV Flat TeleVision
which identifies the card in a POD Gb/s Giga bits per second
module G-TXT Green TeleteXT
CL Constant Level: audio output to H H_sync to the module
connect with an external amplifier HD High Definition
COLUMBUS COlor LUMinance Baseband HDD Hard Disk Drive
Universal Sub-system HDCP High-bandwidth Digital Content
ComPair Computer aided rePair Protection: A "key" encoded into the
CP Connected Planet / Copy Protection HDMI/DVI signal that prevents video
CSM Customer Service Mode data piracy. If a source is HDCP coded
CSS Content Scrambling System; An and connected via HDMI/DVI without
encryption method for MPEG-2 video the proper HDCP decoding, the
on DVDs. The algorithm and keys picture is put into a "snow vision"
required to decode the disc are stored mode or changed to a low resolution.
on the DVD-player For normal content distribution the
CTI Color Transient Improvement: source and the display device must be
manipulates steepness of chroma enabled for HDCP "software key"
transients decoding.
HDMI High Definition Multimedia Interface
HP HeadPhone
Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 89

I Monochrome TV system. Sound OTC On screen display Teletext and


carrier distance is 6.0 MHz Control; also called Artistic (SAA5800)
I2 C Integrated IC bus P50 Project 50: communication protocol
I2D Integrated IC Data bus between TV and peripherals
I2S Integrated IC Sound bus PAL Phase Alternating Line. Color system
IB In Band channel mainly used in West Europe (color
IF Intermediate Frequency carrier= 4.433619 MHz) and South
Interlaced Scan mode where two fields are used America (color carrier PAL M=
to form one frame. Each field contains 3.575612 MHz and PAL N= 3.582056
half the number of the total amount of MHz)
lines. The fields are written in "pairs", PCB Printed Circuit Board (same as
causing line flicker. "PWB")
IR Infra Red PCM Pulse Code Modulation
IRQ Interrupt Request PCMCIA Personal Computer Memory Card
ITU-656 The ITU Radio communication Sector International Association
(ITU-R) is a standards body PDP Plasma Display Panel
subcommittee of the International PFC Power Factor Corrector (or Pre-
Telecommunication Union relating to conditioner)
radio communication. ITU-656 (a.k.a. PIP Picture In Picture
SDI), is a digitized video format used PLL Phase Locked Loop. Used for e.g.
for broadcast grade video. FST tuning systems. The customer
Uncompressed digital component or can give directly the desired frequency
digital composite signals can be used. POD Point Of Deployment: A removable
The SDI signal is self-synchronizing, CAM module, implementing the CA
uses 8 bit or 10 bit data words, and has system for a host (e.g. a TV-set)
a maximum data rate of 270 Mbit/s, POR Power On Reset, signal to reset the uP
with a minimum bandwidth of 135 Progressive Scan Scan mode where all scan lines are
MHz. displayed in one frame at the same
ITV Institutional TeleVision; TV sets for time, creating a double vertical
hotels, hospitals etc. resolution.
JOP Jaguar Output Processor PSIP Program and System Information
LS Last Status; The settings last chosen Protocol: A standard for (broadcast)
by the customer and read and stored digital television. PSIP consists of
in RAM or in the NVM. They are called channel mapping data, program guide
at start-up of the set to configure it data, information about closed
according to the customer's captions and content advisory ratings,
preferences and other data related to the current
LATAM Latin America and future programs.
LCD Liquid Crystal Display PTC Positive Temperature Coefficient,
LED Light Emitting Diode non-linear resistor
L/L' Monochrome TV system. Sound PWB Printed Wiring Board (same as "PCB")
carrier distance is 6.5 MHz. L' is Band PWM Pulse Width Modulation
I, L is all bands except for Band I QAM Quadrature Amplitude Modulation;
LORE LOcal REgression approximation modulation method
noise reduction QTNR Quality Temporal Noise Reduction
LPL LG.Philips LCD (supplier) QVCP Quality Video Composition Processor
LS Loudspeaker RAM Random Access Memory
LVDS Low Voltage Differential Signalling RGB Red, Green, and Blue. The primary
Mbps Mega bits per second color signals for TV. By mixing levels
M/N Monochrome TV system. Sound of R, G, and B, all colors (Y/C) are
carrier distance is 4.5 MHz reproduced.
MOP Matrix Output Processor RC Remote Control
MOSFET Metal Oxide Silicon Field Effect RC5 / RC6 Signal protocol from the remote
Transistor, switching device control receiver
MPEG Motion Pictures Experts Group RESET RESET signal
MPIF Multi Platform InterFace ROM Read Only Memory
MUTE MUTE Line R-TXT Red TeleteXT
NC Not Connected RRT This is one of the PSIP tables received
NICAM Near Instantaneous Compounded via an ATSC compliant transport
Audio Multiplexing. This is a digital stream. In case of the OpenCable
sound system, mainly used in Europe. compliant transport stream, RRT is
NTC Negative Temperature Coefficient, received via the out of band SI
non-linear resistor SAM Service Alignment Mode
NTSC National Television Standard S/C Short Circuit
Committee. Color system mainly used SCART Syndicat des Constructeurs
in North America and Japan. Color d'Appareils Radiorecepteurs et
carrier NTSC M/N= 3.579545 MHz, Televisieurs
NTSC 4.43= 4.433619 MHz (this is a SCL Serial Clock I2C
VCR norm, it is not transmitted off-air) SCL-F CLock Signal on Fast I2C bus
NVM Non-Volatile Memory: IC containing SD Standard Definition
TV related data such as alignments SDA Serial Data I2C
O/C Open Circuit SDA-F DAta Signal on Fast I2C bus
OOB Out Of Band channel SDI Serial Digital Interface, see “ITU-656”
OSD On Screen Display SDRAM Synchronous DRAM
EN 90 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

SECAM SEequence Couleur Avec Memoire.


Color system mainly used in France
and East Europe. Color carriers=
4.406250 MHz and 4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SOG Sync On Green
SOPS Self Oscillating Power Supply
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SSB Small Signal Board
STBY STandBY
SOG Sync On Green
SVGA 800x600 (4:3)
SVHS Super Video Home System
SW Software
SWAN Spatial temporal Weighted Averaging
Noise reduction
SXGA 1280x1024
TFT Thin Film Transistor
THD Total Harmonic Distortion
TMDS Transmission Minimized Differential
Signalling
TXT TeleteXT
TXT-DW Dual Window with TeleteXT
uP Microprocessor
UXGA 1600x1200 (4:3)
V V-sync to the module
VCR Video Cassette Recorder
VESA Video Electronics Standards
Association
VGA 640x480 (4:3)
VL Variable Level out: processed audio
output toward external amplifier
VSB Vestigial Side Band; modulation
method
WYSIWYR What You See Is What You Record:
record selection that follows main
picture and sound
WXGA 1280x768 (15:9)
XTAL Quartz crystal
XGA 1024x768 (4:3)
Y Luminance signal
Y/C Luminance (Y) and Chrominance (C)
signal
YPbPr Component video. Luminance and
scaled color difference signals (B-Y
and R-Y)
YUV Component video
Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 91

9.3 IC Data Sheets

This section shows the internal block diagrams and pin


configurations of ICs that are drawn as "black boxes" in the
electrical diagrams (with the exception of "memory" and "logic"
ICs).

9.3.1 Diagram A3, AVS1ACP08 (IC 7H05)

Block Diagram
AVS1ACP08 AVS12CB
MODE
7
VSS 1
Supply Reset
VDD 4
MR A2
Mains
mode 2
VM 8 Peak Voltage Parasitic
Dectector Filter CP Controller Q

Zero Crossing
Detector S VG G
Triggering Q 5 3
CP Time 1
OSC/IN 2 Controller
V DD A1
Oscillator
OSC/OUT 3 4

Pin Configuration

VSS 1 8 VM
Osc/In 2 7 Mode

Osc/Out 3 6 N.C.

VDD 4 5 VG
G_16290_081.eps
020206

Figure 9-3 Internal block diagram and pin configuration


EN 92 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.2 Diagram A4, MC34067P (IC 7U01)

Block Diagram Pin Configuration


15
VCC
Enable / 9 VCC UVLO / 5.0 V 5
Vref
MC34067
UVLO Adjust Enable Reference
1
Osc Charge Osc Charge 1 16 One–Shot RC
Variable Vref UVLO
2
Osc RC Frequency Osc RC 2 15 VCC
Oscillator 3 Oscillator
Control Current 14 Osc Control Current 3 14 Drive Output A
Output A
16
Steering
Gnd 4 13 Power Gnd
One–Shot One–Shot
Flip–Flop 12 Vref 5
Output B 12 Drive Output B
Error Amp 6 2.5 V
Output Clamp 13 Error Amp Out 6 11 CSoft–Start
Noninverting 8 Pwr Gnd
Input Inverting Input 7 10 Fault Input
Inverting Input 7 Enable/UVLO
Noninverting Input 8 9
Error Adjust
11 Amp Soft–Start 10
Soft–Start Fault Detector Fault Input (Top View)

4 Ground
F_15710_163.eps
230905

Figure 9-4 Internal block diagram and pin configuration

9.3.3 Diagram B1A, NCP5422ADR2G (IC 7U00)

Block Diagram VCC ROSC

BIAS CURRENT
+ SOURCE
GEN RAMP1 RAMP2

+ VCC
8.6 V BST

7.8 V
IS+1
CLK1
+ BST
OSC GATE(H)1
IS−1
− + − CLK2 S
Reset non−overlap
IS+2 70 mV Dominant VCC
PWM FAULT GATE(L)1
+ Comparator 1 R
IS−2
− + − FAULT

70 mV S Q FAULT
Set RAMP1
Dominant
− 0.425 V BST
R GATE(H)2
+ − S
+ + non−overlap
− 0.25 V Reset
FAULT Dominant VCC
PWM GATE(L)2
Comparator 2 R
RAMP2 FAULT
E/A OFF
GND
+ E/A OFF
− 0.425 V 1.2 mA FAULT
5.0 A + E/A1 −
1.0 V −
− +
+

E/A2
1.0 V

VFB1 COMP1 VFB2 COMP2

Pin Configuration

SO−16
1 16
GATE(H)1 GATE(H)2
GATE(L)1 GATE(L)2
NCP5422A

GND
AWLYWW

VCC
BST ROSC
IS+1 IS+2
IS−1 IS−2
VFB1 VFB2
COMP1 COMP2

A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
F_15400_129.eps
240505

Figure 9-5 Internal block diagram and pin configuration


Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 93

9.3.4 Diagram B2A, NXT2004 (IC 7T22)

Block Diagram

VSB/QAM MPEG
IF In A/D
text text FEC
text
Demodulator Transport

Sense
32K x 8
RF Gain text
SRAM BERT
text
AGC
text
IF AGC
RF AGC

µC
text
Crystal OSC
text

I2 C
Tuner Control
I2C Compatible
GPIO text
Slave Interface
Smart Antenna
(CEA 909)

I2C_SLAVE_ADDR_0
I2C_SLAVE_ADDR_1
Pin Configuration
DVDD_PLL

BIAS_RES

GPIO_1
GPIO_0
GPIO_2

GPIO_3
GPIO_4

GPIO_5

VDD1.2
VDD3.3
VDD1.2

VDD3.3

DGND
DGND

DGND

DGND
DGND
DGND
DGND
AGND

AG N D
AVDD

AVDD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76

AVDD_PLL 1 75 DGND
DGND 2 74 DGND
AGND 3 73 DGND
ADC_VREF_N 4 72 DGND
ADC_VREF_P 5 71 MPEG_DATA_0
ADC_INCM 6 70 VDD3.3
ADC_INP 7 69 MPEG_DATA_1
ADC_INN 8 68 MPEG_DATA_2
AVDD_ADC 9 67 MPEG_DATA_3
AVDD_ADC MPEG_DATA_4
AVDD_ADC
10
11
NXT2004 66
65 DGND
AGND 12 64 VDD2.5

AGND 13 100-pin LQFP 63 VDD1.2


AGND 14 62 MPEG_DATA_5
NC 15 61 DGND
VDD1.2 16
(14 x 14 x 1.4 mm) 60 DGND
DGND 17 59 /POWER_RESET
VDD2.5 18 58 MPEG_DATA_6
DGND 19 57 DGND
AGND 20 56 MPEG_DATA_7/SER_DATA
AVDD 21 55 MPEG_DATA_EN
NC 22 54 DGND
VDD1.2 23 53 MPEG_PKT_SYNC
DGND 24 52 VDD1.2
AGND 25 51 MPEG_CLK
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RF_AGC
OSC_X TAL_ IN
O S C _ XT A L _ O U T

P DE T _ CO M P _ I N
A U X_ AGC
IF_AGC

MPEG_ERR
PDET_REF_OUT

I2C_SCL
I2C_SDA
AVDD_OSC

DGND

DGND

DGND
UC_EN
AVDD
AGND

GPIO_7
GPIO_6
OSC_CLK

VDD3.3
VDD1.2

VDD3.3
VDD1.2

VDD3.3

G_16290_085.eps
020206

Figure 9-6 Internal block diagram and pin configuration


EN 94 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.5 Diagram B3A/B/C/D, PNX 3000H (IC 7A00)

Block Diagram 1× CVBSOUTA


CVBSOUTB
2NDSIFEXT
(FMRAD)
SIFAGC CVBSOUTIF

QSS
2 SIF MIXER
SIFIN 2nd SIF internal
AMP &
AM SND
DEMOD
DTV 1st IF 2
SWITCH DTVOUT
Fpc

2
VIFIN
IF 2 VIF VIF DTV 2nd IF
2 SWITCH AMP PLL
DTVIFIN
& SNDTRAP
DTVIFAGC DTVIF &
TUNERAGC MIXER GROUP PNX3000
DTVIFPLL DELAY
VIFPLL

CVBS0 CVBS_IF
CVBS1 CVBS/Y_PRIM
CVBS2
CVBS A 10
CVBS/Y3
C3 PRIM. C D DATA 4
SWITCH DLINK1
CVBS/Y4 LINK 1
C4
VIDEO CLK
YCOMB
IDENT
CCOMB
CVBS_DTV ICLP 297 MHz
CLP_PRIM
2ndSIF
2NDSIFAGC
AGC
DET
AM sound
CVBS
OUT VCA
SWITCH A 10 DATA 4
& DLINK3
D LINK 3
CVBS CVBS_SEC
SEC.
SWITCH CLK
ICLP 297 MHz
CLP_SEC
CLP_YUV ICLP
DATA 4
ICLP A 10 DLINK2
Yyuv LINK 2
R1/PR1/V1 D
G1/Y1/Y1
RGB/YUV
B1/PB1/U1 U CLK
MATRIX
297 MHz BGDEC
& A
R2/PR2/V2 L1/AMint L A 10
SWITCH V
G2/Y2/Y2 D D VDEFLO
B2/PB2/U2
R1/AMext A 2 primary digital audio CLK VDEFLS
R VDEFL
D secondary digital audio BAND
GAP VAUDO
297 MHz REF
L2/MIC1/PipMono A L 2 VAUDS
2 DATALINK VAUD
MIC1 D
PLL RREF
MIC
AMPS
R2/MIC2/AM A R VD2V5
2 27 MHz
MIC2
D 13.5 MHz 54 MHz

MIC1 MIC2 6.75 MHz


ADC XREF
AM CLOCK DIVIDER
int 13.5 or 27 MHz
AUDIO SWITCH PLL
AUDIO SWITCH (ANALOG OUT)
(DIGITAL OUT)
CLP_PRIM HV_PRIM
TIMING
CLP_YUV
CIRCUIT
AUDIO CLP_SEC HV_SEC
AMPS

VOLTAGE
I2C-BUS
TO IRQ
INTERFACE
CURRENT

MCE430
REW
R1 R2 R3 R4 R5 DSNDL1 LINEL SCART2R ADR SCL SDA
L1 L2 L3 L4 L5 DSNDR1 LINER SCART2L
AM DSNDL2 SCART1L
EXT DSNDR2 SCART1R EWVIN EWIOUT

Pin Configuration

F_15400_131.eps
240505

Figure 9-7 Internal block diagram and pin configuration


Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 95

9.3.6 Diagram B4A/B/C/D/E/F, PNX 2015 (IC 7J00)

Block Diagram
16-BIT 225 MHz DDR

16
PNX2015
MEMORY CONTROLLER

video
NORTH TUNNEL SOUTH TUNNEL PNX8550
coprocessor

DV4
VIP
HD input
(TDA9975)
DV5
MEMORY
VO-1
BASED SCALER

VIDEO MPEG
VO-2
DECODER
HUB
12 × DACS speakers

AUDIO1 AUDIO1
DEMDEC DSP
PNX8550
PNX3000 I2D1
DV1
VIDDEC1
2D/3D
MUX DV2 PNX8550
COMB FILTER
VIDDEC2
DV3
PNX3000 I2D2

AUDIO2 AUDIO2
PNX8550
DEMDEC DSP

PNX8550 LVDS to LCD panel

TV MICROCONTROLLER SUBSYSTEM

001aab086
remote keyboard I 2 C-bus UART AV link
control

Pin Configuration
index area 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

A
B
C
D
E
F
G
H
J PNX2015
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AK
Transparent top view F_15400_132.eps
240505

Figure 9-8 Internal block diagram and pin configuration


EN 96 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.7 Diagram B5C, VIPER (IC 7V00)

Block Diagram
Streaming Interface
32-Bit 225 MHz DDR Optional External from Tunnel
Video Improvement
Processing

PNX8550
Memory 30 (dig)
DVD-CSS Controller 5-Layer
Tunnel Primary
TS Output Video Out
TS Out HD/VGA/656
Video/TS Router

10
1SD+1HD 2-Layer Analog
YUV422 Secondary DENC
3x656 20
TS Inputs Video In Video Out S-Video or
CVBS
Dual
Cond. Scaler and
Access De-interlacer
Temporal
2x Smartcard Noise Redux
2x I2S Audio Out 2x I2S
Audio In SPDIF
SPDIF
250 MHz
2D DE MIPS32
Dual SD CPU
Single HD
MPEG2
Decoder
2x 240 MHz
TM3260
Media Processor

MemoryStick/ UARTs USB1.1 GPIO PCI2.2 Flash IDE


MultiMedia Card

Pin Configuration
AK
AJ
AH
AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29
shape 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
optional (4x) E_14700_088.eps
250505

Figure 9-9 Internal block diagram and pin configuration


Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 97

9.3.8 Diagram B5F, LD3985M33 (IC 7M05/6)


Diagram B6, LD3985M33 (IC 7G42)
Diagram B7A, LD3985M33 (IC 7B25)

Block Diagram

Pin Configuration

TSOT23-5L/SOT23-5L Flip-Chip

G_16290_084.eps
020206

Figure 9-10 Internal block diagram and pin configuration


EN 98 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.9 Diagram B6, ADV7123KSTZ140 (IC 7G40)

Block Diagram
VAA

BLANK BLANK AND


SYNC SYNC LOGIC

DATA IOR
R9–R0 10 10 DAC
REGISTER IOR

DATA IOG
G9–G0 10 10 DAC
REGISTER IOG

DATA IOB
B9–B0 10 10 DAC
REGISTER IOB

POWER-DOWN VOLTAGE
PSAVE REFERENCE VREF
MODE
CIRCUIT
CLOCK
ADV7123

GND RSET COMP

Pin Configuration
PSA VE
RSET
R5

R0
R7

R2
R9

R4
R6

R1
R8

R3

48 47 46 45 44 43 42 41 40 39 38 37

G0 1 36 V
REF
PIN 1
G1 2 IDENTIFIER 35 COMP
G2 3 34 IOR
G3 4 33 IOR
G4 5 32 IOG
G5 6 ADV7123 31 IOG
TOP VIEW
G6 7 30 VAA
(Not to Scale)
G7 8 29 VAA
G8 9 28 IOB
G9 10 27 IOB
BLANK 11 26 GND
SYNC 12 25 GND

13 14 15 16 17 18 19 20 21 22 23 24
B9
B8
B7
B6
B5

CL OCK
B0

B4
B3
B2
B1
VA A

G_16290_083.eps
020206

Figure 9-11 Internal block diagram and pin configuration


Circuit Descriptions, Abbreviation List, and IC Data Sheets EP1.1U 9. EN 99

9.3.10 Diagram B7A, LD1117DT33 (IC 7B45)

Block Diagram Pin Configuration


LD1117DT

DPAK

F_15710_166.eps
230905

Figure 9-12 Internal block diagram and pin configuration

9.3.11 Diagram B8A, LM339P (IC 7D10)

Block Diagram

Pin Configuration

G_16290_082.eps
020206

Figure 9-13 Internal block diagram and pin configuration


EN 100 9. EP1.1U Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.12 Diagram B7B, TDA9975H (IC 7B50)

Block Diagram
τ ORR/V

I²C AGC τ ORB/U

REFG/Pb τ ORG/Y

B/Pb1
ADC
B/Pb2 10
B/Pb3 I²C 10/12
I²C I²C
CLAMP
BIAS I²C I²C I²C I²C I²C
BIAS
CONTROL B/Pb CHANNEL

RANGE CONTROL
VPA[11:0]

DOWNSAMPLE
REFG/Y

CONVERSION

FORMATTER

VIDEO PORT
SELECTION
I²C

COLOUR

FILTERS
G/Y1
G/Y CHANNEL

4:2:2

4:2:2
G/Y2 10 VPB[11:0]
G/Y3
10/12
I²C

REFR/Pr VPC[11:0]
I²C
R/Pr1
R/Pr CHANNEL
(GAIN)

R/Pr2 10
R/Pr3 I²C
(CLAMP)

10/12
I²C I²C

I²C +
- FREF

CLAMP VHREF TIMING I²C


+ VREF
GAIN GENERATOR -
I²C
+ HREF
I²C -
(CLKPIX) I²C
MCLK LINE TIME
MEASUREMENT (CLKFOR)

I²C (CLKOUT)
VCLK
COAST

I²C
AVI CLOCKS
SOG/Y1 PL
SOG/Y2
SYNC I²C (COAST) GENERATOR
I²C
SOG/Y3 SLICERS
I²C UPSAMPLE I²C I²C
I²C

H(C)SYNC1
τ
DETECTION

SELECTION

+ HS
ACTIVITY

H(C)SYNC2 -
SYNC

SDRS

H(C)SYNC3
I²C I²C
I²C
VSYNC1
VSYNC2
VSYNC3
τ +
- VS

VAI
I²C I²C I²C TDA9975 DEREPEATER I²C
I²C
I²C I²C

&
RXA0+ + CS
DECODER/ ALIGNEMENT

RXA0- PARALLEL -
EXTRACTION
XOR

2 8 I²C
RXB0+ RECOVERY
PACKET

I²C
RXB0- 8 I²C
2 I²C 8
RXA1+
RXA1- PARALLEL (HDMI CLOCKx2) + DE
-
RXB1+
2
RECOVERY (HDMI CLOCK)
τ I²C
RXB1- I²C
2 I²C I²C
RXA2+
RXA2- PARALLEL
2
RXB2+
RXB2-
RECOVERY τ CTL[3:0]
2 (CTL3) I²C 4
I²C
FORMATTER

RXAC+ AP[3:0]
RXAC-
HDCP AUDIO FIFO
AUDIO

2 I²C
RXBC+
RXBC- I²C
CIPHER I²C WS
2 I²C SERIAL AUDIO PLL
INTERFACE ACLK
MEMORY
FRO I²C I²C
I²C
TERMINATION SERIAL POWER
OE
RESISTANCE HDMI RECEIVER I²C I²C INTERFACE MANAGEMENT
CONTROL I²C
HSDAA

HSDAB

HSCLA

HSCLB

SDA

DIS
SCL

A0
RRXA

RRXB

PD

Pin Configuration

F_15400_135.eps
240505

Figure 9-14 Internal block diagram and pin configuration


Spare Parts List EP1.1U 10. EN 101

10. Spare Parts List


Not available at the time of writing. As soon as they become
available, a Service Info or Service Manual update will be
issued via the appropriate channels.

11. Revision List


Manual xxxx xxx xxxx.0
• First release.

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