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L1 S1 M1 D1

Data path A
Register file A Register file B
D2
Data path B
S2 M2 L2
L1 data memory controller
Cache control
Memory protection
Interrupt
and exception
controller
Power control
Instruction decode
16/32bit instruction dispatch
Instruction fetch
SPLOOP buffer
C64x+ CPU
IDMA
Bandwidth management
Cache control
L1 program memory controller Advanced
event
triggering
(AET)
L2 memory
controller
Bandwidth
management
Memory
protection
registers
Configuration
L1P
cache/SRAM
L1D
cache/SRAM
PLL2
DDR2 memory
EMIFA
Other
peripherals
EDMA
Boot
configuration
S
w
i
t
c
h
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d

c
e
n
t
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l

r
e
s
o
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r
c
e
PLL2
L
2

m
e
m
o
r
y
controller
controller
memory
External
controller
DMA
Master
DMA
Slave
Cache
control
Bandwidth management
Memory protection

AED[15:0]
ABA[1:0]
ABE[1:0]
ASDWE
AEA[23:0]
Internal
configuration
bus
EMIF
Control
registers
Shared by all
interfaces
AECLKIN
EDMA bus
AARDY
AECLKOUT
Asynchronous ready input
ARNW
AOE
ACE[3:2]
ASADS
Asynchronous/synchronous
interface
MUXed asynchronous/
synchronous memory
write enable

AED[15:8] AED[7:0]
EMIF
16bit device
8bit device

GND or 0
ACEn
AOE
AEA[N:0]
AED[7:0]
ABA[1:0]
AARDY
(A)
CS
OE
A[N:2]
D[7:0]
EMIF ROM
A[1:0]

GND or 0
ACEn
AOE
AEA[N:0]
AED[15:0]
ABA1
AARDY
(A)
CS
OE
A[N:1]
D[15:0]
EMIF ROM
A0

Setup Strobe Hold


AECLKOUT
Byte enables
Address
Read data
ACE
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
2 3 1
AARDY
(A)
Disabled state

AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
AARDY
(A)
Byte enables
Address
Write data
Disabled state
Setup
Strobe
Hold
2
3
1

Byte enables
Address
Write data
AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
AARDY
Setup
Strobe
Strobe
Hold 1
1
1
1 Strobe
2

Byte enables
Address
AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
AARDY
Setup
Strobe
Strobe
Hold
Rd data
1
1
1
1
Strobe
2

AECLKOUT
ACEn
AEA[23:0]/
ABA[1:0]
ASDWE
AOE
ARNW
ABE[1:0]
AED[15:0]
AARDY
(A)
Disabled state
Address
Byte enables
Write data
Setup
Strobe
Hold
2
4
3
Setup
Strobe
Hold
AECLKOUT
ACE[n]
AEA[23:0]/
ABA[1:0]
ASDWE
AOE
ARNW
ABE[1:0]
AED[15:0]
AARDY
(A)
Address
Disabled state
2
4
3
Byte enables
Read data

Address
AECLKOUT
ACEn
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
AARDY
Setup
Strobe
Strobe
Hold
ABE[1:0]
Write data
Bytewrite strobe
1
1
1
1 Strobe
2

Address
AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
AOE
ASDWE
ARNW
AARDY
Rd data
Setup
Strobe
Strobe
Hold 1
1
1
1
Strobe
2

0
1
1
AECLKOUT
ACEn
(A)
ASDWE
ABE0n
(B)
AOE
ASADS
AEA[N:0]/ABA[1:0]
(C)
AED[N:0]
(B)
CLK
CE
CS1
ADV
BWE
BW[N:0]
OE
ADSC
A[N:0]
D[N:0]
EMIF SBSRAM
1 CS0
ADSP
1 GW

RL = 2
Read/D4
latched
Read/D3
latched
D5
latched
BE1 BE2 BE3
D1 D2 D3
AECLKOUT
ACEn
ABE[1:0]
(A)
AEA[23:0]/
ABA[1:0]
AED[15:0]
ASADS
AOE
ASDWE
BE4 BE5 BE6
A2 A1 A3 A4 A5 A6
D4 D5 D6
Read Read
Read/D1
latched
D6 latched/
deselect
Read/D2
latched

BE1 BE2 BE3


D1 D2 D3
AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
ASADS
AOE
ASDWE
BE4 BE5 BE6
A2 A1 A3 A4 A5 A6
D4 D5 D6
WL = 0
Write Write Write Write Write Deselect Write

0
1
0
AECLKOUT
ACEn
(A)
ASDWE
ABE[N:0]
(B)
AOE
ASADS
AEA[N:0]/ABA[1:0]
(C)
AED[N:0]
(B)
CLK
CEN
CE1
CE2
CE2
ARNW
BW[N:0]
OE
ADV/LD
A[N:0]
D[N:0]
EMIF ZBT SRAM

BE1 BE2 BE3


D1 D2 D3
AECLKOUT
ACEn
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
ASADS
AOE
ASDWE
BE4 BE5 BE6
A2 A1 A3 A4 A5 A6
D4 D5 D6
Write Write Write Write Write Write Deselect
WL = 2

OE
RCLK
REN
WCLK
WEN
FIFO
Synchronous
Q[31:0]
FF
EF
HF
D[n:0]
(B)
EXT_INTy
(A)
D[31:0]
WEN
WCLK
FIFO
Synchronous
Q[n:0]
(B)
HF
FF
EF
OE
REN
RCLK
AED[15:0]
EXT_INTx
(A)
AOE
ASADS
ACEn
AECLKOUT
EMIF
n

BE1 BE2 BE3


D1 D2 D3
AECLKOUT
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
ASADS
AOE
ASDWE
BE4 BE5 BE6
A2
A1
A3 A4 A5 A6
D4 D5 D6
Read Read Read Read Read Read
RL = 1
ACEn
(CS_EXT=0)
(CS_EXT=1)
ACEn

AECLKOUT
BE1 BE2 BE3
D1 D2 D3
ABE[1:0]
AEA[23:0]/
ABA[1:0]
AED[15:0]
ASADS
AOE
ASDWE
BE4 BE5 BE6
A2 A1 A3 A4 A5 A6
D4 D5 D6
ACEn
Write Write Write Write Write Write
WL = 0

Command/data
scheduler
Command
to memory
Command FIFO
Write FIFO
Read FIFO
Registers
EDMA
bus
Write data
to memory
Read data
from memory
Command
Data