LAB2

Verilog structural & dataflow review Verilog behavior model 4-bit comparator Simple Security System

reviewstructural model
module FA_4bit(a,b,cin,sum,cout); input [3:0] a,b; input cin; output [3:0] sum; output cout; wire [2:0] c;

FA_1bit fa3( .a(a[3]), .b(b[3]), .cin(c[2]), .s(sum[3]), .cout(cout) ); FA_1bit fa2( .a(a[2]), .b(b[2]), .cin(c[1]), .s(sum[2]), .cout(c[2]) ); FA_1bit fa1( .a(a[1]), .b(b[1]), .cin(c[0]), .s(sum[1]), .cout(c[1]) ); FA_1bit fa0( .a(a[0]), .b(b[0]), .cin(cin), .s(sum[0]), .cout(c[0]) );
endmodule

reviewdataflow model
assign output = using opeartor data representation 4b0010 8hF1 10d1023 8dz {1,2}

behavior model
C For example
module mux_4to1(Dout, D0,D1,D2,D3,select); input [7:0] D0,D1,D2,D3; input [1:0] select; output [7:0] Dout; assign Dout = (select==2b00) ? D0 : (select==2b01) ? D1 : (select==2b10) ? D2 : (select==2b11) ? D3 : 8dz; endmodule module mux_4to1(Dout, D0,D1,D2,D3,select); input [7:0] D0,D1,D2,D3; input [1:0] select; output [7:0] Dout; reg [7:0] Dout; always@(*) begin case(select) 2b00: Dout=D0; 2b01: Dout=D1; 2b10: Dout=D2; 2b11: Dout=D3; endcase end endmodule

behavior model
For exampleif-else
module mux_4to1(Dout, D0,D1,D2,D3,select); input [7:0] D0,D1,D2,D3; input [1:0] select; output [7:0] Dout; reg [7:0] Dout; always@(*) begin if(select==2b00) Dout=D0; else if(select==2b01) Dout=D1; else if(select==2b10) Dout=D2; else Dout=D3; end endmodule

Comparators
Combinational Design

Equality Comparator
XNOR X Y X 0 0 1 1 Y 0 1 0 1 Z 1 0 0 1

Z = !(X $ Y)

4-Bit Equality Comparator

A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

FIELD A = [A0..3]; FIELD B = [B0..3]; FIELD C = [C0..3];

4-bit Equality Detector

A[3..0] B[3..0]

Equality Detector

A_EQ_B

4-bit Magnitude Comparator

A_LT_B A_EQ_B
A_GT_B

A[3..0] B[3..0]

Magnitude Detector

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

How can we find A_GT_B?

How many rows would a truth table have?

28 = 256!

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

Find A_GT_B

If A = 1001 and B = 0111 is A > B? Why?

Because A3 > B3 i.e. A3 & !B3 = 1

Therefore, one term in the logic equation for A_GT_B is A3 & !B3

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

A_GT_B = A3 & !B3 + ..

If A = 1101 and B = 1011 is A > B? Why?

Because A3 = B3 and A2 > B2 i.e. C3 = 1 and A2 & !B2 = 1 Therefore, the next term in the logic equation for A_GT_B is C3 & A2 & !B2

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

A_GT_B = A3 & !B3 + C3 & A2 & !B2 + .. Because A3 = B3 and A2 = B2 and A1 > B1 i.e. C3 = 1 and C2 = 1 and A1 & !B1 = 1

If A = 1010 and B = 1001 is A > B? Why?

Therefore, the next term in the logic equation for A_GT_B is C3 & C2 & A1 & !B1

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

A_GT_B = A3 & !B3 + C3 & A2 & !B2 + C3 & C2 & A1 & !B1 + .. Because A3 = B3 and A2 = B2 and A1 = B1 and A0 > B0 i.e. C3 = 1 and C2 = 1 and C1 = 1 and A0 & !B0 = 1 Therefore, the last term in the logic equation for A_GT_B is C3 & C2 & C1 & A0 & !B0

If A = 1011 and B = 1010 is A > B? Why?

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

A_GT_B = A3 & !B3 + C3 & A2 & !B2 + C3 & C2 & A1 & !B1 + C3 & C2 & C1 & A0 & !B0

Magnitude Comparator
A0 B0 A1 B1 A2 B2 A3 B3 C3 C2 C1 A_EQ_B C0

Find A_LT_B

A_LT_B = !A3 & B3 + C3 & !A2 & B2 + C3 & C2 & !A1 & B1 + C3 & C2 & C1 & !A0 & B0

1-Bit Magnitude Comparator

x y

Gout Eout Lout

1 -bit comparator

Gin Lin

The variable Eout is 1 if A = B and Gin = 0 and Lin = 0. The variable Gout is 1 if A > B or if A = B and Gin = 1. The variable Lout is 1 if A < B or if A = B and Lin = 1.

4-Bit Magnitude Comparator

x3 y3 x2 y2 x1 y1 x0 y0 gt eq lt G4 1-bit comp L4 L3 G3 1-bit comp L2 G2 1-bit comp L1 G1 1-bit comp L0 G0 Gin=0 Lin=0

X 1101 1110 1011 0101 1010

Y 0110 1011 1011 0111 1011

gt = 1

eq = 1 lt = 1