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<=
<=
<=
<=
'0';
sA(3);
sB(3);
D(0);
end Behavioral;
Cto.vhd
------------------------------------------------------------------entity Cto is
Port ( I : in STD_LOGIC_VECTOR (3 downto 0);
Z : out STD_LOGIC_VECTOR (3 downto 0));
end Cto;
architecture Behavioral of Cto is
begin
With I Select
Z <= "0000" when
"0001" when
"0010" when
"0011" when
"0100" when
"1000" when
"1001" when
"1010" when
"1011" when
"1100" when
"0000" when
end Behavioral;
"0000",
"0001",
"0010",
"0011",
"0100",
"0101",
"0110",
"0111",
"1000",
"1001",
others;
S2 = 0
S2 = 1
2. (40%) Disee una ALU para palabras de 4bits que realice las siguientes funciones
indicadas en la tabla con las siguientes caractersticas:
Realice en diseo con sumadores completos.
a. Con un circuito para B que dependa slo de S1 y S0 (sin S2), mostrando su funcin
b. Con un circuito para A, mostrando su funcin.
c. Muestre cmo sera la conexin total del diseo.
d. Implemente con cdigo Vhdl pensado en su circuito.
Las dos primeras instrucciones aritmticas son de incremento A + 1 (no es A+F).
S1
0
0
1
1
S0
0
1
0
1
Aritmticas
A+1
B+1
A+B
A-B
S1
0
0
1
1
S0
0
1
0
1
Lgicas
not(A)
not(B)
A or B
A and B
W X Y Z
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
F
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
"00",
"01",
"10",
when others;
Ayudas
Condicionales
------------------------------------------------------------------s_name <= value1 when boolean-expr1 else
value2 when boolean-expr2 else
value3 when boolean-expr3 else
...
value_n;
------------------------------------------------------------------with selector select
signal-name <= value-1
value-2
value-3
...
value-n
when choice-1 ,
when choice-2,
when choice-3,
when choice-n;
------------------------------------------------------------------process(sensitivity-list)
begin
if boolean-expr-1 then
s-statements;
elsif boolean-expr-2 then
s-statements ;
elsif boolean-expr-3 then
s-statements;
...
else
sequential
end if;
end process;
------------------------------------------------------------------process(sensitivity-list)
begin
case case-expression is
when choice-1 =>
sequential statements;
when choice-2 =>
sequential statements;
...
when choice-n =>
sequential statements;
end case;
end process;
-------------------------------------------------------------------