2/24/2014

EEC-553 CAD OF ELECTRONICS LAB FILE

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EEC-553 CAD OF ELECTRONICS LAB FILE

Ratings: (0) | Views: 226 | Likes: 0 Published by Shitansh Nigam UPTU/GBTU/MMTU Electronics and Communication 3rd year CAD lab File See More

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INDEX

S.NO
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

EXPERIMENT NAME

Transient analysis and simulation of CMOS inverter. Transient and simulation analysis of NAND gate Transient and simulation analysis of CMOS nor gate.
. .

Transient analysis and simulation of NMOS inverter. . Transient analysis and simulation of BJT inverter. Design of 4:1 multiplexer using with statement. Design of 4:1 multiplexer using when stat ement.

Design of 4:1 multiplexer using case statement.

Design D flipflop with reset using VHDL.

Design full adder using half adder for structural modelling. Design of 4-bit ripple carry adder using full adder as a component for structural modelling.

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EXPERIMENT 01
- Transient analysis and simulation of CMOS inverter. Object - orcade Lite-9.1. Software used

- CMOS inverters (Complementary NOSFET Inverters) are some of the most widely Theory used and adaptable MOSFET inverters used in chip design. They operate with very little power loss and at relatively high speed.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals.(See diagram) The circuit below is the simplest CMOS logic gate.

When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting (switch closed) while the bottom transistor behaves like an open circuit. Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage (5 V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed) while the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V). The function of this gate can be summarized by the following table: Input Output High Low Low High

The output is the opposite of the input - this gate inverts the input.

Notice that always one of the transistors will be an open circuit and no current flows http://www.scribd.com/doc/133115703/EEC-553-CAD-OF-ELECTRONICS-LAB-FILE

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Notice that always one of the transistors will be an open circuit and no current flows from the supply voltage to ground.

Fig: Transistor "switch model

The switch model of the MOSFET transistor is defined as follows:
MOSFET Condition MOSFET State of MOSFET

NMOS NMOS PMOS PMOS

Vgs<Vtn Vgs>Vtn Vsg<Vtp Vsg>Vtp

OFF ON OFF ON

When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic low.

Procedure

M_M1 V_V1 M_M2

Open the blank project in orcade family release 9.1. Include library:-ANALOG, BIPOLAR, PWRMOS, SOURCE, TRANSISTOR .Draw the circuit. Go to pspice and open new simulation profile. Perform transient analysis. Create net list and then run. Then we obtain final waveform.
N00263 N00282 0 0 M2N6659 N00385 0 5Vdc N00263 N00282 N00385 N00385 M2N6806

Net list description

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V_V2 +PULSE N00282 0 0 5 0 0 0 50ns 100ns

EEC-553 CAD OF ELECTRONICS LAB FILE

Circuit diagram-

Output waveform

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EXPERIMENT 02
. -Transient and simulation analysis of NAND gate Object - Orcade lite-9.1. Software used

Theory The circuit below has two inputs and one output. Whenever at least one of the inputs is low, the corresponding P-type transistor will be conducting while the N-type transistor will be closed. Consequently, the output voltage will be high. Conversely, if both inputs are high, then both P-type transistors at the top will be open circuits and both N-type transistors will be conducting. Hence, the output voltage is low. The function of this gate can be summarized by the following table:
V1 Low V2 Low Output High High High Low

Low High High Low High High

If logical 1's are associated with high voltages then the function of this gate is called NAND for negated AND .
. Again, there is never a conducting path from the supply voltage to ground

FIG 1: CMOS NAND GATE

CIRCUIT DIGGRAM:

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