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A

Compal Confidential
2

PAWGE Schematics Document


AMD APU Zacate-FT1 + FCH Hudson-M3L + GPU RobsonXT

2011-11-21

REV:1.0

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Cover Page
Size
B
Date:

Document Number

Rev
1.0

LA8681P
Tuesday, November 29, 2011

Sheet
E

of

48

QIWG5

Compal confidential

LS7981P CardReader/B
LS7982P USB/B
LS7983P PWR/B

File Name : PAWGE

QIWG6

LVDS Conn.

Memory BUS(DDRIII) 200pin DDRII-SO-DIMM X2

page 22

AMD Brazos APU


CRT Conn.
HDMI Conn.
page 23

page 8,9

BANK 0, 1, 2, 3

1.5V DDRIII 1333

FT1
BGA 413-Ball
19mm x 19mm

page 24

AMDRosbon XT_M2

Single Channel

LS7981P CardReader/B
LS7982P USB/B
LS7983P PWR/B
LS7984P LED/B
LS7985P ODD/B

page 5,6,7

VRAM 64*16
DDR3*4

x4 PCI-E GPP GEN2


x4 UMI Gen. 2

page 15 ~ 21

2Channel Speaker

page 27

Hudson M3L

AZALIA

page 27

page 10,11,12,13,14

page 29

GIGA LAN
RTL8111/8105

Audio Jacks
Stereo
HeadPhone Output
Microphone Input

10*USB2.0

4 * x1 PCI-E 1.0

page 27

CX20671

BGA 656-Ball
23mm x 23mm

WLAN &WiMax

Internal MIC

Audio Codec

2*SATA serial

LPC BUS

CMOS Camera page 22


BlueTooth CONN page 28
USB PORT 2.0 x2(Left)

USB PORT 3.0 x2(Right)

page 33

page 34

page 25,26

SPI ROM

PCI Express
Mini card Slot 1

WLAN/WiMAX

EC

page 11

ENE KB9012

Card Reader

page 30

USB(WiMAX)

Realtek RTS5178
SD/MMC
Daoughter board

PCI-E(WLAN)

WLAN/WiMAX page 29

Int.KBD
page 32

Touch Pad
page 32

SATA3.0 HDD CONN


page 28
Thermal Sensor
SATA ODD CONN
page 28

EMC1403 page 29

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Block Diagrams
Size
B
Date:

Document Number

Rev
1.0

LA8681P
Tuesday, November 29, 2011

Sheet
E

of

48

Voltage Rails

Power Plane

Description

S1

VIN

Adapter power supply (19V)

N/A

B+

AC or battery power rail for power circuit.

N/A

S5

FCH Hudson-M3L
USB Port List

N/A

N/A

USB1.1

N/A

N/A

S3

+APU_CORE

Core voltage for CPU (0.7-1.2V)

ON

OFF

OFF

+APU_CORE_NB

1.0V switched power rail

ON

OFF

OFF

+1.5V

1.5V power rail for CPU VDDIO and DDRIII

ON

ON

OFF

+0.75VS

0.75VS switched power rail for DDR terminator

ON

OFF

OFF

+1.0VS

1.0V switched power rail for NB VDDC & VGA

ON

OFF

OFF

+1.1VS

1.1VS switched power rail

ON

OFF

OFF

+1.8VS

1.8V switched power rail

ON

OFF

OFF

+3VALW

3.3V always on power rail

ON

ON

ON*

+3V_LAN

3.3V power rail for LAN

ON ON(WOL)

+3VS

3.3V switched power rail

ON

OFF

OFF

+5VALW

5V always on power rail

ON

ON

ON*

OFF

+5VS

5V switched power rail

ON

OFF

OFF

+VSB

VSB always on power rail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

+1.1VALW

1.1V always on power rail

ON

ON

ON*

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

EC SM Bus1 address

EC SM Bus2 address

Device

Address

HEX

Smart Battery

0001-011xb

15H

SM Bus Controller 0
Device

Address

HEX

1111-100xb

F8H

EMC1403-2(DDR,WLAN)

1001-101xb

9AH

SB-TSI

1001-100xb

98H

Brazos
PCIE Port List

NC

Port1

NC

PCIE1
PCIE2
PCIE3

Device

HEX

1001-000xb

90

DDR DIMM2 (FCH_SMB0)

1001-001xb

92

ODD

SATA2

NC

SATA3

NC

Right USB

PCIE0

LAN

SATA4

NC

Right USB

PCIE1

WLAN

SATA5

NC

Port2

Mini-PCIE

PCIE2

NC

Port3

USB Camera

PCIE3

NC

Port4

NC

Port5

CardReader

Port6

BT

Port7

NC

Port8

NC

Port9

NC

Port11

BOM Structure

Left USB1
Left USB2

Port12

NC

Port13

NC

UMA@ : UMA only


PX@
: DIS muxluss PX 4.0
Robson@ : Robson GPU
GIGA@ : RTL8111 1000
8105@ : RTL8105 10/100
DIMM@ : DIMM select
CMOS@ : USB camera
BT@
: BT function
ME@
: ME components
X76@, H1G@, H512@, S1G@, S512@
45@
: 45 Level
HDMI@
: HDMI function
non HDMI@
: HDMI function

: VRAM

AN@
: Apple + Nokia ear phone combo
A@
: Apple ear phone
PCB@
: PCB PN
14@
: 14"
15@
: 15"
BBH@
: BBH
nonBBH@@
: nonBBH@

(FCH_SMB0)

Address

SATA1

Port1

HEX

DDR DIMM1 (FCH_SMB0)

HDD

Port0

H_THERMTRIP# (FCH_ALERT#)

SM Bus Controller 1

SATA0

USB2.0

APU SIC/SID (FCH_SMB3)

FCH Hudson-M3L
SATA Port List

GPU
PCIE x4

(FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#)

Address

PCIE0

Port0

Port10

EMC1412-2 (dGPU)

Device

APU

FCH

WLAN (FCH_SMB0)

2010/06/30

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Notes List
Size
B
Date:

Document Number

Rev
1.0

LA8681P
Tuesday, November 29, 2011

Sheet
E

of

48

Power-Up/Down Sequence

BACO option :

2. VDDR3 should ramp-up before or simultaneously with VDDC.

PXS_RST# : High ->Normal operation (dGPU is not reset on BACO mode)


PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)

VDDR3(3.3VGS)

Note: Do not drive any IOs before VDDR3 is ramped up.

PCIE_VDDC(1.0V)
C

PXS_RST# : Low -> Reset dGPU ; High ->Normal operation


PXS_PWREN : Low -> dGPU Power OFF ; High -> dGPU Power ON

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.

Without BACO option :

VDDR1(1.5VGS)

dGPU Power Pins

Voltage

PX 3.0

BACO Mode Max current

PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,


DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18

1.8V

OFF

ON

1679mA

DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and


SPV10

1.0V

OFF

ON

575mA

PCIE_VDDC

1.0V

OFF

ON

2A

VDDR3 , and A2VDD

3.3V

OFF

ON

190mA

BIF_VDDC (current consumption = 55mA@1.0V, in


BACO mode)
BIF_VDDC=VGA_CORE When GPU enable
BIF_VDDC=1.0V
When BACO

Same as
VDDC

OFF

ON
Same as
PCIE_VDDC

70mA

VDDR1

1.5V

OFF

OFF

2.8A

VDDC/VDDCI

1.12V

OFF

OFF

12.9A

VDDC/VDDCI(1.12V)
VDD_CT(1.8V)

iGPU

PXS_RST#

PE_EN

dGPU

PERSTb

BACO Switch

BIF_VDDC
PXS_PWREN

REFCLK

PX_mode

+3.3VALW

Straps Reset

+1.0V

Straps Valid

MOS

Regulator

+3.3VGS

1
+1.0VGS

+1.5V

+1.5VGS

SI4800

Regulator

Global ASIC Reset


+1.8V

SI4800

T4+16clock

+B

+1.8VGS

+VGA_CORE

PWRGOOD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2010/06/30

Deciphered Date

2012/07/14

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

dGPU Block Diagram


Size
B
Date:

Document Number

Rev
1.0

LA8681P
Tuesday, November 29, 2011

Sheet
1

of

48

PCB@

AAAU22

PCB 0R3 LA-8681P REV0 M/B

E1200@

BBBU22

EM1200GBB22GV

EM1800GBB22GV

R400 1

2 1K_0402_5%

APU_SVD

R405 2

1 300_0402_5%

APU_RST#

R401 2

1 300_0402_5%

APU_PWRGD

R402 1

2 510_0402_1%

TEST_25_L

R403 1

2 1K_0402_5%

TEST36

<23> HDMI_TX1P
<23> HDMI_TX1N
<23> HDMI_TX0P
<23> HDMI_TX0N
<23> HDMI_CLKP
<23> HDMI_CLKN

+3VS

R510 1

2 4.7K_0402_5%

EDID_CLK

R511 1

2 4.7K_0402_5%

EDID_DATA

R410 1

2 1K_0402_5%

APU_PROCHOT#

R411 1

2 1K_0402_5%

APU_ALERT#_R

TO EC

B9
A9

TDP1_TXP1
TDP1_TXN1

HDMI_TX0P_C
HDMI_TX0N_C

D10
C10

TDP1_TXP2
TDP1_TXN2

HDMI_CLKP_C
HDMI_CLKN_C

A10
B10

TDP1_TXP3
TDP1_TXN3

<22> LVDS_A2
<22> LVDS_A2#

B5
A5

LTDP0_TXP0
LTDP0_TXN0

<22> LVDS_A1
<22> LVDS_A1#

D6
C6

LTDP0_TXP1
LTDP0_TXN1

<22> LVDS_A0
<22> LVDS_A0#

A6
B6

<22> LVDS_ACLK
<22> LVDS_ACLK#

D8
C8

<10> APU_CLK
<10> APU_CLK#

V2
V1

<10,44> APU_PWRGD
@ C1022
100P_0402_50V8J

LTDP0_TXP3
LTDP0_TXN3
CLKIN_H
CLKIN_L

<10> APU_DISP_CLK
<10> APU_DISP_CLK#

D2
D1

<44> APU_SVC
<44> APU_SVD

J1
J2

SVC
SVD

P3
P4

SIC
SID

<16,29,30> EC_SMB_CK2
<16,29,30> EC_SMB_DA2

R809 1
R810 1

2 0_0402_5%
2 0_0402_5%

EC_SMB_CK2_R
EC_SMB_DA2_R

T3
T4

<10> APU_RST#

LTDP0_TXP2
LTDP0_TXN2

1
<10,30,37> H_PROCHOT#

R808 1

2 0_0402_5%

APU_PROCHOT#
U1
APU_THERMTRIP# U2
APU_ALERT#_R
T2

APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#

DP MISC

APU_SVC

VGA DAC

2 1K_0402_5%

DISP_CLKIN_H
DISP_CLKIN_L

RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L

N2
N1
P1
P2
M4
M3
M1

TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L

F4
G1
F3

VDDCR_NB_SENSE
VDDCR_CPU_SENSE
VDDIO_MEM_S_SENSE

<44> APU_VDDNB_RUN_FB_H
<44> APU_VDD0_RUN_FB_H
T77PAD

F1

<44> APU_VDD0_RUN_FB_L

B4
W11
V5
+3VS

DP_ZVSS

R398 1

2 150_0402_1%

DP_ZVSS

H3

DP_BLON
DP_DIGON
DP_VARY_BL

G2
H2
H1

APU_ENBKL <22>
APU_ENVDD <22>
APU_BLPWM <22>

TDP1_AUXP
TDP1_AUXN

B2
C2

HDMI_CLK <23>
HDMI_DATA <23>

TDP1_HPD

C1

LTDP0_AUXP
LTDP0_AUXN

A3
B3

LTDP0_HPD

D3

DAC_RED
DAC_REDB
DAC_GREEN
DAC_GREENB
DAC_BLUE
DAC_BLUEB
DAC_HSYNC
DAC_VSYNC

HDMI_DET <23>
EDID_CLK
EDID_DATA
LTDP0_HPD

C12
D13
A12
B12
A13
B13

EDID_CLK <22>
EDID_DATA <22>
R406 1

2 100K_0402_5%

R407 1

2 150_0402_1%

R408 1

2 150_0402_1%

R409 1

2 150_0402_1%

DAC_RED <24>
DAC_GRN <24>
DAC_BLU <24>

E1
E2

CRT_HSYNC <24>
CRT_VSYNC <24>

DAC_SCL
DAC_SDA

F2
D4

DAC_ZVSS

D12

TEST4
TEST5
TEST6
TEST14
TEST15
TEST16
TEST17
TEST18
TEST19
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST31
TEST33_H
TEST33_L
TEST34_H
TEST34_L
TEST35
TEST36
TEST37

TEST

R399 1

TDP1_TXP0
TDP1_TXN0

HDMI_TX1P_C
HDMI_TX1N_C

DISPLAYPORT 0

APU_DBREQ#

CLK

2 1K_0402_5%

A8
B8

SER

R404 1

HDMI_TX2P_C
HDMI_TX2N_C

CTRL

C508 1 HDMI@
0.1U_0402_16V7K
2
C509 1
0.1U_0402_16V7K
2
HDMI@
C510 1 HDMI@
0.1U_0402_16V7K
2
C511 1
0.1U_0402_16V7K
2
HDMI@
C512 1 HDMI@
0.1U_0402_16V7K
2
C513 1
0.1U_0402_16V7K
2
HDMI@
C514 1 HDMI@
0.1U_0402_16V7K
2
C515 1
0.1U_0402_16V7K
2
HDMI@

<23> HDMI_TX2P
<23> HDMI_TX2N

DISPLAYPORT 1

U22B

+1.8VS

E1800@

JTAG

AAAU6

R1
R2
R6
T5
E4
K4
L1
L2
M2
K1
K2
L5
M5
M21
J18
J19
U15
T15
H4
N5
R5

CRT_DDC_CLK <24>
CRT_DDC_DATA <24>
DAC_ZVSS

R413 1

2 499_0402_1%

PAD T66
PAD T67

AMD check list update


20101110

PAD T68

TEST15

R415 1
@
2 1K_0402_5%
PAD T69
PAD T95
TEST18
R416 1
2 1K_0402_5%
TEST19
R417 1
2 1K_0402_5%
TEST25_H
R419 1
2 510_0402_1%
TEST_25_L
TEST28_H
PAD T71
TEST28_L
PAD T72
TEST31
PAD T73
TEST33_H
C516 1
R420 1
2 0.1U_0402_16V4Z
TEST33_L
C517 1
R421 1
2 0.1U_0402_16V4Z
Delete Test point for layout limitation
20100818
non HDMI@
TEST35
R422 1
2 1K_0402_5%
TEST36
TEST37
R958 1 HDMI@ 2 1K_0402_5%
PAD T76
+1.8VS

2 51_0402_1%
2 51_0402_1%

HDMI function enable R958 mount


disable R422 mount

VSS_SENSE
TEST38
DMAACTIVE_L

RSVD_1
RSVD_2
RSVD_3

K3
T1

ALLOW_STOP# <10>
R423 1

2 1K_0402_5%

+1.8VS

S IC E SERIES EME450GBB22GVA 1.65G BGA

2
E

APU_THERMTRIP#

Q79
1

+1.8VS

+1.8VS

H_THERMTRIP# <12>

MMBT3904_NL_SOT23-3

JHDT1
1

APU_TCK

R843 2

1 1K_0402_5%

APU_TMS

R844 2

1 1K_0402_5%

APU_TDI

R845 2

1 1K_0402_5%

APU_TDO

10

10

APU_PWRGD

11

12

12

APU_RST#

13

14

14

APU_DBRDY

15

16

16

APU_DBREQ#

17

18

18

J108_PLLTST0

R851 1 @

2 0_0402_5%

TEST19

19

20

20

J108_PLLTST1

R852 1 @

2 0_0402_5%

TEST18

R842

2
0_0402_5%

If FCH internal pull-up disabled, level-shifter could be deleted.


Need BIOS to disable internal pull-up!!

1K_0402_5%

1
1
R427 @

AMD Debug
check the connect need or not

+1.8VS

1K_0402_5%

R424
10K_0402_5%

R425

need to pop for HDT debug


20101012
@

APU_TRST#

R846 1

20_0402_5% APU_TRST#_R

R847 2 @

1 10K_0402_5%

11

R848 2 @

1 10K_0402_5%

13

R849 2 @

1 10K_0402_5%

15

17
19

Please be noted about TEST_18 and TEST_19


SAMTE_ASP-136446-07-B
@

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

Title

Compal Electronics, Inc.


FT1 CTRL/DP/CRT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

need to pop for HDT debug


20101012

Size Document Number


Custom
Date:

Rev
1.0

LA8681P

Wednesday, November 30, 2011

Sheet
1

of

48

U22E

<8,9> DDR_A_DQS0
<8,9> DDR_A_DQS#0
<8,9> DDR_A_DQS1
<8,9> DDR_A_DQS#1
<8,9> DDR_A_DQS2
<8,9> DDR_A_DQS#2
<8,9> DDR_A_DQS3
<8,9> DDR_A_DQS#3
<8,9> DDR_A_DQS4
<8,9> DDR_A_DQS#4
<8,9> DDR_A_DQS5
<8,9> DDR_A_DQS#5
<8,9> DDR_A_DQS6
<8,9> DDR_A_DQS#6
<8,9> DDR_A_DQS7
<8,9> DDR_A_DQS#7
<8>
<8>
<8>
<8>
<9>
<9>
<9>
<9>

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

<8>
<8>
<9>
<9>

DDR_A_DQS0
DDR_A_DQS#0
DDR_A_DQS1
DDR_A_DQS#1
DDR_A_DQS2
DDR_A_DQS#2
DDR_A_DQS3
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS#4
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS6
DDR_A_DQS#6
DDR_A_DQS7
DDR_A_DQS#7

A16
B16
B20
A20
E23
E22
J22
J23
R22
P22
W22
V22
AC20
AC21
AB16
AC16

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK3
DDR_B_CLK#3

M17
M16
M19
M18
N18
N19
L18
L17

DDR_CKE0
DDR_CKE1

<8,9> DDR_CKE0
<8,9> DDR_CKE1

D15
B19
D21
H22
P23
V23
AB20
AA16

DDR_RST#
DDR_EVENT#

<8,9> DDR_RST#
<8,9> DDR_EVENT#

<8>
<8>
<9>
<9>

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

F15
E15

DDR_A_ODT0
DDR_A_ODT1
DDR_B_ODT0
DDR_B_ODT1

W19
V15
U19
W15

DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
DDR_CS0_DIMMB#
DDR_CS1_DIMMB#

T17
W16
U17
V16

DDR_A_RAS#
DDR_A_CAS#
DDR_A_WE#

<8,9> DDR_A_RAS#
<8,9> DDR_A_CAS#
<8,9> DDR_A_WE#

L23
N17

U18
V19
V17

M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15

DDR SYSTEM MEMORY

R18
T18
F16

<8,9> DDR_A_BS0
<8,9> DDR_A_BS1
<8,9> DDR_A_BS2

M_ADD0
M_ADD1
M_ADD2
M_ADD3
M_ADD4
M_ADD5
M_ADD6
M_ADD7
M_ADD8
M_ADD9
M_ADD10
M_ADD11
M_ADD12
M_ADD13
M_ADD14
M_ADD15
M_BANK0
M_BANK1
M_BANK2
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DQS_H0
M_DQS_L0
M_DQS_H1
M_DQS_L1
M_DQS_H2
M_DQS_L2
M_DQS_H3
M_DQS_L3
M_DQS_H4
M_DQS_L4
M_DQS_H5
M_DQS_L5
M_DQS_H6
M_DQS_L6
M_DQS_H7
M_DQS_L7

M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39

M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55

M_RESET_L
M_EVENT_L
M_CKE0
M_CKE1

M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63

M0_ODT0
M0_ODT1
M1_ODT0
M1_ODT1
M0_CS_L0
M0_CS_L1
M1_CS_L0
M1_CS_L1

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7

C18
A19
B21
D20
A18
B18
A21
C20

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15

C23
D23
F23
F22
C22
D22
F20
F21

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23

H21
H23
K22
K21
G23
H20
K20
K23

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

N23
P21
T20
T23
M20
P20
R23
T22

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39

V20
V21
Y23
Y22
T21
U23
W23
Y21

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47

Y20
AB22
AC19
AA18
AA23
AA20
AB19
Y18

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55

AC17
Y16
AB14
AC14
AC18
AB18
AB15
AC15

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

M23

+MEM_VREF

DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]

DDR_A_D[0..63]

<8,9>

DDR_A_MA[0..15]
DDR_A_DM[0..7]

<8,9>
<8,9>

U22A
<15> PCIE_CRX_GTX_P0
<15> PCIE_CRX_GTX_N0

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

AA6
Y6

<15> PCIE_CRX_GTX_P1
<15> PCIE_CRX_GTX_N1

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

AB4
AC4

<15> PCIE_CRX_GTX_P2
<15> PCIE_CRX_GTX_N2

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

AA1
AA2

<15> PCIE_CRX_GTX_P3
<15> PCIE_CRX_GTX_N3

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

Y4
Y3

1
2
R435 2K_0402_1%

+1.05VS

P_ZVDD_10

Y14

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_GPP_TXP0
P_GPP_TXN0

P_ZVDD_10

P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_ZVSS

AB6 PCIE_CTX_C_GRX_P0 C518 1


AC6 PCIE_CTX_C_GRX_N0 C519 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P0 <15>
PCIE_CTX_GRX_N0 <15>

AB3 PCIE_CTX_C_GRX_P1 C520 1


AC3 PCIE_CTX_C_GRX_N1 C521 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P1 <15>
PCIE_CTX_GRX_N1 <15>

Y1
Y2

PCIE_CTX_C_GRX_P2 C522 1
PCIE_CTX_C_GRX_N2 C523 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P2 <15>
PCIE_CTX_GRX_N2 <15>

V3
V4

PCIE_CTX_C_GRX_P3 C524 1
PCIE_CTX_C_GRX_N3 C525 1

2 0.1U_0402_16V7K
2 0.1U_0402_16V7K

PCIE_CTX_GRX_P3 <15>
PCIE_CTX_GRX_N3 <15>

AA14 P_ZVSS

R436 1

1.27K_0402_1%

Less than 1"

M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47

M_CLK_H0
M_CLK_L0
M_CLK_H1
M_CLK_L1
M_CLK_H2
M_CLK_L2
M_CLK_H3
M_CLK_L3

B14
A15
A17
D18
A14
C14
C16
D16

PCIE I/F

R17
H19
J17
H18
H17
G17
H15
G18
F19
E19
T19
F17
E18
W17
E16
G15

Less than 1"


<10> UMI_RX0P
<10> UMI_RX0N

AA12
Y12

<10> UMI_RX1P
<10> UMI_RX1N

AA10
Y10

<10> UMI_RX2P
<10> UMI_RX2N

AB10
AC10

<10> UMI_RX3P
<10> UMI_RX3N

AC7
AB7

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_UMI_TXP0
P_UMI_TXN0

UMI I/F

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

AB12
AC12

UMI_TX0P_C
UMI_TX0N_C

C526 1
C527 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AC11
AB11

UMI_TX1P_C
UMI_TX1N_C

C528 1
C529 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AA8
Y8

UMI_TX2P_C
UMI_TX2N_C

C530 1
C531 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

AB8
AC8

UMI_TX3P_C
UMI_TX3N_C

C532 1
C533 1

2
2

0.1U_0402_16V7K
0.1U_0402_16V7K

UMI_TX0P <10>
UMI_TX0N <10>
UMI_TX1P <10>
UMI_TX1N <10>
UMI_TX2P <10>
UMI_TX2N <10>
UMI_TX3P <10>
UMI_TX3N <10>

S IC E SERIES EME450GBB22GVA 1.65G BGA

M_VREF

M_RAS_L
M_CAS_L
M_WE_L
M_ZVDDIO_MEM_S
S IC E SERIES EME450GBB22GVA 1.65G BGA

M22 M_ZVDDIO_MEM_SR437 2

+1.5V_APU

39.2_0402_1%

+1.5V_APU

+1.5V_APU

R438
1K_0402_1%
DDR_EVENT#

2
1K_0402_5%

+MEM_VREF

R444 1

R439
1K_0402_1%

C535

1
1

C534

1000P_0402_50V7K

0.1U_0402_16V4Z

Place within 1000 mils to APU


20100526

Compal Secret Data

Security Classification
Issued Date

2010/06/30

2012/0630

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


FT1 DDRIII/UMI/PCIE

Size
Document Number
Custom
Date:

Rev
1.0

LA8681P

Wednesday, November 30, 2011


E

Sheet

of

48

+1.8VS

10U_0603_6.3V6M

1U_0402_6.3V6K
C549

1U_0402_6.3V6K
C548

1U_0402_6.3V6K
C547

1U_0402_6.3V6K
C538

0.1U_0402_16V7K
C546

C545

180P_0402_50V8J
C537

Change from SM010014520 to SD002000080


20100816

10U_0603_6.3V6M

1U_0402_6.3V6K
C558

C556

1
FBMA-L11-201209-221LMA30T_0805

+1.0VS has been raised to +1.05VS for


AMD design guide 45339_R1.02 update 20101004
+1.05VS

5.5A

10U_0603_6.3V6M

place C564
2
close APU ball

1U_0402_6.3V6K
C567

2
1

0.1U_0402_16V7K
C566

L32

0.5A

10U_0603_6.3V6M
C574

1U_0402_6.3V6K
C573

1U_0402_6.3V6K
C572

0.1U_0402_16V7K
C571

2
1

0.1U_0402_16V7K
C570

U13
W13
V12
T12

C1102

+VDD_10
VDD_10_1
VDD_10_2
VDD_10_3
VDD_10_4

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

C564

+VDDL_10
180P_0402_50V8J
C565

U11

VDDPL_10

FBMA-L11-201209-221LMA30T_0805
Change from SM010014520 to SD002000080
20100816

N13
N20
N22
P10
P14
R4
R7
R20
T6
T9
T11
T13
U4
U5
U7
U12
U20
U22
V8
V9
V11
V13
W1
W2
W4
W5
W7
W12
W20
Y5
Y7
Y9
Y11
Y13
Y15
Y17
Y19
AA4
AA22
AB2
AB5
AB9
AB13
AB17
AB21
AC5
AC9
AC13
A11

VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSSBG_DAC

+3VS
S IC E SERIES EME450GBB22GVA 1.65G BGA

A4

VDD_33

VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49

10U_0603_6.3V6M

C590

C598

1U_0402_6.3V6K

C597

1U_0402_6.3V6K

C595

C596

C594

1U_0402_6.3V6K

C589

10U_0603_6.3V6M

U22D
A7
B7
B11
B17
B22
C4
D5
D7
D9
D11
D14
B15
D17
D19
E7
E9
E12
E20
F8
F11
F13
G4
G5
G7
G9
G12
G20
G22
H6
H11
H13
J4
J5
J7
J20
K10
K14
L4
L6
L8
L11
L13
L20
L22
M7
N4
N6
N8
N11

+1.5V_APU

1U_0402_6.3V6K

L31

S IC E SERIES EME450GBB22GVA 1.65G BGA

0.1U_0402_16V7K

C593

C592

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

C591

180P_0402_50V8J
C557

1U_0402_6.3V6K

C588

180P_0402_50V8J

C587

180P_0402_50V8J

C586

C585

1U_0402_6.3V6K

1U_0402_6.3V6K

C584

1U_0402_6.3V6K

C583

1U_0402_6.3V6K

1U_0402_6.3V6K

C582

0.2A

DP Phy/IO

DDR3

VDDIO_MEM_S_1
VDDIO_MEM_S_2
VDDIO_MEM_S_3
VDDIO_MEM_S_4
VDDIO_MEM_S_5
VDDIO_MEM_S_6
VDDIO_MEM_S_7
VDDIO_MEM_S_8
VDDIO_MEM_S_9
VDDIO_MEM_S_10
VDDIO_MEM_S_11

+VDD_18_DAC

POWER

2A
G16
G19
E17
J16
L16
L19
N16
R16
R19
W18
U16

L30
W9

VDD_18_DAC

180P_0402_50V8J
C569

+1.5V_APU

Change from SM010014520 to SD002000080


20100816
+1.8VS

PCIE/IO/DDR3 Phy

+APU_CORE_NB

VDDCR_NB_1
VDDCR_NB_2
VDDCR_NB_3
VDDCR_NB_4
VDDCR_NB_5
VDDCR_NB_6
VDDCR_NB_7
VDDCR_NB_8
VDDCR_NB_9
VDDCR_NB_10
VDDCR_NB_11
VDDCR_NB_12
VDDCR_NB_13
VDDCR_NB_14
VDDCR_NB_15
VDDCR_NB_16
VDDCR_NB_17
VDDCR_NB_18
VDDCR_NB_19
VDDCR_NB_20
VDDCR_NB_21
VDDCR_NB_22

0.15A

10A
E8
E11
E13
F9
F12
G11
G13
H9
H12
K11
K13
L10
L12
L14
M11
M12
M13
N10
N12
N14
P11
P13

C580

C555

180P_0402_50V8J

180P_0402_50V8J

C554
C563

+APU_CORE_NB

0.1U_0402_16V7K

1U_0402_6.3V6K

C553
C562

0.1U_0402_16V7K

1U_0402_6.3V6K

C552
C561

0.1U_0402_16V7K

1U_0402_6.3V6K

C551
C560

0.1U_0402_16V7K

1U_0402_6.3V6K

C550
C559

0.1U_0402_16V7K

L29
2
1
FBMA-L11-201209-221LMA30T_0805

GND

U8
W8
U6
U9
W6
T7
V7

VDD_18_1
VDD_18_2
VDD_18_3
VDD_18_4
VDD_18_5
VDD_18_6
VDD_18_7

DIS PLL

GPU AND NB CORE

DAC

CPU CORE

VDDCR_CPU_1
VDDCR_CPU_2
VDDCR_CPU_3
VDDCR_CPU_4
VDDCR_CPU_5
VDDCR_CPU_6
VDDCR_CPU_7
VDDCR_CPU_8
VDDCR_CPU_9
VDDCR_CPU_10
VDDCR_CPU_11
VDDCR_CPU_12
VDDCR_CPU_13
VDDCR_CPU_14
VDDCR_CPU_15

+VDD_18

TSense/PLL/DP/PCIE/IO

E5
E6
F5
F7
G6
G8
H5
H7
J6
J8
L7
M6
M8
N7
R8

+APU_CORE
D

2A

U22C

0.1U_0402_16V7K
C581

11A

+APU_CORE

C603

C602

C601

180P_0402_50V8J

180P_0402_50V8J

0.1U_0402_16V7K

C600

0.1U_0402_16V7K

C599

0.1U_0402_16V7K

+1.5V_APU
1

+1.5V

J15

JUMP_43X79

By case (Along split)


+1.5V_APU

Issued Date

2010/06/30

Deciphered Date

2012/06/30

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

C615

C614

180P_0402_50V8J

C613

C612

180P_0402_50V8J

Compal Electronics, Inc.


P07-FT1 PWR/VSS

Size
C
Date:

180P_0402_50V8J

C611

C610

180P_0402_50V8J

C609

C608

Compal Secret Data

Security Classification

Near CPU Socket

0.1U_0402_16V7K

0.1U_0402_16V7K

C623

22U_0805_6.3V6M

C622

330U_2.5V_M

0.1U_0402_16V7K

+1.5V_APU

0.1U_0402_16V7K

POWER

Document Number

Rev
1.0

LA8681P
Tuesday, November 29, 2011
1

Sheet

of

48

+1.5V

DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

<6,9> DDR_CKE0
C

<6,9> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_A_CLK0
<6> DDR_A_CLK#0
DDR_A_MA10
<6,9> DDR_A_BS0
<6,9> DDR_A_WE#
<6,9> DDR_A_CAS#
DDR_A_MA13
<6> DDR_CS1_DIMMA#

DDR_A_D32
DDR_A_D33
<6,9> DDR_A_DQS#4
<6,9> DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6,9> DDR_A_DQS#6
<6,9> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7

1
R446
10K_0402_5%
2

0.1U_0402_16V4Z

C647

C646

+3VS

2.2U_0603_6.3V4Z

DDR_A_D58
DDR_A_D59
R445
10K_0402_5%
1
2

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207

CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
GND1
BOSS1

CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
GND2
BOSS2

DDR_A_MA[0..15] <6,9>

R440
1K_0402_1%

DDR_A_DM[0..7] <6,9>
1

R441
1K_0402_1%
1

DDR_A_DM[0..7]

DDR_A_D6
DDR_A_D7

+VREF_CA
2

DDR_A_DM1

+VREF_DQ

DDR_A_D12
DDR_A_D13

R443
1K_0402_1%

DDR_A_D20
DDR_A_D21

R442
1K_0402_1%

DDR_RST# <6,9>
DDR_A_D14
DDR_A_D15

Combine to one?

DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 <6,9>
DDR_A_DQS3 <6,9>
DDR_A_D30
DDR_A_D31

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

DDR_A_MA11
DDR_A_MA7

C628

C629
1

0.1U_0402_16V4Z
2
C630

1
0.1U_0402_16V4Z

C631
1

0.1U_0402_16V4Z
2
C632

1
0.1U_0402_16V4Z

C633
1

DDR_A_MA2
DDR_A_MA0
DDR_A_CLK1 <6>
DDR_A_CLK#1 <6>
DDR_A_BS1 <6,9>
DDR_A_RAS# <6,9>
DDR_CS0_DIMMA# <6>
DDR_A_ODT0 <6>

CRB 0.1u X1

4.7u X1

CRB

100U

DDR_A_ODT1 <6>

X2

+1.5V
+0.75VS
+VREF_CA

DDR_A_D36
DDR_A_D37
DDR_A_DM4
DDR_A_D38
DDR_A_D39
DDR_A_D44
DDR_A_D45

1
+
2

20100729
DDR_A_DQS#5 <6,9>
DDR_A_DQS5 <6,9>

Place near JDIMM1

DDR_A_D46
DDR_A_D47

SF000002Y00

DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <6,9>
DDR_A_DQS7 <6,9>
DDR_A_D62
DDR_A_D63
A

DDR_EVENT# <6,9>
FCH_SMDAT0 <9,12,29>
FCH_SMCLK0 <9,12,29>
+0.75VS

Compal Secret Data

Security Classification

DDR3 SO-DIMM A
Reverse Type

0.1U_0402_16V4Z
2

1
0.1U_0402_16V4Z

DDR_A_MA6
DDR_A_MA4

206
208

LCN_DAN06-K4406-0103

+1.5V

DDR_CKE1 <6,9>
DDR_A_MA15
DDR_A_MA14

C643

DDR_A_D18
DDR_A_D19

+1.5V

220U_6.3V_M

<6,9> DDR_A_DQS#2
<6,9> DDR_A_DQS2

DDR_A_MA[0..15]

DDR_A_DQS#0 <6,9>
DDR_A_DQS0 <6,9>

+1.5V
<6,9>

0.1U_0402_16V4Z

DDR_A_D16
DDR_A_D17

DDR_A_D[0..63]

C641

DDR_A_D10
DDR_A_D11

DDR_A_D[0..63]

4.7U_0603_6.3V6K

<6,9> DDR_A_DQS#1
<6,9> DDR_A_DQS1

DDR_A_D4
DDR_A_D5

C642

DDR_A_D8
DDR_A_D9

VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS

0.1U_0402_16V4Z

DDR_A_D2
DDR_A_D3

VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C644

DDR_A_DM0

ME@

1000P_0402_50V7K

DDR_A_D0
DDR_A_D1

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

C645

C627

1000P_0402_50V7K

0.1U_0402_16V4Z

C626

+1.5V
JDIMM1

+VREF_DQ

Issued Date

2010/06/30

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


DDR3 SODIMM-I Socket

Size Document Number


Custom
Date:

Rev
1.0

LA8681P

Wednesday, November 30, 2011


1

Sheet

of

48

+1.5V

DDR_A_D10
DDR_A_D11
DDR_A_D16
DDR_A_D17
<6,8> DDR_A_DQS#2
<6,8> DDR_A_DQS2
DDR_A_D18
DDR_A_D19
DDR_A_D24
DDR_A_D25
DDR_A_DM3
DDR_A_D26
DDR_A_D27

73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203

<6,8> DDR_CKE0

<6,8> DDR_A_BS2
DDR_A_MA12
DDR_A_MA9
DDR_A_MA8
DDR_A_MA5
DDR_A_MA3
DDR_A_MA1
<6> DDR_B_CLK2
<6> DDR_B_CLK#2
DDR_A_MA10
<6,8> DDR_A_BS0
<6,8> DDR_A_WE#
<6,8> DDR_A_CAS#
DDR_A_MA13
<6> DDR_CS1_DIMMB#

DDR_A_D32
DDR_A_D33
<6,8> DDR_A_DQS#4
<6,8> DDR_A_DQS4

DDR_A_D34
DDR_A_D35
DDR_A_D40
DDR_A_D41
DDR_A_DM5
DDR_A_D42
DDR_A_D43
DDR_A_D48
DDR_A_D49
<6,8> DDR_A_DQS#6
<6,8> DDR_A_DQS6
DDR_A_D50
DDR_A_D51
DDR_A_D56
DDR_A_D57
DDR_A_DM7
For DRAM strap pin reservation
20100817
DDR_A_D58
DDR_A_D59
DIMM@
R961 1
2 10K_0402_5%
+3VS
C667
2.2U_0603_6.3V4Z
DIMM@

DIMM@
205

C668
2
0.1U_0402_16V4Z

only one 4.7k

G1

CKE1
VDD2
A15
A14
VDD4
A11
A7
VDD6
A6
A4
VDD8
A2
A0
VDD10
CK1
CK1#
VDD12
BA1
RAS#
VDD14
S0#
ODT0
VDD16
ODT1
NC2
VDD18
VREF_CA
VSS28
DQ36
DQ37
VSS30
DM4
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
DM6
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
SDA
SCL
VTT2
G2

DDR_A_DM[0..7] <6,8>

DDR_RST# <6,8>
DDR_A_D14
DDR_A_D15
DDR_A_D20
DDR_A_D21
DDR_A_DM2
DDR_A_D22
DDR_A_D23
DDR_A_D28
DDR_A_D29
DDR_A_DQS#3 <6,8>
DDR_A_DQS3 <6,8>

+1.5V

DDR_A_D30
DDR_A_D31
2

74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204

0.1U_0402_16V4Z
2

C650
DIMM@
1
0.1U_0402_16V4Z

DDR_CKE1 <6,8>

C651
DIMM@
1

0.1U_0402_16V4Z
2
2

0.1U_0402_16V4Z
2

C652
C653
C654
DIMM@
DIMM@
DIMM@
1
1
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C655
DIMM@
1
C

DDR_A_MA15
DDR_A_MA14
DDR_A_MA11
DDR_A_MA7
DDR_A_MA6
DDR_A_MA4

CRB 0.1u X1

4,7uX1

DDR_A_MA2
DDR_A_MA0
+0.75VS
DDR_B_CLK3 <6>
DDR_B_CLK#3 <6>

DDR_A_BS1 <6,8>
DDR_A_RAS# <6,8>

2
DIMM@

DDR_CS0_DIMMB# <6>
DDR_B_ODT0 <6>

DIMM@

DDR_B_ODT1 <6>
+VREF_CA
DDR_A_D36
DDR_A_D37
DDR_A_DM4

DIMM@

DDR_A_D38
DDR_A_D39

DDR_A_D44
DDR_A_D45

Place near JDIMM2


1
DIMM@

DDR_A_DQS#5 <6,8>
DDR_A_DQS5 <6,8>
DDR_A_D46
DDR_A_D47
DDR_A_D52
DDR_A_D53
DDR_A_DM6
DDR_A_D54
DDR_A_D55
DDR_A_D60
DDR_A_D61
DDR_A_DQS#7 <6,8>
DDR_A_DQS7 <6,8>
DDR_A_D62
DDR_A_D63
DDR_EVENT# <6,8>
FCH_SMDAT0 <8,12,29>
FCH_SMCLK0 <8,12,29>

+0.75VS

206

LCN_DAN06-K4806-0103

DIMM@
R962
10K_0402_5%

DDR3 SO-DIMM B
Reverse Type

For DRAM strap pin reservation


20100817

<6,8>

DDR_A_MA[0..15] <6,8>

DDR_A_DM1

CRB

CKE0
VDD1
NC1
BA2
VDD3
A12/BC#
A9
VDD5
A8
A5
VDD7
A3
A1
VDD9
CK0
CK0#
VDD11
A10/AP
BA0
VDD13
WE#
CAS#
VDD15
A13
S1#
VDD17
NCTEST
VSS27
DQ32
DQ33
VSS29
DQS#4
DQS4
VSS32
DQ34
DQ35
VSS34
DQ40
DQ41
VSS36
DM5
VSS37
DQ42
DQ43
VSS39
DQ48
DQ49
VSS41
DQS#6
DQS6
VSS44
DQ50
DQ51
VSS46
DQ56
DQ57
VSS48
DM7
VSS49
DQ58
DQ59
VSS51
SA0
VDDSPD
SA1
VTT1

DDR_A_DM[0..7]
DDR_A_D12
DDR_A_D13

DDR_A_D[0..63]

C663

<6,8> DDR_A_DQS#1
<6,8> DDR_A_DQS1

DDR_A_D[0..63]
DDR_A_MA[0..15]

0.1U_0402_16V4Z

DDR_A_D8
DDR_A_D9

DDR_A_DQS#0 <6,8>
DDR_A_DQS0 <6,8>
DDR_A_D6
DDR_A_D7

C664

DDR_A_D2
DDR_A_D3

DDR_A_D4
DDR_A_D5

4.7U_0603_6.3V6K

DDR_A_DM0

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72

C666

VSS1
DQ4
DQ5
VSS3
DQS#0
DQS0
VSS6
DQ6
DQ7
VSS8
DQ12
DQ13
VSS10
DM1
RESET#
VSS12
DQ14
DQ15
VSS14
DQ20
DQ21
VSS16
DM2
VSS17
DQ22
DQ23
VSS19
DQ28
DQ29
VSS21
DQS#3
DQS3
VSS24
DQ30
DQ31
VSS26

1000P_0402_50V7K

VREF_DQ
VSS2
DQ0
DQ1
VSS4
DM0
VSS5
DQ2
DQ3
VSS7
DQ8
DQ9
VSS9
DQS#1
DQS1
VSS11
DQ10
DQ11
VSS13
DQ16
DQ17
VSS15
DQS#2
DQS2
VSS18
DQ18
DQ19
VSS20
DQ24
DQ25
VSS22
DM3
VSS23
DQ26
DQ27
VSS25

C665

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71

DDR_A_D0
DDR_A_D1

ME@

0.1U_0402_16V4Z

DIMM@
C648 C649

1000P_0402_50V7K

0.1U_0402_16V4Z

DIMM@
D

+1.5V
JDIMM2

+VREF_DQ

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

Compal Electronics, Inc.


DDR3 SODIMM-II Socket

Size Document Number


Custom
Date:

Rev
1.0

LA8681P

Wednesday, November 30, 2011

Sheet
1

of

48

C146 place close to FCH

C146 1

U2A

2 150P_0402_50V8J

HUDSON-2

<25>
<25>
<29>
<29>

WLAN

<25>
<25>
<29>
<29>

AB33
AB31
AB28
AB29
Y33
Y31
Y28
Y29

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

PCIE_CALRP
PCIE_CALRN

AF29
AF31

PCIE_CALRP
PCIE_CALRN

PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
PCIE_FTX_DRX_N1

V33
V31
W30
W32
AB26
AB27
AA24
AA23

1
1
1
1

2
2
2
2

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

AA27
AA26
W27
V27
V26
W26
W24
W23

PCIE_FRX_DTX_P0
PCIE_FRX_DTX_N0
PCIE_FRX_DTX_P1
PCIE_FRX_DTX_N1

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N

R26
T26

<5> APU_DISP_CLK
<5> APU_DISP_CLK#

H33
H31
T24
T23

<5> APU_CLK
<5> APU_CLK#
R98
R99

<15> CLK_PCIE_VGA
<15> CLK_PCIE_VGA#

VGA

1
1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R

J30
K29
H27
H28
J27
K26

WLAN
LAN

<29> CLK_PCIE_WLAN
<29> CLK_PCIE_WLAN#

R102 1
R103 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R

F33
F31

<25> CLK_PCIE_LAN
<25> CLK_PCIE_LAN#

R100 1
R101 1

2 0_0402_5%
2 0_0402_5%

CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R

E33
E31

T101

@
22_0402_5%
R559 1
2

25M_X2

DISP_CLKP
DISP_CLKN
DISP2_CLKP
DISP2_CLKN
APU_CLKP
APU_CLKN
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N

GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N

M27
M26

GPP_CLK5P
GPP_CLK5N

N25
N26

GPP_CLK6P
GPP_CLK6N

R23
R24

GPP_CLK7P
GPP_CLK7N

N27
R27

GPP_CLK8P
GPP_CLK8N

C31

C33

INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35

GPP_CLK1P
GPP_CLK1N

M23
M24

J26

25M_X1

PCIE_RCLKP
PCIE_RCLKN

LPCCLK0

LPC

G30
G28

CLK_CALRN

LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48

DMA_ACTIVE#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#

APU

F27

14M_25M_48M_OSC
S5_CORE_EN
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G

25M_X1

25M_X2

32K_X1

32K_X2

C789 @
1
2

@
C790
150P_0402_50V8J

@
R693
8.2K_0402_5%

U43

APU_PCIE_RST# <15,29>
2

APU_PCIE_RST#_C

0.1U_0402_16V4Z

MC74VHC1G08DFT2G SC70 5P
@ R692
2
B
1
2
33_0402_5%
1 A

APU_PCIE_RST #: Reset PCIE device on APU

AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9

AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/SD_LED/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#

S5 PLUS

CLK_CALRN

2 2K_0402_1%

CLOCK GENERATOR

R95

PCI_CLK3 <14>
PCI_CLK4 <14>

+3VALW

+1.1VS_CKVDD

PCIRST#

AB5

PCI_CLK1 <14>

R866
0_0402_5%
1

2 590_0402_1%
2 2K_0402_1%

1
1

C718
C720
C721
C719

PCIE_FTX_C_DRX_P0
PCIE_FTX_C_DRX_N0
PCIE_FTX_C_DRX_P1
PCIE_FTX_C_DRX_N1

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

@R695
@
R695
1
2
0_0402_5%

PLT_RST# <25,30>

R692/ C790 close to FCH

PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27

<14>
<14>
<14>
<14>
<14>

Module design have reserve GPIO44,45 for


VGA power enable and reset

T14

T99

AF18
AE18
AC16
AD18

B25

R558 1

2 22_0402_5%

D25
D27
C28
A26
A29
A31
B27
AE27
AE19

CLK_PCI_EC <14,30>
@
1
2
R670
0_0402_5%

CLK_PCI_DB <29>

LPC_CLK1 <14>
LPC_AD0 <29,30>
LPC_AD1 <29,30>
LPC_AD2 <29,30>
LPC_AD3 <29,30>
LPC_FRAME# <29,30>

SERIRQ <30>

G25
E28 APU_PROCHOT#_R
E26
G26
F26

APU_PWRGD <5,44>

H7
F1
F3
E6

RTC_CLK <14,30>

R15

APU_RST# <5>

change to 510 Ohm

T100

W=20mils

G2

32K_X1

G4

32K_X2

ALLOW_STOP# <5>
H_PROCHOT# <5,30,37>

2 0_0402_5%

25M_X1

+RTCBATT
2
510_0402_5%

1
R105

+VDDAN_11_PCIE

LAN

AE30
AE32
AD33
AD31
AD28
AD29
AC30
AC32

UMI_RXP0_C
UMI_RXN0_C
UMI_RXP1_C
UMI_RXN1_C
UMI_RXP2_C
UMI_RXN2_C
UMI_RXP3_C
UMI_RXN3_C

0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K
0.1U_0402_16V7K

AF3
AF1
AF5
AG2
AF6

C156
2

R94
R88

2
2
2
2
2
2
2
2

PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39

UMI_TX0P
UMI_TX0N
UMI_TX1P
UMI_TX1N
UMI_TX2P
UMI_TX2N
UMI_TX3P
UMI_TX3N

1
1
1
1
1
1
1
1

PCIE_RST#
A_RST#

1U_0402_6.3V6K

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

C147
C148
C149
C150
C151
C152
C153
C154

AE2
AD5

PCI CLKS

UMI_RX0P
UMI_RX0N
UMI_RX1P
UMI_RX1N
UMI_RX2P
UMI_RX2N
UMI_RX3P
UMI_RX3N

APU_PCIE_RST#_C
2 33_0402_5% A_RST#

PCI INTERFACE

<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>

1 R557

PCI EXPRESS INTERFACES

PLT_RST#

CLRP1 @
SHORT PADS

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38


C158 1

1
2
R106 1M_0402_5%
NC
OSC

R107
20M_0402_5%

Y4
1 25MHZ_20PF_FSX3M-25.M20FDO 1
C157
22P_0402_50V8J

C155
22P_0402_50V8J

Y1
32.768KHZ_12.5PF_CM31532768DZFT

C159 1

NC

32K_X2

Compal Secret Data

Security Classification
2011/10/12

Issued Date

22P_0402_50V8J

Deciphered Date

2013/10/12

Title

Compal Electronics, Inc.


FCH PCIE/CLK/PCI/LPC/RTC

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

for Clear CMOS

OSC

22P_0402_50V8J
3

32K_X1

2
1

25M_X2
4

Size Document Number


Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet
E

10

of

48

4MB SPI ROM


& Non-share ROM.

SPI_CLK_FCH

+3VALW

2 SPI_WP#_R
3.3K_0402_5%

R108 1

10K_0402_5%
2 SPI_HOLD#

U2B
1

HUDSON-2

SATA_RX0N
SATA_RX0P

AN22
AL22

SATA_TX1P
SATA_TX1N

<28> SATA_FRX_C_DTX_N1
<28> SATA_FRX_C_DTX_P1

AJ22
AH22
AM23
AK23

FCH-M3L NC pin

AH24
AJ24

SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P

AL26
AN26

SATA_TX4P
SATA_TX4N

AJ26
AH26

SATA_RX4N
SATA_RX4P

AN29
AL28

SATA_TX5P
SATA_TX5N

AK27
AM27

SATA_RX5N
SATA_RX5P

AL29
AN31

NC6
NC7

AH33
AH31
AJ33
AJ31

1K_0402_1%

1 R128

SATA_CALRP

AF28

931_0402_1%

1 R130

SATA_CALRN

AF27

GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR

SATA_TX2P
SATA_TX2N

AN24
AL24

AL31
AL33

+AVDD_SATA

SATA_RX1N
SATA_RX1P

GBE LAN

AH20
AJ20

SD CARD

AL20
AN20

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD_DATA2/GPIO79
SD_DATA3/GPIO80

SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161

SPI ROM

ODD

<28> SATA_FTX_C_DRX_P1
<28> SATA_FTX_C_DRX_N1

SATA_TX0P
SATA_TX0N

VGA_RED
NC8
NC9
VGA_GREEN
NC10
NC11
VGA_BLUE
NC12
NC13

VGA DAC

<28> SATA_FRX_C_DTX_N0
<28> SATA_FRX_C_DTX_P0

AK19
AM19

SERIAL ATA

HDD

<28> SATA_FTX_C_DRX_P0
<28> SATA_FTX_C_DRX_N0

VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71

SATA_CALRP
SATA_CALRN

VGA_DAC_RSET
10K_0402_5% 1

2 R133

AD22
AF21

SATA_ACT#/GPIO67
SATA_X1

AG21

SATA_X2

AUX_VGA_CH_P
AUX_VGA_CH_N

VGA MAINLINK

+3VS

AUXCAL
ML_VGA_L0P
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229

T48
<28> BT_ON#

AH16
AM15
AJ16
AK15
AN16
AL16

<29> BT_DISABLE#
<29> WL_OFF#

K6

<28> ODD_EN

FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58

HW MONITOR

1
R149

1
R151

K5

VIN4/SLOAD_1/GPIO179

10K_0402_5%
K3
10K_0402_5%
2

M6
10K_0402_5%

TEMPIN1/GPIO172

SPI_SO_R
SPI_SI_R
SPI_CLK_FCH_R
SPI_SB_CS0#_R
SPI_WP#

VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182

TEMPIN3/TALERT#/GPIO174

SPI_WP#

U4
SPI_SB_CS0#
1 CS#
VCC 8
SPI_SO_L
2
7
HOLD#
SPI_WP#_R 3 SO/SIO1
WP#
SCLK 6
33_0402_5%
4 GND
5
SI/SIO0
R117
W25Q32BVSSIG SOIC 8
R116
0_0402_5%
1
2

R110
SPI_HOLD#
0_0402_5%
SPI_CLK_FCH 1
2
SPI_SI
1
2

SPI_CLK_FCH_R
SPI_SI_R

33_0402_5%
R119
R110 place close to FCH
+3VALW

GBE_PHY_INTR

R121 1

2 10K_0402_5%

L32

FCH-M3L NC pin

M29
M28
N30
M33
N32
K31
V28
V29
U28
T31
T33
T29
T28
R32
R30
P29
P28

C29

L2

1
R137
1
R138
1
R139

1
R148

10K_0402_5%
2
10K_0402_5%
2
10K_0402_5%

N4
P1
P3
M1
M5

TEMPIN2/GPIO173
NC1
NC2
NC3
NC4
NC5

C160
22P_0402_50V8J
@

L30

M3

VIN5/SCLK_1/GPIO180
1
R146

GBE_PHY_INTR

V6
V5
V3
T6
V1

N2

TEMPIN0/GPIO171

R115
0_0402_5%
SPI_SB_CS0#_R 1
2
SPI_SO_R
1
2

AC4
AD3
AD9
W10
AB8
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9

VIN1/GPIO176

VIN3/SDATO_1/GPIO178

+3VALW
0.1U_0402_16V4Z
C165
1
2

AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14

VIN0/GPIO175

VIN2/SDATI_1/GPIO177

R111
33_0402_5%
@
R112 1

AG16
AH10
A28
G27
L4

10K_0402_5%

Need to enable internal


pull down to leave
unconnected

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

FCH SATA/SPI/VGA/HWM/SD
Size Document Number
Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet
E

11

of

48

U2D

PCIE_RST2 : Reset PCIE device on Hudson 3

<30> GATEA20

GA20IN/GEVENT0#

<30> KBRST#
<30> EC_SCI#
<30> EC_SMI#

AG19
R9
C26
T5
U4
K1
V7
R10
AF19

KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
LPC_PD#/GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD

SYS_RESET#

2 10K_0402_5%

<25,29> FCH_PCIE_WAKE#
<5> H_THERMTRIP#

WD_PWRGD

U2

<30> EC_RSMRST#
<25> LAN_CLKREQ#

<27> FCH_SPKR
<8,9,29> FCH_SMCLK0
<8,9,29> FCH_SMDAT0

For FCH internal debug use


@

2 2.2K_0402_5%

TEST0

R181 1

2 2.2K_0402_5%

TEST1

R183 1

2 2.2K_0402_5%

TEST2

FCH_SMCLK0
FCH_SMDAT0
FCH_SMCLK1
FCH_SMDATA1

<29> WLAN_CLKREQ#
<15,17,43> VGA_PWRGD

R156 2

<16> PEG_CLKREQ#

1 0_0402_5% PEG_CLKREQ#_R

USB_OC7#
<28> ODD_DA#_FCH

+3VALW

USB_OC5#

<28> ODD_DETECT#
2 10K_0402_5%

USB_OC7#

2 10K_0402_5%

USB_OC2#

R625

2 10K_0402_5%

USB_OC1#

R174

2 10K_0402_5%

USB_OC0#

R883

R624

R618

2 10K_0402_5%

ODD_DA#_FCH

R649

2 10K_0402_5%

ODD_DETECT#

R620

2 10K_0402_5%

USB_OC5#

R163

2 10K_0402_5%

USB_OC3#

<32> USB_OC2#
<33> USB_OC1#
<34> USB_OC0#

2 10K_0402_5%

R169

2 100K_0402_5%

R170

2 10K_0402_5% FCH_PCIE_WAKE#

<27> HDA_BITCLK_AUDIO
<27> HDA_SDOUT_AUDIO
<27> HDA_SDIN0

<27> HDA_SYNC_AUDIO
<27> HDA_RST_AUDIO#

R159 1
R160 1

2 33_0402_5%
2 33_0402_5%

R161 1
R162 1

2 33_0402_5%
2 33_0402_5%

HDA_SYNC
HDA_RST#

T61
T19

GPIO189
GPIO190
<15> PXS_RST#
<17,43> PXS_PWREN

0_0402_5% 2
0_0402_5% 2

PX@ 1
PX@ 1

R96
R97

FCH_SMDAT0

R175

2 10K_0402_5%

WD_PWRGD

R173

2 8.2K_0402_5% WLAN_CLKREQ#

R176

2 8.2K_0402_5%

2 2.2K_0402_5%

2 2.2K_0402_5%

Q112
S 2N7002K_SOT23-3

2
G

<30> VGA_GATE#

LAN_CLKREQ#

2 10K_0402_5%

FCH_SMDATA1

R177 1

2 2.2K_0402_5%

EC_RSMRST#

R178 1

2 10K_0402_5%

HDA_BITCLK

R180 1

2 10K_0402_5%

HDA_SDIN0

2 10K_0402_5% PEG_CLKREQ#_R

USB 1.1

USB_HSD13P
USB_HSD13N

USB_HSD11P
USB_HSD11N

K19
J19
J21

D21
C20
D23
C22

PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192

EMBEDDED CTRL

10K_0402_5%
R684

KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226

USB30_P11 <34>
USB30_N11 <34>

K12
K13

USB30_P10 <34>
USB30_N10 <34>

E10
F10

FCH-M3L NC pin

Root

H9
G9

USB20_P6 <28>
USB20_N6 <28>

USB_HSD5P
USB_HSD5N

A8
C8

USB20_P5 <32>
USB20_N5 <32>

USB_HSD4P
USB_HSD4N

F8
E8

USB_HSD0P
USB_HSD0N

USB20_P3 <22>
USB20_N3 <22>

C5
A5

USB20_P2 <29>
USB20_N2 <29>

C1
C3

USB20_P1 <32>
USB20_N1 <32>

E1
E3
C16
A16

USB_SS_TX3P
USB_SS_TX3N

A14
C14

USB_SS_RX2P
USB_SS_RX2N

FCH-M3L NC pin

C6
A6

USBSS_CALRP
USBSS_CALRN

USB_SS_TX2P
USB_SS_TX2N

USB20_P0 <33>
USB20_N0 <33>
USBSS_CALRP
USBSS_CALRN

R864 1
R865 1

D15
B15

H13
G13

USB30_FRX_DTX_P1
USB30_FRX_DTX_N1

USB_SS_TX0P
USB_SS_TX0N

J16
H16

USB30_FTX_DRX_P0
USB30_FTX_DRX_N0

USB_SS_RX0P
USB_SS_RX0N

J15
K15

USB30_FRX_DTX_P0
USB30_FRX_DTX_N0

H19
G19
G22
G21
E22
H22
J22
H21

R165
R167
R227
R228

KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208

CMOS
WLAN Root
RP2
RP1

+FCH_VDD_11_SSUSB_S

E14
F14
USB30_FTX_DRX_P1
USB30_FTX_DRX_N1

SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200

2 1K_0402_1%
2 1K_0402_1%

BT
CR

FCH-M3L NC pin

C12
A12

F15
G15

USB_SS_TX1P
USB_SS_TX1N

Root

LP2
LP1

C10
A10

USB_HSD6P
USB_HSD6N

USB_HSD1P
USB_HSD1N

PS2_DAT/SDA4/GPIO187
PS2_CLK/CEC/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166

FCH-M3L NC pin

G12
F12

USB_HSD8P
USB_HSD8N

USB_HSD2P
USB_HSD2N

AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#

2 11.8K_0402_1%

K10
J12

B11
D11

USB_HSD3P
USB_HSD3N

BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#

R154 1

H10
G10

USB_HSD9P
USB_HSD9N

USB_HSD7P
USB_HSD7N

USB_RCOMP

1
1
1
1

2
2
2
2

USB30_FTX_DRX_P1 <34>
USB30_FTX_DRX_N1 <34>

LP2

USB30_FRX_DTX_P1 <34>
USB30_FRX_DTX_N1 <34>
USB30_FTX_DRX_P0 <34>
USB30_FTX_DRX_N0 <34>

LP1

USB30_FRX_DTX_P0 <34>
USB30_FRX_DTX_N0 <34>

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

EC_PWM2

EC_PWM2 <14>

strap pin

K21
K22
F22
F24
E24
B23
C24
F18

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38


GPIO189
GPIO190

BOARD
Config.
10K_0402_5%
R683

R168 1

10K_0402_5%
R685
2 UMA@ 1

2 UMA@ 1
FCH_SMCLK1

PX@ 1

2 10K_0402_5%

R166 1

10K_0402_5%
R682
PX@ 1
2

AB3
AB1
AA2
Y5
Y3
Y1
AD6
AE4

F21
E20
F20
A22
E18
A20
J18
H18
G18
B21
K18
D19
A18
C18
B19
B17
A24
D17

PX@

+3VALW +3VALW

R182 1 PX@

CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#/VGA_PD
GBE_LED0/GPIO183
SPI_HOLD#/GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#

FCH_SMCLK0

H6
H5

USB_SS_RX1P
USB_SS_RX1N

+3VS

R172

USB_FSD0P/GPIO185
USB_FSD0N

USB_SS_RX3P
USB_SS_RX3N
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0

EC_LID_OUT#

R171

H1
H3

RSMRST#

H_THERMTRIP#

R164
3

USB_OC3#
USB_OC2#
USB_OC1#
USB_OC0#

M7
R8
T1
P6
F5
P5
J7
T8

B9

USB_FSD1P/GPIO186
USB_FSD1N

USB_HSD12P
USB_HSD12N

USB 3.0

R179 1

AG24
AE24
AE26
AF22
AH17
AG18
AF24
AD26
AD25
T7
R7
AG25
AG22
J2
AG26
V8
W8
Y6
V10
AA8
AF25

G8

USB_RCOMP

USB_HSD10P
USB_HSD10N

HD AUDIO

+3VALW

TEST0
TEST1/TMS
TEST2

AE22

R155 1

+3VALW

T9
T10
V9

USBCLK/14M_25M_48M_OSC

USB 2.0

TEST0
TEST1
TEST2

ACPI / WAKE UP EVENTS

FCH_PWRGD

GPIO

<30> PM_SLP_S3#
<30> PM_SLP_S5#
<30> PBTN_OUT#
<30,44> FCH_PWRGD

PCIE_RST2#/PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD

USB OC

AB6
R2
W7
T3
W2
J4
N7

<30> EC_LID_OUT#

USB MISC

HUDSON-2
T17

GPIO189

GPIO190

Function

PX4 Full

PX4 low

UMA Low

UMA Full

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C

Title

FCH-ACPI/USB/HDA/GPIO
Size Document Number
Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet
E

12

of

48

+3VS

1007mA

PCI/GPIO I/O

CORE S0
CLKGEN I/O
PCI EXPRESS
SERIAL ATA

MAIN LINK
GBE LAN

22U_0603_6.3V6M

3.3V_S5 I/O

22U_0603_6.3V6M

C193

1U_0402_6.3V6K

2.2U_0402_6.3V6M

C209

USB

10U_0603_6.3V6M

C177

C206

1U_0402_6.3V6K

C205

USB SS

220 ohm

26mA
AA4

1
R198

0.1U_0402_16V7K

VDDIO_AZ_S

L14
1
2
MBK1608221YZF_2P

2
0_0402_5%

AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.

+3VS

+VDDIO_AZ
C236 1

1
2
R200
0_0402_5%
2 2.2U_0402_6.3V6M

VDDIO_AZ_S should be tied to


+3.3/1.5V_S5 rail if Wake on Ring
is supported
4

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

2
0_0603_5%

+3VALW

C233

0.1U_0402_16V7K

C240

+VDDXL_3.3V
Tie to +3.3V_S5 rail if USB3 Wake
is supported; otherwise, tie to
+3.3V_S0 rail.
Hudson-2 designs: Tie to +3.3V_S0
rail.

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38


0.1U_0402_16V7K

C239

1U_0402_6.3V6K

C238

42 ohm/4A

+VDDCR_11_SSUSB
10U_0603_6.3V6M

1 R201
2
0_0603_5%

1
R197

+VDDAN_33_HWM

VDDCR_11_SSUSB_S_1
VDDCR_11_SSUSB_S_2
VDDCR_11_SSUSB_S_3
VDDCR_11_SSUSB_S_4

M8
2.2U_0402_6.3V6M

2
0_0402_5%

+3VALW

0.1U_0402_16V7K

C228

VDDAN_33_HWM_S

C232

L15

+3VALW

L9
1
2
MBK1608221YZF_2P

1U_0402_6.3V6K

C222

2.2U_0402_6.3V6M

FBMA-L11-201209-221LMA30T_0805

+1.1VS
42ohm @ 100MHz
1
2
R191
0_0805_5%

+1.1VS
42ohm @ 100MHz
1
2
R194
0_0805_5%

1
R195

+VDDPL_11_SYS_S

J24
C226

+1.1VALW

12mA
VDDAN_11_SSUSB_S_1
VDDAN_11_SSUSB_S_2
VDDAN_11_SSUSB_S_3
VDDAN_11_SSUSB_S_4
VDDAN_11_SSUSB_S_5

424mA
N16
N17
P17
M17

1U_0402_6.3V6K

C221

0.1U_0402_16V7K

C231

0.1U_0402_16V7K

C230

2.2U_0402_6.3V6M

C217

0.1U_0402_16V7K

C216

1U_0402_6.3V6K

C215
2

+1.1VALW

POWER

C237

VDDPL_11_SYS_S

+1.1VS
42ohm @ 100MHz
1
2
R187
0_0603_5%

220 ohm

70mA

VDDCR_11_USB_S_1
VDDCR_11_USB_S_2

P16
M14
N14
P13
P14

2
0_0805_5%

+1.1VALW

42mA

0.1U_0402_16V7K

2.2U_0402_6.3V6M

C227

1U_0402_6.3V6K

+3VS

220 ohm

+VDDCR_1.1V

T12
T13

187mA
N20
M20

+VDDAN_11_SSUSB
C229

1 R199
2
0_0603_5%

VDDCR_11_S_1
VDDCR_11_S_2

+VDDXL_3.3V

282mA

2
L12
+VDDPL_33_SATA
1
2
MBK1608221YZF_2P

1U_0402_6.3V6K

C225

0.1U_0402_16V7K

40mils

VDDAN_11_USB_S_1
VDDAN_11_USB_S_2

G24

+FCH_VDD_11_SSUSB_S

2.2U_0402_6.3V6M

C218

U12
U13

5mA
VDDXL_33_S

+VDDIO_33_S

Add C234 follow AMD


reccommandation 10/28

C224

L10
+VDDPL_33_PCIE
1
2
MBK1608221YZF_2P

10U_0603_6.3V6M

C223

VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12

140mA

+VDDCR_11V_USB

220 ohm

+3VS

220 ohm

0.1U_0402_16V7K

L13
1
2
MBK1608221YZF_2P

C234
0.1U_0402_16V7K

+1.1VALW

C220

2.2U_0402_6.3V6M

C219

0.1U_0402_16V7K

C211

2.2U_0402_6.3V6M

C210

+VDDAN_11_USB_S

220 ohm

220 ohm

L11

+VDDAN_33_USB

G7
H8
J8
K8
K9
M9
M10
N9
N10
M12
N12
M11

+1.1VALW
1
2
MBK1608221YZF_2P

L7
+VDDPL_33_USB_S
1
2
MBK1608221YZF_2P

C214

10U_0603_6.3V6M

C213

0.1U_0402_16V7K

C200

2.2U_0402_6.3V6M

220 ohm

C198

L6
1
2 +VDDPL_33_SSUSB_S
MBK1608221YZF_2P

C212

220 ohm/2A

10U_0603_6.3V6M

1
2
FBMA-L11-201209-221LMA30T_0805

+3VALW

VDDIO_GBE_S_1
VDDIO_GBE_S_2

470mA

+VDDAN_33_USB

N18
L19
M18
V12
V13
Y12
Y13
W11

1U_0402_6.3V6K

L8

1U_0402_6.3V6K

AA9
AA10

C208

2
0_0402_5%

VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8

+AVDD_SATA

59mA

VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2

1U_0402_6.3V6K

1
R196

VDDIO_33_GBE_S

AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19

C207

AB11
AA11

C204

AB10

0.1U_0402_16V7K

VDDAN_11_ML_1
VDDAN_11_ML_2
VDDAN_11_ML_3
VDDAN_11_ML_4

+3VALW

VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10

+VDDAN_11_PCIE

C203

Y22
V23
V24
V25

+VDDAN_11_PCIE

1337mA

226mA

1U_0402_6.3V6K

VDDPL_11_DAC

22U_0603_6.3V6M

V21

C197

LDO_CAP

AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27

1U_0402_6.3V6K

VDDPL_33_SATA

7mA

demo board connect to GND

del +FCH_VDDAN_33_DAC power plane

VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8

VDDPL_33_PCIE

C196

AG28
2
M31
2.2U_0603_6.3V4Z

1088mA

VDDPL_33_USB_S

@
1
C194

0.1U_0402_16V7K

12mA

+VDDPL_33_SATA

VDDPL_33_SSUSB_S

C195

LDO_CAP: Internally generated 1.8V


supply for the RGB outputs

AH29

C192

11mA

+VDDPL_33_PCIE

1U_0402_6.3V6K

D7

VDDAN_33_DAC

C186

L18

14mA

VDDPL_33_ML

C191

11mA

+VDDPL_33_SSUSB_S
+VDDPL_33_USB_S

VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8

0.1U_0402_16V7K

T22

VDDPL_33_DAC

+1.1VS_CKVDD
C190

U22

30mA

VDDPL_33_SYS

0.1U_0402_16V7K

VDDPL_33_SSUSB_S
For Hudson3 USB3.0 only
For Hudson2, connect to GND

V22

12mA

1
R184

+1.1VS_CKVDD

340mA
C189

demo board connect to GND

20mA

H26
J25
K24
L22
M22
N21
N22
P22

1U_0402_6.3V6K

H24

+VDDPL_33_SYS

C185

47mA

del +VDDPL_33_MLDAC power plane

T14
T17
T20
U16
U18
V14
V17
V20
Y17

0.1U_0402_16V7K

VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9

C184

VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10

0.1U_0402_16V7K

C183

AB17
AB18
AE9
AD10
AG7
AC13
AB12
AB13
AB14
AB16

0.1U_0402_16V7K

C179

0.1U_0402_16V7K

C187

0.1U_0402_16V7K

C178

+VCC_VDDCR_11

HUDSON-2

102mA

+VDDIO_33_PCIGP

2
0_0603_5%

22U_0603_6.3V6M

1
R185

+3VS

C176

0.1U_0402_16V7K

C182

2.2U_0402_6.3V6M

220 ohm

+1.1VS

U2C
+VDDPL_33_SYS
C181

L4
1
2
MBK1608221YZF_2P

Title

FCH PWR
Size Document Number
Custom
Date:

Rev
0.1

LA8681P

Tuesday, November 29, 2011

Sheet
E

13

of

48

DEBUG STRAPS
STRAP PINS
NON_FUSION
CLOCK MODE

EC
ENABLED

DEFAULT

EC_PWM2

RTC_CLK

CLKGEN
ENABLED

LPC ROM

S5 PLUS
MODE
DISABLED

1
@
2

1
2

+3VALW

+3VALW

+3VALW

PULL
LOW

PCI_AD26

PCI_AD25

PCI_AD24

PCI_AD23

USE PCI
PLL

DISABLE
ILA
AUTORUN

USE FC
PLL

USE DEFAULT
PCIE STRAPS

DISABLE PCI
MEM BOOT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

DEFAULT

BYPASS
PCI PLL

ENABLE
ILA
AUTORUN

BYPASS
FC PLL

USE EEPROM
PCIE STRAPS

ENABLE PCI
MEM BOOT

+3VALW
R208 10K_0402_5%

+3VS

R207 10K_0402_5%

+3VS

R206 10K_0402_5%

+3VS

S5 PLUS
MODE
ENABLED

PCI_AD27

DEFAULT

DEFAULT

SPI ROM

DEFAULT

DEFAULT

PULL
HIGH

DEFAULT

CLKGEN
DISABLE

EC
DISABLED

FUSION
CLOCK
MODE

IGNORE
DEBUG
STRAP

FORCE
PCIE GEN1

PULL
LOW

LPC_CLK1

DEFAULT

<10> PCI_AD27
C

<10> PCI_AD26
<10> PCI_AD25

<10> PCI_CLK1
<10> PCI_AD24
<10> PCI_CLK3
<10> PCI_AD23

1
@
2

1
2

1
2
1
2

1
2

1
2

1
2

1
2

1
2

R213 2.2K_0402_5%

R212 2.2K_0402_5%

R220 2.2K_0402_5%

R219 2.2K_0402_5%

R218 10K_0402_5%

R211 2.2K_0402_5%

<12> EC_PWM2
<10,30> RTC_CLK

R210 2.2K_0402_5%

<10> LPC_CLK1

R209 2.2K_0402_5%

<10,30> CLK_PCI_EC

<10> PCI_CLK4

R217 10K_0402_5%

EFUSE

USE
DEBUG
STRAPS

LPC_CLK0_EC

R205 10K_0402_5%

VSSPL_SYS

ALLOW
PCIE GEN2

PCI_CLK4

R216 10K_0402_5%

H25

VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC

PCI_CLK3

R204 10K_0402_5%

VSSXL

PCI_CLK1

R215 10K_0402_5%

VSSAN_HWM

PULL
HIGH

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

R203 10K_0402_5%

N8
K25

T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33

R214 10K_0402_5%

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

R202 10K_0402_5%

GROUND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

HUDSON-2
A3
A33
B7
B13
D9
D13
E5
E12
E16
E29
F7
F9
F11
F13
F16
F17
F19
F23
F25
F29
G6
G16
G32
H12
H15
H29
J6
J9
J10
J13
J28
J32
K7
K16
K27
K28
L6
L12
L13
L15
L16
L21
M13
M16
M21
M25
N6
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R4
R11
R25
R28
T11
T16
T18

U2E

T21
L28
K33
N28
R6

S IC 218-0755091 A13 HUDSON-M3L FCBGA 656P C38


A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/10/12

Deciphered Date

2013/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

FCH-VSS/Strap
Size
B
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet
1

14

of

48

PCIE_CTX_GRX_P[3..0]

<6> PCIE_CTX_GRX_P[3..0]

PCIE_CRX_GTX_P[3..0]

U6A PX@

PCIE_CTX_GRX_N[3..0]

<6> PCIE_CTX_GRX_N[3..0]

PCIE_CRX_GTX_P[3..0] <6>

PCIE_CRX_GTX_N[3..0]

LVDS Interface

PCIE_CRX_GTX_N[3..0] <6>

PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0

AA38
Y37

PCIE_RX0P
PCIE_RX0N

PCIE_TX0P
PCIE_TX0N

Y33
Y32

PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

1 C241 PX@
1 C242 PX@

PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0

PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1

Y35
W36

PCIE_RX1P
PCIE_RX1N

PCIE_TX1P
PCIE_TX1N

W33 PCIE_CRX_C_GTX_P1
W32 PCIE_CRX_C_GTX_N1

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

1 C243 PX@
1 C244 PX@

PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1

PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2

W38
V37

PCIE_RX2P
PCIE_RX2N

PCIE_TX2P
PCIE_TX2N

U33 PCIE_CRX_C_GTX_P2
U32 PCIE_CRX_C_GTX_N2

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

1 C245 PX@
1 C246 PX@

PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2

PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3

V35
U36

PCIE_RX3P
PCIE_RX3N

PCIE_TX3P
PCIE_TX3N

U30 PCIE_CRX_C_GTX_P3
U29 PCIE_CRX_C_GTX_N3

0.1U_0402_16V7K
0.1U_0402_16V7K

2
2

1 C247 PX@
1 C248 PX@

PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3

U38
T37

PCIE_RX4P
PCIE_RX4N

PCIE_TX4P
PCIE_TX4N

T33
T32

T35
R36

PCIE_RX5P
PCIE_RX5N

PCIE_TX5P
PCIE_TX5N

T30
T29

R38
P37

PCIE_RX6P
PCIE_RX6N

PCIE_TX6P
PCIE_TX6N

P33
P32

P35
N36

PCIE_RX7P
PCIE_RX7N

PCIE_TX7P
PCIE_TX7N

P30
P29

N38
M37

PCIE_RX8P
PCIE_RX8N

PCIE_TX8P
PCIE_TX8N

N33
N32

M35
L36

PCIE_RX9P
PCIE_RX9N

PCIE_TX9P
PCIE_TX9N

N30
N29

L38
K37

PCIE_RX10P
PCIE_RX10N

PCIE_TX10P
PCIE_TX10N

L33
L32

K35
J36

PCIE_RX11P
PCIE_RX11N

PCIE_TX11P
PCIE_TX11N

L30
L29

J38
H37

PCIE_RX12P
PCIE_RX12N

PCIE_TX12P
PCIE_TX12N

K33
K32

H35
G36

PCIE_RX13P
PCIE_RX13N

PCIE_TX13P
PCIE_TX13N

J33
J32

G38
F37

PCIE_RX14P
PCIE_RX14N

PCIE_TX14P
PCIE_TX14N

K30
K29

F35
E37

PCIE_RX15P
PCIE_RX15N

PCIE_TX15P
PCIE_TX15N

H33
H32

U6G PX@

<12,17,43> VGA_PWRGD

R221 2

R224 2 PX@
1
10K_0402_5%
GPU_RST#

AH16

CALIBRATION
PCIE_CALRP

Y30

1.27K_0402_1% 1 PX@

2 R223

PCIE_CALRN

Y29

2K_0402_1% 1 PX@

2 R225

PERSTB

PX@
ROBSON XT M2
R226
100K_0402_5%

TXOUT_U1P_DPF1P
TXOUT_U1N_DPF1N

AH35
AJ36

TXOUT_U2P_DPF0P
TXOUT_U2N_DPF0N

AG38
AH37

TXOUT_U3P
TXOUT_U3N

AF35
AG36
C

Issued Date

AP34
AR34

TXOUT_L0P_DPE2P
TXOUT_L0N_DPE2N

AW37
AU35

TXOUT_L1P_DPE1P
TXOUT_L1N_DPE1N

AR37
AU39

TXOUT_L2P_DPE0P
TXOUT_L2N_DPE0N

AP35
AR35

TXOUT_L3P
TXOUT_L3N

AN36
AP37

1 0_0402_5%

U7

GPU_RST#

PX@
MC74VHC1G08DFT2G SC70 5P
A

Compal Electronics, Inc.

Compal Secret Data


2011/10/12

Deciphered Date

2013/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N

+1.0VGS

Security Classification

AA30

5
<10,29> APU_PCIE_RST#

PWRGOOD

AJ38
AK37

+3VGS

<12> PXS_RST#

TXOUT_U0P_DPF2P
TXOUT_U0N_DPF2N

PCIE_REFCLKP
PCIE_REFCLKN

0_0402_5%
1

AK35
AL36

ROBSON XT M2

R222
@
2

TXCLK_UP_DPF3P
TXCLK_UN_DPF3N

LVTMDP

CLOCK
CLK_PCIE_VGA AB35
CLK_PCIE_VGA# AA36

<10> CLK_PCIE_VGA
<10> CLK_PCIE_VGA#

VARY_BL
DIGON

AK27
AJ27

PCI EXPRESS INTERFACE

LVDS CONTROL

ATI_RobsonXT_M2_PCIE/LVDS
Size
B
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet
1

15

of

48

CONFIGURATION STRAPS

U6B

ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE


GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET

I2C

R
RB

R232 GPU_GPIO5

10K_0402_5%
10K_0402_5%

1
1

@
@

2
2

R234 GPU_GPIO8
R236 GPU_GPIO9

10K_0402_5%
10K_0402_5%
10K_0402_5%

1 PX@
@
1
@
1

2
2
2

R237 GPU_GPIO11
R239 GPU_GPIO12
R240 GPU_GPIO13

GPU_GPIO11
GPU_GPIO12
GPU_GPIO13

RB751V_SOD323
D2 @ 1

<30,38> ACIN

2
T49

GPU_VID0
GPIO_16

<43> GPU_VID0
T50
R241 1 @

2 10K_0402_5%
GPU_VID1
GPIO21_BBEN

<43> GPU_VID1
+3VGS

T51
10K_0402_5%
10K_0402_5%
10K_0402_5%

1
1
1

@
@
@

2 R242
2 R243
2 R244

GPIO24_TRSTB
GPIO25_TDI
GPIO27_TMS

10K_0402_5%

2 R245

GPIO26_TCK

PEG_CLKREQ#
GPIO24_TRSTB
GPIO25_TDI
GPIO26_TCK
GPIO27_TMS
GPIO28_TDO

<12> PEG_CLKREQ#

T52

AK24

GPIO_0
GPIO_1
GPIO_2
GPIO_3_SMBDATA
GPIO_4_SMBCLK
GPIO_5_AC_BATT
GPIO_6
GPIO_7_BLON
GPIO_8_ROMSO
GPIO_9_ROMSI
GPIO_10_ROMSCK
GPIO_11
GPIO_12
GPIO_13
GPIO_14_HPD2
GPIO_15_PWRCNTL_0
GPIO_16
GPIO_17_THERMAL_INT
GPIO_18_HPD3
GPIO_19_CTF
GPIO_20_PWRCNTL_1
GPIO_21_BB_EN
GPIO_22_ROMCSB
GPIO_23_CLKREQB
JTAG_TRSTB
JTAG_TDI
JTAG_TCK
JTAG_TMS
JTAG_TDO
GENERICA
GENERICB
GENERICC
GENERICD
GENERICE_HPD4
GENERICF_HPD5
GENERICG_HPD6

G
GB
B
BB

DAC1

HSYNC
VSYNC
RSET
AVDD
AVSSQ
VDD1DI
VSS1DI
R2/NC
R2B/NC
G2/NC
G2B/NC
B2/NC
B2B/NC
C/NC
Y/NC
COMP/NC

+DPLL_PVDD

H2SYNC/GENLK_CLK
V2SYNC/GENLK_VSYNC

HPD1

AH13

A2VDD/NC
A2VDDQ/NC
VREFG
A2VSSQ/TSVSSQ

1 249_0402_1%

2
1
C279 0.1U_0402_16V7K
PX@

+VREFG_GPU

1 499_0402_1%

+DPLL_PVDD AM32
AN32
+DPLL_VDDC AN31
XTALIN
XTALOUT

AV33
AU34

R2SET/NC

PLL/CLOCK
DPLL_VDDC

AW34
+DPLL_VDDC

XTALIN
Voltage Swing: 1.8 V

0.1U_0402_16V7K
PX@
C287

1U_0402_6.3V6K
PX@
C285

10U_0603_6.3V6M
PX@
C284

125mA
1

AW35

DDC2CLK
DDC2DATA
XO_IN
AUX2P
AUX2N

XO_IN2

DDCCLK_AUX3P
DDCDATA_AUX3N

AF29
AG29

DPLUS
DMINUS

THERMAL

TS_FDO

T58

AK32

R254

+1.8VGS

1
2
BLM15BD121SN1D_0402

(1.8V@20mA TSVDD)
+TSVDD
1

27MHZ_16PF_X5H027000FG1H
C292 PX@
18P_0402_50V8J

AJ32
AJ33

PX@
C290
0.1U_0402_16V4Z

PX@
L20

PX@
C289
1U_0402_6.3V6K

1M_0402_5%
Y2 PX@
2
1

PX@
C291
18P_0402_50V8J

AL31

XTALIN

PX@
C288
10U_0603_6.3V6M

PX@

TS_FDO
DDC6CLK
DDC6DATA

TS_A/NC

DDCCLK_AUX7P
DDCDATA_AUX7N

TSVDD
TSVSS

ROBSON XT M2

DDCCLK_AUX4P
DDCDATA_AUX4N
DDCCLK_AUX5P
DDCDATA_AUX5N

XTALOUT

DDC1CLK
DDC1DATA
AUX1P
AUX1N

XTALIN
XTALOUT

+1.0VGS
L19 PX@
2
1
BLM15BD121SN1D_0402

H2SYNC

AU20
AT19

RSVD

GENERICC

AT21
AR20

AUD[1]

HSYNC

AUD[0]

VSYNC

AU22
AV21

+3VGS

@
R250
10K_0402_5%

AF37
AE38

AC36
AC38
AB34

R238 1 PX@

AD34
AE34

+AVDD

AC33
AC34

+VDD1DI

2
L16 PX@
BLM15BD121SN1D_0402

GPIO21

H2SYNC

GENERICC

GPIO2

2 499_0402_1%

TX_PWRS_ENB

Transmitter Power Saving Enable


GPIO0 0: 50% Tx output swing for mobile mode
1: full Tx output swing (Default setting for Desktop)

TX_DEEMPH_EN

PCI Express Transmitter De-emphasis Enable


GPIO1 0: Tx de-emphasis diabled for mobile mode
1: Tx de-emphasis enabled (Defailt setting for desktop)

(1.8V@65mA AVDD)
(1.8V@100mA VDD1DI) 1

AC30
AC31

AD30
AD31

2
+1.8VGS
L17 PX@
BLM15BD121SN1D_0402

1
+3VGS
2

AF30
AF31

R246
10K_0402_5%
AC32
AD32
AF32

+VDD2DI
GENLK_CLK
GENLK_VSYNC

AG31
AG32

+VDD2DI

AG33

+A2VDD

AD33

+A2VDDQ

+1.8VGS
Robson@L28
1
2
BLM15BD121SN1D_0402

2mA

T53
T54

Internal VGA Thermal Sensor


+3VGS
R247
10K_0402_5%

VGA_SMB_CK2

+A2VDD

AF33

VGA_SMB_DA2

Q17A
DMN66D0LDW-7_SOT363-6
4

EC_SMB_CK2

<5,29,30>
B

EC_SMB_DA2

<5,29,30>

PX@
Q17B
DMN66D0LDW-7_SOT363-6

+3VGS
Robson@L41
1
2
BLM15BD121SN1D_0402

100mA
R330 1 Robson@2
715_0402_1%

1
PX@

Robson@ Robson@ Robson@


2
2
2

Robson@ Robson@ Robson@


2
2
2

AM26
AN26
AM27
AL27
AM19
AL19

+A2VDDQ

+1.8VGS
Robson@L27
1
2
BLM15BD121SN1D_0402

130mA

AN20
AM20
AL30
AM30

Robson@ Robson@ Robson@


2
2
2

AL29
AM29
AN21
AM21

AJ30
AJ31
AK30
AK29

Compal Electronics, Inc.

Compal Secret Data

Security Classification

PX@

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

GPIO8

Title

ATI_RobsonXT_M2_Main_MSIC
Size
C
Date:

11

ALLOW FOR PULLUP PADS FOR THESE STRAPS BUT DO NOT INSTALL
RESISTOR. IF THESE GPIOS ARE USED, THEY MUST KEEP "LOW" AND
NOT CONFLICT DURING RESET

+1.8VGS

@
R265
10K_0402_5%

AE36
AD35

AA29

0
AUD[1] AUD[0]
0 0 No audio function
0 1 Audio for DisplayPort and HDMI if dongle is detected
1 0 Audio for DisplayPort only
1 1 Audio for both DisplayPort and HDMI

AMD RESERVED CONFIGURATION STRAPS

AD39
AD37

AD29
AC29

+3VGS

AT23
AR22

DPLL_PVDD
DPLL_PVSS
DDC/AUX

RSVD

C437

PX@
2 R248
PX@
2 R249

0.1U_0402_16V7K
PX@
C282

1U_0402_6.3V6K
PX@
C281

75mA
10U_0603_6.3V6M
PX@
C280

L18 PX@
2
1
BLM15BD121SN1D_0402

AT17
AR16

DAC2

VDD2DI/NC
VSS2DI/NC

+1.8VGS

IGNORE VIP DEVICE STRAPS

VIP_DEVICE_STRAP_ENA

0.60 V level, Please


VREFG Divider ans
cap close to ASIC

+1.8VGS

XXX

V2SYNC

AU16
AV15

0
0: disable
1: enable

AH20
AH18
AN16
AH23
AJ23
AH17
AJ17
AK17
AJ13
AH15
AJ16
AK16
AL16
AM16
AM14
AM13
AK14
AG30
AN14
AM17
AL13
AJ14
AK13
AN13
AM23
AN23
AK23
AL24
AM24
AJ19
AK19
AJ20
AK20
AJ24
AH26
AH24

SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT

10K_0402_5%

GPU_GPIO0
GPU_GPIO1
GPU_GPIO2
VGA_SMB_DA2
VGA_SMB_CK2
GPU_GPIO5
GPU_GPIO_6
R02
GPU_GPIO8
GPU_GPIO9

GPIO[13:11]

R229 GPU_GPIO0
R230 GPU_GPIO1
R231 GPU_GPIO2

ROMIDCFG(2:0)

GENERAL PURPOSE I/O


@
1
2
1 PX@
2
1 PX@
2
R1.0

AT15
AR14

SCL
SDA

10K_0402_5%
10K_0402_5%
10K_0402_5%

ENABLE EXTERNAL BIOS ROM

0.1U_0402_16V7K
PX@
C1033

STRAPS
+3VGS

TX5P_DPD0P
TX5M_DPD0N

GPIO_22_ROMCSB

AK26
AJ26

BIOS_ROM_EN

TX4P_DPD1P
TX4M_DPD1N

AU14
AV13

DPD

RESERVED

SWAPLOCKA
SWAPLOCKB

GPIO21

10U_0603_6.3V6M

TX3P_DPD2P
TX3M_DPD2N

RSVD

10U_0603_6.3V6M

TXCDP_DPD3P
TXCDM_DPD3N

AT33
AU32

10U_0603_6.3V6M

TX2P_DPC0P
TX2M_DPC0N

VGA ENABLED

10U_0603_6.3V6M
PX@
C273

TX1P_DPC1P
TX1M_DPC1N

RESERVED

GPIO9

10U_0603_6.3V6M
PX@
C278

DPC

GPIO8

BIF_VGA DIS

1U_0402_6.3V4Z
C429

TX0P_DPC2P
TX0M_DPC2N

RSVD

AR32
AT31

1U_0402_6.3V4Z
C380

TXCCP_DPC3P
TXCCM_DPC3N

AV31
AU30

1U_0402_6.3V4Z
C436

TX5P_DPB0P
TX5M_DPB0N

0: 2.5GT/s
1: 5GT/s

RSVD

1U_0402_6.3V6K
PX@
C274

TX4P_DPB1P
TX4M_DPB1N

Advertises PCIE speed


when compliance test

AR30
AT29

1U_0402_6.3V6K
PX@
C277

DPB

GPIO2

GPIO1

0.1U_0402_10V6K
C435

TX3P_DPB2P
TX3M_DPB2N

0: disable
1: enable

GPIO0

TX_DEEMPH_EN

0.1U_0402_16V7K
PX@
C276

AJ21
AK21

TXCBP_DPB3P
TXCBM_DPB3N

PCIE FULL TX OUTPUT SWING


PCIE TRANSMITTER DE-EMPHASIS

TX_PWRS_ENB

AT27
AR26

C434

<20> VRAM_ID0
<20> VRAM_ID1
<20> VRAM_ID2

TX2P_DPA0P
TX2M_DPA0N

RECOMMENDED
SETTINGS

DESCRIPTION OF DEFAULT SETTINGS


0: 50% swing
1: Full swing

C430

DVPCNTL_MVP_0
DVPCNTL_MVP_1
DVPCNTL_0
DVPCNTL_1
DVPCNTL_2
DVPCLK
DVPDATA_0
DVPDATA_1
DVPDATA_2
DVPDATA_3
DVPDATA_4
DVPDATA_5
DVPDATA_6
DVPDATA_7
DVPDATA_8
DVPDATA_9
DVPDATA_10
DVPDATA_11
DVPDATA_12
DVPDATA_13
DVPDATA_14
DVPDATA_15
DVPDATA_16
DVPDATA_17
DVPDATA_18
DVPDATA_19
DVPDATA_20
DVPDATA_21
DVPDATA_22
DVPDATA_23

PIN

STRAPS

AU26
AV25

0.1U_0402_10V6K
C395

TX1P_DPA1P
TX1M_DPA1N
AR8
AU8
AP8
AW8
AR3
AR1
AU1
AU3
AW3
AP6
AW5
AU5
AR6
AW6
AU6
AT7
AV7
AN7
AV9
AT9
AR10
AW10
AU10
AP10
AV11
AT11
AR12
AW12
AU12
AP12

AT25
AR24

0.1U_0402_10V6K
C438

DPA

TX0P_DPA2P
TX0M_DPA2N

MUTI GFX

AU24
AV23

TXCAP_DPA3P
TXCAM_DPA3N

RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
1 = INSTALL 10K RESISTOR
X = DESIGN DEPENDANT
NA = NOT APPLICABLE

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

16

of

48

+5VS

+5VS

1.0V_ON#

PX@

C296
@
0.1U_0402_16V7K
1
2
U10
5

+1.0VGS

PX_MODE

1.0V_ON#

PX@
MC74VHC1G08DFT2G SC70 5P

Q22
PX@
AO3414_SOT23-3

+VGA_CORE

Q23
PX@
AO3414_SOT23-3
1

C294
22U_0805_6.3V6M

RUNPWROK
2

2
G

PX@ 2
R880
0_0402_5%

+BIF_VDDC

PX@
S

PXS_PWREN

55mA@1.0V, in BACO mode

PX_MODE <43>
G

@
R261
20K_0402_5%

Q19
PX@
AO3414_SOT23-3

2
+3VGS

Q18
PX@
AO3414_SOT23-3

2
G

+3VGS

Q24
2N7002K_SOT23-3
PX@

2
G

Q68A
DMN66D0LDW-7_SOT363-6

MC74VHC1G08DFT2G SC70 5P

<18> PX_EN

PX@

Q68B
DMN66D0LDW-7_SOT363-6

PX@
4

U9
Y

VDDC_ON#

R257
10K_0402_5%
PX@

+3VGS

PX@
1 R259
2
10K_0402_5%

VGA_PWRGD

R256
10K_0402_5%
PX@

<12,15,43>

0.1U_0402_16V7K
@ C293

+3VGS

@
C297
1U_0603_10V6K

VDDC_ON#

+1.8VS TO +1.8VGS

PXS_PWREN#1
@ R281
0_0402_5%

Q32 PX@
S 2N7002K_SOT23-3

2
G

PX@
R271

2
51K_0402_5%
PX@

S
2N7002K_SOT23-3

C357 PX@
0.1U_0603_25V7K

PXS_PWREN

R270

@ Q33

2
G

PXS_PWREN#1
@ R272
0_0402_5%

Q30 PX@
S 2N7002K_SOT23-3

2
G

R263
100K_0402_5%

PX@
C303
1U_0603_10V6K

@ R268

PX@
2

PX@
C302
10U_0603_6.3V6M

Q27
PX@
AP2301GN-HF_SOT23-3

20K_0402_5%
1

PX@2

47K_0402_5%

PXS_PWREN#

1R370

2MM

+5VALW

PX@

20K_0402_5%

470_0603_5%

R279

10U_0603_6.3V6M

PXS_PWREN#

470_0603_5%
Q26
DTC124EKAT146_SC59-3
D

@ Q29

2
G

@ R269

OUT

PX@
C399
1U_0603_10V6K

+VSB

1
2
3

PXS_PWREN 2

<12,43> PXS_PWREN

IN

2N7002K_SOT23-3

C304 PX@
0.1U_0603_25V7K

PX@

GND

8
7
6
5

PX@
C398
10U_0603_6.3V6M

PX@
C423

2MM
U13
PX@
AO4430L_SO8

+3VALW

+3VGS
J2

PX@
C375
10U_0603_6.3V6M

+3VS

+1.8VGS
J4
2

+1.8VS

+3.3VS TO +3.3VGS

+1.05VS TO +1.0VGS
+1.5V

+1.5VGS
+1.05VS

+1.0VGS
J7

PX_MODE#
1

PX@
R275
20K_0402_5%

PX@
R273
100K_0402_5%

2
2
G
0_0402_5% @ Q31
2N7002K_SOT23-3

2MM
U14
PX@
AO4430L_SO8

+VSB

R309

43K_0402_5%
1

R280
0_0402_5%
@

PX@
C308
0.1U_0603_25V7K

PXS_PWREN#1
@ R310
0_0402_5%

Q34 PX@
S 2N7002K_SOT23-3

2
G

PX@
C421
1U_0603_10V6K

@ R277
470_0603_5%

@ Q38

2
G
2N7002K_SOT23-3

C358 PX@
0.1U_0603_25V7K

PX@ PX@
Q69A
DMN66D0LDW-7_SOT363-6

R862 PX@
1
2
39K_0402_5%

PX@

PX@
C419
10U_0603_6.3V6M

PX@
PX_MODE# 2
Q69B
DMN66D0LDW-7_SOT363-6

1
2
3

20K_0402_5%

PXS_PWREN#

8
7
6
5

@
R274
470_0603_5%

R278

PX_MODE

@ R282
1

PX@
C307
1U_0603_10V6K

+VSB

10U_0603_6.3V6M

PX@
C306
10U_0603_6.3V6M

2
+3VALW

PX@
C376
1
2
3

1 2

C305
PX@

8
7
6
5

U12
PX@
AO4430L_SO8

10U_0603_6.3V6M

+1.5VS TO +1.5VGS

1
2MM

J9

PX@
R276
100K_0402_5%

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_RobsonXT_M2_BACO POWER
Size
C
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

17

of

48

U6F

+DPAB_VDD18

1.8V@300mA DPAB_VDD18)

+DPCD_VDD18
DP C/D POWER

DP A/B POWER

130mA
+DPCD_VDD18

@
2

DPAB/DPA_VDD18#1
DPAB/DPA_VDD18#2

+DPCD_VDD10

0_0402_5%
PX@

+DPAB_VDD10

AP13
AT13

AN17
AP16
AP17
AW14
AW16

DPCD/DPC_VDD10#1
DPCD/DPC_VDD10#2
DP/DPC_VSSR#1
DP/DPC_VSSR#2
DP/DPC_VSSR#3
DP/DPC_VSSR#4
DP/DPC_VSSR#5

DPAB/DPA_VDD10#1
DPAB/DPA_VDD10#2
DP/DPA_VSSR#1
DP/DPA_VSSR#2
DP/DPA_VSSR#3
DP/DPA_VSSR#4
DP/DPA_VSSR#5

+DPAB_VDD10

AP31
AP32

+1.0VGS

AN27
AP27
AP28
AW24
AW26

1 R285

0_0402_5%
1

PX@

+DPAB_VDD18

GND

+DPCD_VDD10

1 R286

AP22
AP23

+DPCD_VDD10

DPCD/DPD_VDD18#1
DPCD/DPD_VDD18#2

DPAB/DPB_VDD18#1
DPAB/DPB_VDD18#2

DPCD/DPD_VDD10#1
DPCD/DPD_VDD10#2

DPAB/DPB_VDD10#1
DPAB/DPB_VDD10#2

AP25 130mA
AP26

PX@

@ C320
0.1U_0402_16V7K

@ C318
10U_0603_6.3V6M

0_0402_5%

@ C319
1U_0402_6.3V6K

+DPCD_VDD10
C

(1.0V@220mA DPAB_VDD10)

+DPCD_VDD18

+1.0VGS

2 @

110mA

@
2

DPCD/DPC_VDD18#1
DPCD/DPC_VDD18#2

AN24
AP24

10U_0603_6.3V6M
C317

AP20
AP21

1U_0402_6.3V6K
C316

PX@

C310
0.1U_0402_16V7K

C313
10U_0603_6.3V6M

0_0402_5%

C314
1U_0402_6.3V6K

C315
0.1U_0402_16V7K

1 R284

C309
10U_0603_6.3V6M

U6H
+1.8VGS

+1.8VGS

1 R283
C312
1U_0402_6.3V6K

C311
0.1U_0402_16V7K

+DPAB_VDD18
1

+DPAB_VDD10
AP14
AP15

AN33 110mA
AP33

2
AN19
AP18
AP19
AW20
AW22

150_0402_1% 2 PX@

+1.8VGS

1 R287 AW18

DP/DPD_VSSR#1
DP/DPD_VSSR#2
DP/DPD_VSSR#3
DP/DPD_VSSR#4
DP/DPD_VSSR#5

DPCD_CALR

DP/DPB_VSSR#1
DP/DPB_VSSR#2
DP/DPB_VSSR#3
DP/DPB_VSSR#4
DP/DPB_VSSR#5

DPAB_CALR

AN29
AP29
AP30
AW30
AW32

AW28 R288 1 PX@

+DPEF_VDD18

150mA
@ C321
10U_0603_6.3V6M

0_0402_5%
PX@

+DPEF_VDD18

@ C323
0.1U_0402_16V7K

@ C322
1U_0402_6.3V6K

1 R289

AH34
AJ34

DP E/F POWER
DPEF/DPE_VDD18#1
DPEF/DPE_VDD18#2

+DPAB_VDD18
DPEF/DPE_VDD10#1
DPEF/DPE_VDD10#2

DPAB_VDD18/DPB_PVDD
DP_VSSR/DPB_PVSS

DP/DPE_VSSR#1
DP/DPE_VSSR#2
DP/DPE_VSSR#3
DP/DPE_VSSR#4

DPCD_VDD18/DPC_PVDD
DP_VSSR/DPC_PVSS

AF34
AG34

+DPEF_VDD10

DPEF_VDD18/DPE_PVDD
DP_VSSR/DPE_PVSS

20mA
@ C325
1U_0402_6.3V6K

@ C324
10U_0603_6.3V6M

@ C326
0.1U_0402_16V7K

+DPEF_VDD10

AK33
AK34

DPEF_VDD18/DPF_PVDD
DP_VSSR/DPF_PVSS
AF39
AH39
AK39
AL34
AM34

150_0402_1%

PX@ 1 R292

AM39

AV19
AR18

AM37
AN38
+DPEF_VDD18

DPEF/DPF_VDD10#1
DPEF/DPF_VDD10#2

AU18
AV17

+DPEF_VDD18

DPEF/DPF_VDD18#1
DPEF/DPF_VDD18#2

+DPEF_VDD10

AV29
AR28

+DPCD_VDD18
DPCD_VDD18/DPD_PVDD
DP_VSSR/DPD_PVSS

20mA
+1.0VGS

AU28
AV27

+DPCD_VDD18

PX@

DP PLL POWER
DPAB_VDD18/DPA_PVDD
DP_VSSR/DPA_PVSS

20mA
AL33
AM33

+DPEF_VDD18

0_0402_5%

2 150_0402_1%

+DPAB_VDD18

20mA

+DPEF_VDD10

AN34
AP39
AR39
AU37

1 R291

F15
F17
F19
F21
F23
F25
F27
F29
F31
F33
F7
F9
G2
G6
H9
J2
J27
J6
J8
K14
K7
L11
L17
L2
L22
L24
L6
M17
M22
M24
N16
N18
N2
N21
N23
N26
N6
R15
R17
R2
R20
R22
R24
R27
R6
T11
T13
T16
T18
T21
T23
T26
U15
U17
U2
U20
U22
U24
U27
U6
V11
V16
V18
V21
V23
V26
W2
W6
Y15
Y17
Y20
Y22
Y24
Y27
U13
V13

AL38
AM35

DP/DPF_VSSR#1
DP/DPF_VSSR#2
DP/DPF_VSSR#3
DP/DPF_VSSR#4
DP/DPF_VSSR#5

DPEF_CALR
ROBSON XT M2
PX@

GND#1
GND#2
GND#3
GND#4
GND#5
GND#6
GND#7
GND#8
GND#9
GND#10
GND#11
GND#12
GND#13
GND#14
GND#15
GND#16
GND#17
GND#18
GND#19
GND#20
GND#21
GND#22
GND#23
GND#24
GND#25
GND#26
GND#27
GND#28
GND#29
GND#30
GND#31
GND#32
GND#33
GND#34
GND#35
GND#36
GND#37
GND#38
GND#39
GND#40
GND#41
GND#42
GND#43
GND#44
GND#45
GND#46
GND#47
GND#48
GND#49
GND#50
GND#51
GND#52
GND#53
GND#54
GND#55
GND#56
GND#57
GND#58
GND#59
GND#60
GND/PX_EN#61
GND#62
GND#63
GND#64
GND#65
GND#66
GND#67
GND#68
GND#69
GND#70
GND#71
GND#72
GND#73
GND#74
GND#75
GND#76
GND#77
GND#78
GND#79
GND#80
GND#81
GND#82
GND#83
GND#84
GND#85
GND#86
GND#87
GND#88
GND#89
GND#90
GND#91
GND#92
GND#93
GND#94
GND#95
GND#96
GND#97
GND#98

GND#100
GND#101
GND#102
GND#103
GND#104
GND#105
GND#106
GND#107
GND#108
GND#109
GND#110
GND#111
GND#112
GND#113
GND#114
GND#115
GND#116
GND#117
GND#118
GND#119
GND#120
GND#121
GND#122
GND#123
GND#124
GND#125
GND#126
GND#127
GND#128
GND#129
GND#130
GND#131
GND#132
GND#133
GND#134
GND#135
GND#136
GND#137
GND#138
GND#139
GND#140
GND#141
GND#142
GND#143
GND#144
GND#145
GND#146
GND#147
GND#148
GND#149
GND#150
GND#151
GND#153
GND#154
GND#155
GND#156
GND#157
GND#158
GND#159
GND#160
GND#161
GND#163
GND#164
GND#165
GND#166
GND#167
GND#168
GND#169
GND#170
GND#171
GND#172
GND#173
GND#174
GND#175
GND#152
GND#162

VSS_MECH#1
VSS_MECH#2
VSS_MECH#3

A3
A37
AA16
AA18
AA2
AA21
AA23
AA26
AA28
AA6
AB12
AB15
AB17
AB20
AB22
AB24
AB27
AC11
AC13
AC16
AC18
AC2
AC21
AC23
AC26
AC28
AC6
AD15
AD17
AD20
AD22
AD24
AD27
AD9
AE2
AE6
AF10
AF16
AF18
AF21
AG17
AG2
AG20
AG22
AG6
AG9
AH21
AJ10
AJ11
AJ2
AJ28
AJ6
AK11
AK31
AK7
AL11
AL14
AL17
AL2
AL20
AL21
AL23
AL26
AL32
AL6
AL8
AM11
AM31
AM9
AN11
AN2
AN30
AN6
AN8
AP11
AP7
AP9
AR5
B11
B13
B15
B17
B19
B21
B23
B25
B27
B29
B31
B33
B7
B9
C1
C39
E35
E5
F11
F13

PX_EN <17>
1

PCIE_VSS#1
PCIE_VSS#2
PCIE_VSS#3
PCIE_VSS#4
PCIE_VSS#5
PCIE_VSS#6
PCIE_VSS#7
PCIE_VSS#8
PCIE_VSS#9
PCIE_VSS#10
PCIE_VSS#11
PCIE_VSS#12
PCIE_VSS#13
PCIE_VSS#14
PCIE_VSS#15
PCIE_VSS#16
PCIE_VSS#17
PCIE_VSS#18
PCIE_VSS#19
PCIE_VSS#20
PCIE_VSS#21
PCIE_VSS#22
PCIE_VSS#23
PCIE_VSS#24
PCIE_VSS#25
PCIE_VSS#26
PCIE_VSS#27
PCIE_VSS#28
PCIE_VSS#29
PCIE_VSS#30
PCIE_VSS#31
PCIE_VSS#32
PCIE_VSS#33
PCIE_VSS#34
PCIE_VSS#35

R290
4.7K_0402_5%
PX@
2

AB39
E39
F34
F39
G33
G34
H31
H34
H39
J31
J34
K31
K34
K39
L31
L34
M34
M39
N31
N34
P31
P34
P39
R34
T31
T34
T39
U31
U34
V34
V39
W31
W34
Y34
Y39

A39 MECH#1
AW1 MECH#2
AW39MECH#3

T55 PAD
T56 PAD
T57 PAD

ROBSON XT M2
PX@
A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_RobsonXT_M2_PWR_GND
Size
C
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

18

of

48

+1.8VGS
PX@ L21
2
1
MBK1608121YZF_0603

(1.8V@504mA PCIE_VDDR)

U6E

+PCIE_VDDR

+MPV18

L25 PX@
1
2
BLM15BD121SN1D_0402

0.1U_0402_16V7K
PX@
C405

Design
1
1
1

M20
M21
V12
U12

NC_VDDRHA
NC_VSSRHA
NC_VDDRHB
NC_VSSRHB

2
PLL

2
H7
H8

MPV18#1
MPV18#2

PX@
1
2
MCK1608471YZF 0603

(1.8V@75mA SPV18)

+SPV18 AM10

(120mA SPV10)

+SPV10

AN9

0.1U_0402_16V7K
PX@
C426

1U_0402_6.3V6K
PX@
C424

10U_0603_6.3V6M
PX@
C420

AN10

SPVSS

1
VOLTAGE
SENESE

2
<43> VCCSENSE_VGA

AF28
AG28

<43> VSSSENSE_VGA

AH29

FB_VDDC
FB_VDDCI
FB_GND

1U_0402_6.3V6K
PX@
C334

10U_0603_6.3V6M
PX@
C335

1U_0402_6.3V6K
PX@
C333

1U_0402_6.3V6K
PX@
C332

0.1U_0402_16V7K
PX@
C330

10U_0603_6.3V6M
PX@
C354

1U_0402_6.3V6K
@
C353

1U_0402_6.3V6K
PX@
C352

1U_0402_6.3V6K
PX@
C351

1U_0402_6.3V6K
PX@
C350

1U_0402_6.3V6K
PX@
C349

PCIE_VDDC
1u
10u

CRB
7
1

VDDC
1u
10u
22u

CRB
30
10
0

Design
5 (1@)
1

1U_0402_6.3V6K
PX@
C369

1U_0402_6.3V6K
PX@
C368

1U_0402_6.3V6K
PX@
C367

1U_0402_6.3V6K
PX@
C366

1U_0402_6.3V6K
PX@
C365

1U_0402_6.3V6K
PX@
C364

1U_0402_6.3V6K
PX@
C363

1U_0402_6.3V6K
PX@
C362

1U_0402_6.3V6K
PX@
C360

1U_0402_6.3V6K
PX@
C359

+VGA_CORE

Design
25
1
1

1U_0402_6.3V6K
PX@
C389

1U_0402_6.3V6K
PX@
C388

1U_0402_6.3V6K
PX@
C387

1U_0402_6.3V6K
PX@
C386

1U_0402_6.3V6K
PX@
C385

1U_0402_6.3V6K
PX@
C384

1U_0402_6.3V6K
PX@
C383

+VGA_CORE

+VGA_CORE

+BIF_VDDC

For non-BACO designs, connect BIF_VDDC to VDDC.


For BACO designs - see BACO reference schematics

VDDCI
1u
10u
22u

CRB
10
3
0

Design
9
2
1
B

+VGA_CORE

(GDDR3/DDR3 1.12V@4A VDDCI)


(GDDR5 1.12V@16A VDDCI)

SPV18
SPV10

AA15
AA17
AA20
AA22
AA24
AA27
AB16
AB18
AB21
AB23
AB26
AB28
AC17
AC20
AC22
AC24
AC27
AD18
AD21
AD23
AD26
AF17
AF20
AF22
AG16
AG18
AG21
AH22
AH27
AH28
M26
N24
N27
R18
R21
R23
R26
T17
T20
T22
T24
T27
U16
U18
U21
U23
U26
V17
V20
V22
V24
V27
Y16
Y18
Y21
Y23
Y26
Y28

+1.0VGS
L26

22U_0603_6.3V6M
PX@
C394

VDDR4#1
VDDR4#2
VDDR4#3
VDDR4#6

(M97, Broadway and Madison: 1.8V@150mA MPV18)

L24
PX@
1
2
MCK1608471YZF 0603

1U_0402_6.3V6K
PX@
C404

CRB
1
1
1

+1.8VGS

10U_0603_6.3V6M
PX@
C403

SPV10
0.1u
1u
10u

+1.8VGS

0.1U_0402_16V7K
PX@
C408

Design
1
1
1

1U_0402_6.3V6K
PX@
C407

CRB
1
1
1

10U_0603_6.3V6M
PX@
C406

SPV18
0.1u
1u
10u

AD12
AF11
AF12
AG11

VDDR4#4
VDDR4#5
VDDR4#7
VDDR4#8

Design
2
3
1

+1.0VGS

VDDCI#1
VDDCI#2
VDDCI#3
VDDCI#4
VDDCI#5
VDDCI#6
VDDCI#7
VDDCI#8
VDDCI#9
VDDCI#10
VDDCI#11
VDDCI#12
VDDCI#13
VDDCI#14
ISOLATED VDDCI#15
CORE I/O VDDCI#16
VDDCI#17
VDDCI#18
VDDCI#19
VDDCI#20
VDDCI#21
VDDCI#22

AA13
AB13
AC12
AC15
AD13
AD16
M15
M16
M18
M23
N13
N15
N17
N20
N22
R12
R13
R16
T12
T15
V15
Y13

22U_0603_6.3V6M
PX@
C425

CRB
2
3
1

(1.0V@1920mA PCIE_VDDC)
G30
G31
H29
H30
J29
J30
L28
M28
N28
R28
T28
U28

10U_0603_6.3V6M
PX@
C400

AF13
AF15
AG13
AG15

10U_0603_6.3V6M
PX@
C422

0.1U_0402_16V7K
PX@
C397

1U_0402_6.3V6K
PX@
C396

Design
1
1
1

+VDDR4

PCIE_VDDR
0.1u
1u
10u

1U_0402_6.3V6K
PX@
C418

PX@ L23
1
2
BLM15BD121SN1D_0402

1U_0402_6.3V6K
PX@
C417

+1.8VGS

VDDR3#1
VDDR3#2
VDDR3#3
VDDR3#4

1U_0402_6.3V6K
PX@
C381

I/O
AF23
AF24
AG23
AG24

1U_0402_6.3V6K
PX@
C379

0.1U_0402_16V7K
PX@
C374

1U_0402_6.3V6K
PX@
C414

VDD_CT#1
VDD_CT#2
VDD_CT#3
VDD_CT#4

1U_0402_6.3V6K
PX@
C378

AF26
AF27
AG26
AG27

1U_0402_6.3V6K
PX@
C413

LEVEL
TRANSLATION

1U_0402_6.3V6K
PX@
C377

1U_0402_6.3V6K
PX@
C412

VDDC#1
VDDC#2
VDDC#3
VDDC#4
VDDC#5
VDDC#6
VDDC#7
VDDC#8
VDDC#9
VDDC#10
VDDC#11
VDDC#12
VDDC#13
VDDC#14
VDDC#15
VDDC#16
VDDC#17
VDDC#18
VDDC#19
VDDC#20
VDDC#21
VDDC#22
VDDC#23
VDDC#24
VDDC#25
VDDC#26
VDDC#27
VDDC#28
VDDC#29
VDDC#30
VDDC#31
VDDC#32
VDDC/BIF_VDDC#33
VDDC#34
VDDC#35
VDDC#36
VDDC#37
VDDC#38
VDDC#39
VDDC#40
VDDC#41
VDDC/BIF_VDDC#42
VDDC#43
VDDC#44
VDDC#45
VDDC#46
VDDC#47
VDDC#48
VDDC#49
VDDC#50
VDDC#51
VDDC#52
VDDC#53
VDDC#54
VDDC#55
VDDC#56
VDDC#57
VDDC#58
CORE

1U_0402_6.3V6K
PX@
C411

1U_0402_6.3V6K
PX@
C373

1U_0402_6.3V6K
PX@
C372

1U_0402_6.3V6K
PX@
C371

Design
1
1

10U_0603_6.3V6M
PX@
C370

CRB
1
1

(1.8V@110mA VDD_CT)

+3VGS

1U_0402_6.3V6K
PX@
C393

VDDR4
0.1u
1u

+VDDC_CT

PX@ L22
1
2
BLM15BD121SN1D_0402

1U_0402_6.3V6K
PX@
C392

Design
3
1

+1.8VGS

PCIE_VDDC#1
PCIE_VDDC#2
PCIE_VDDC#3
PCIE_VDDC#4
PCIE_VDDC#5
PCIE_VDDC#6
PCIE_VDDC#7
PCIE_VDDC#8
PCIE_VDDC#9
PCIE_VDDC#10
PCIE_VDDC#11
PCIE_VDDC#12

1U_0402_6.3V6K
PX@
C356

AA31
AA32
AA33
AA34
V28
W29
W30
Y31
AB37

1U_0402_6.3V6K
PX@
C355

PCIE_VDDR#1
PCIE_VDDR#2
PCIE_VDDR#3
PCIE_VDDR#4
PCIE_VDDR#5
PCIE_VDDR#6
PCIE_VDDR#7
PCIE_VDDR#8
PCIE_VDDR/PCIE_PVDD

1U_0402_6.3V6K
PX@
C402

1U_0402_6.3V6K
PX@
C401

1U_0402_6.3V6K
PX@
C410

0.1U_0402_16V7K
PX@
C348

0.1U_0402_16V7K
PX@
C347

0.1U_0402_16V7K
PX@
C346

0.1U_0402_16V7K
PX@
C345

0.1U_0402_16V7K
PX@
C344

1U_0402_6.3V6K
PX@
C343

1U_0402_6.3V6K
PX@
C342

1U_0402_6.3V6K
PX@
C329

1U_0402_6.3V6K
PX@
C341

VDDR1#1
VDDR1#2
VDDR1#3
VDDR1#4
VDDR1#5
VDDR1#6
VDDR1#7
VDDR1#8
VDDR1#9
VDDR1#10
VDDR1#11
VDDR1#12
VDDR1#13
VDDR1#14
VDDR1#15
VDDR1#16
VDDR1#17
VDDR1#18
VDDR1#19
VDDR1#20
VDDR1#21
VDDR1#22
VDDR1#23
VDDR1#24
VDDR1#25
VDDR1#26
VDDR1#27
VDDR1#28
VDDR1#29
VDDR1#30
VDDR1#31
VDDR1#32
VDDR1#33
VDDR1#34

1U_0402_6.3V6K
PX@
C409

Design
1
3
1

CRB
3
1

CRB
2
2
1

Design
6
5
5

VDDR3
1u
10u

MPV18
0.1u
1u
10u

1U_0402_6.3V6K
PX@
C340

10U_0603_6.3V6M
PX@
C328

10U_0603_6.3V6M
PX@
C339

AC7
AD11
AF7
AG10
AJ7
AK8
AL9
G11
G14
G17
G20
G23
G26
G29
H10
J7
J9
K11
K13
K8
L12
L16
L21
L23
L26
L7
M11
N11
P7
R11
U11
U7
Y11
Y7

POWER

CRB
1
3
1

1U_0402_6.3V6K
PX@
C391

VDD_CT
0.1u
1u
10u

CRB
6
10
6

10U_0603_6.3V6M
PX@
C390

VDDR1
0.1u
1u
10u

10U_0603_6.3V6M
PX@
C327

10U_0603_6.3V6M
PX@
C338

10U_0603_6.3V6M
PX@
C337

220U_B2_2.5VM_R35
C336

PCIE

0.1U_0402_16V7K
PX@
C331

MEM I/O

1U_0402_6.3V6K
PX@
C361

For DDR3/GDDR5, MVDDQ = 1.5V

1U_0402_6.3V6K
PX@
C382

+1.5VGS

1U_0402_6.3V6K
PX@
C416

1U_0402_6.3V6K
PX@
C415

VDDCI and VDDC should have seperate regulators with a merge option on PCB
For Madison, Park, Capilano, Robson, Seymour and Whistler, VDDCI and VDDC can share one common regulator

ROBSON XT M2
PX@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_RobsonXT_M2_Power
Size
C
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

19

of

48

L18
L20

+1.5VGS
R299 1 @
R300 1 PX@
R301 1 @

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

L27
N12
AG12

R304 1 PX@
R302 1 @
R305 1 @

2 240_0402_1%
2 240_0402_1%
2 240_0402_1%

M12
M27
AH12

MAA0_0/MAA_0
MAA0_1/MAA_1
MAA0_2/MAA_2
MAA0_3/MAA_3
MAA0_4/MAA_4
MAA0_5/MAA_5
MAA0_6/MAA_6
MAA0_7/MAA_7
MAA1_0/MAA_8
MAA1_1/MAA_9
MAA1_2/MAA_10
MAA1_3/MAA_11
MAA1_4/MAA_12
MAA1_5/MAA_13_BA2
MAA1_6/MAA_14_BA0
MAA1_7/MAA_A15_BA1

WCKA0_0/DQMA_0
WCKA0B_0/DQMA_1
WCKA0_1/DQMA_2
WCKA0B_1/DQMA_3
WCKA1_0/DQMA_4
WCKA1B_0/DQMA_5
WCKA1_1/DQMA_6
WCKA1B_1/DQMA_7
GDDR5/DDR2/GDDR3
EDCA0_0/QSA_0/RDQSA_0
EDCA0_1/QSA_1/RDQSA_1
EDCA0_2/QSA_2/RDQSA_2
EDCA0_3/QSA_3/RDQSA_3
EDCA1_0/QSA_4/RDQSA_4
EDCA1_1/QSA_5/RDQSA_5
EDCA1_2/QSA_6/RDQSA_6
EDCA1_3/QSA_7/RDQSA_7

DDBIA0_0/QSA_0B/WDQSA_0
DDBIA0_1/QSA_1B/WDQSA_1
DDBIA0_2/QSA_2B/WDQSA_2
DDBIA0_3/QSA_3B/WDQSA_3
DDBIA1_0/QSA_4B/WDQSA_4
DDBIA1_1/QSA_5B/WDQSA_5
DDBIA1_2/QSA_6B/WDQSA_6
DDBIA1_3/QSA_7B/WDQSA_7
ADBIA0/ODTA0
ADBIA1/ODTA1
CLKA0
CLKA0B
CLKA1
CLKA1B
RASA0B
RASA1B
CASA0B
CASA1B
CSA0B_0
CSA0B_1
CSA1B_0
CSA1B_1

MVREFDA
MVREFSA

CKEA0
CKEA1

MEM_CALRN0
MEM_CALRN1
MEM_CALRN2

WEA0B
WEA1B

MEM_CALRP1
MEM_CALRP0
MEM_CALRP2

MAA0_8
MAA1_8

GDDR5

DQA0_0/DQA_0
DQA0_1/DQA_1
DQA0_2/DQA_2
DQA0_3/DQA_3
DQA0_4/DQA_4
DQA0_5/DQA_5
DQA0_6/DQA_6
DQA0_7/DQA_7
DQA0_8/DQA_8
DQA0_9/DQA_9
DQA0_10/DQA_10
DQA0_11/DQA_11
DQA0_12/DQA_12
DQA0_13/DQA_13
DQA0_14/DQA_14
DQA0_15/DQA_15
DQA0_16/DQA_16
DQA0_17/DQA_17
DQA0_18/DQA_18
DQA0_19/DQA_19
DQA0_20/DQA_20
DQA0_21/DQA_21
DQA0_22/DQA_22
DQA0_23/DQA_23
DQA0_24/DQA_24
DQA0_25/DQA_25
DQA0_26/DQA_26
DQA0_27/DQA_27
DQA0_28/DQA_28
DQA0_29/DQA_29
DQA0_30/DQA_30
DQA0_31/DQA_31
DQA1_0/DQA_32
DQA1_1/DQA_33
DQA1_2/DQA_34
DQA1_3/DQA_35
DQA1_4/DQA_36
DQA1_5/DQA_37
DQA1_6/DQA_38
DQA1_7/DQA_39
DQA1_8/DQA_40
DQA1_9/DQA_41
DQA1_10/DQA_42
DQA1_11/DQA_43
DQA1_12/DQA_44
DQA1_13/DQA_45
DQA1_14/DQA_46
DQA1_15/DQA_47
DQA1_16/DQA_48
DQA1_17/DQA_49
DQA1_18/DQA_50
DQA1_19/DQA_51
DQA1_20/DQA_52
DQA1_21/DQA_53
DQA1_22/DQA_54
DQA1_23/DQA_55
DQA1_24/DQA_56
DQA1_25/DQA_57
DQA1_26/DQA_58
DQA1_27/DQA_59
DQA1_28/DQA_60
DQA1_29/DQA_61
DQA1_30/DQA_62
DQA1_31/DQA_63

MEMORY INTERFACE A

C37
C35
A35
E34
G32
D33
F32
E32
D31
F30
C30
A30
F28
C28
A28
E28
D27
F26
C26
A26
F24
C24
A24
E24
C22
A22
F22
D21
A20
F20
D19
E18
C18
A18
F18
D17
A16
F16
D15
E14
F14
D13
F12
A12
D11
F10
A10
C10
G13
H13
J13
H11
G10
G8
K9
K10
G9
A8
C8
E8
A6
C6
E6
A5

DDR2
GDDR5/GDDR3
DDR3

U6D
DDR2
GDDR3/GDDR5
DDR3

G24
J23
H24
J24
H26
J26
H21
G21
H19
H20
L13
G16
J16
H16
J17
H17

MDB0
MDB1
MDB2
MDB3
MDB4
MDB5
MDB6
MDB7
MDB8
MDB9
MDB10
MDB11
MDB12
MDB13
MDB14
MDB15
MDB16
MDB17
MDB18
MDB19
MDB20
MDB21
MDB22
MDB23
MDB24
MDB25
MDB26
MDB27
MDB28
MDB29
MDB30
MDB31
MDB32
MDB33
MDB34
MDB35
MDB36
MDB37
MDB38
MDB39
MDB40
MDB41
MDB42
MDB43
MDB44
MDB45
MDB46
MDB47
MDB48
MDB49
MDB50
MDB51
MDB52
MDB53
MDB54
MDB55
MDB56
MDB57
MDB58
MDB59
MDB60
MDB61
MDB62
MDB63

+1.8VGS
R293
R294
R295
R296
R297
R298

A32
C32
D23
E22
C14
A14
E10
D9
C34
D29
D25
E20
E16
E12
J10
D7

1
1
1
1
1
1

X76@
X76@
X76@
X76@
X76@
X76@

Vendor

2
2
2
2
2
2

10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%

64MX16 (512MB)

128M16 (1GB)

J21
G19

128M16 (1GB)
H27
G27

VRAM_ID1
VRAM_ID2

VRAM_ID0

<16>

VRAM_ID1

<16>

VRAM_ID2

<16>

VRAM_ID0 VRAM_ID1 VRAM_ID2

K4W1G1646G-BC11

64MX16 (512MB)

A34
E30
E26
C20
C16
C12
J11
F8

VRAM_ID0

Samsung 1Gb
PN:SA00004GS40
H5TQ1G63DFR-11C
Hynix 1Gb
PN:SA000041S30
K4W2G1646C-HC11
Samsung 256MB
PN:SA000047Q10
H5TQ2G63BFR-11C/H5TQ2G63DFR-11C
Hynix 256MB
PN:SA00003YO10/
SA00003YO70

R293
1

R296
0

R294
0

R295
1

R293
1

R296
0

R294
0

R295
1

R298
0

R298
0

R297
1

R297
1

J14
H14
K23
K19
K20
K17
K24
K27
M13
K16
K21
J20

C5
C3
E3
E1
F1
F3
F5
G4
H5
H6
J4
K6
K5
L4
M6
M1
M3
M5
N4
P6
P5
R4
T6
T1
U4
V6
V1
V3
Y6
Y1
Y3
Y5
AA4
AB6
AB1
AB3
AD6
AD1
AD3
AD5
AF1
AF3
AF6
AG4
AH5
AH6
AJ4
AK3
AF8
AF9
AG8
AG7
AK9
AL7
AM8
AM7
AK1
AL4
AM6
AM1
AN4
AP3
AP1
AP5

+VDD_MEM15_REFDB Y12
+VDD_MEM15_REFSB AA12

K26
L15

DQB0_0/DQB_0
DQB0_1/DQB_1
DQB0_2/DQB_2
DQB0_3/DQB_3
DQB0_4/DQB_4
DQB0_5/DQB_5
DQB0_6/DQB_6
DQB0_7/DQB_7
DQB0_8/DQB_8
DQB0_9/DQB_9
DQB0_10/DQB_10
DQB0_11/DQB_11
DQB0_12/DQB_12
DQB0_13/DQB_13
DQB0_14/DQB_14
DQB0_15/DQB_15
DQB0_16/DQB_16
DQB0_17/DQB_17
DQB0_18/DQB_18
DQB0_19/DQB_19
DQB0_20/DQB_20
DQB0_21/DQB_21
DQB0_22/DQB_22
DQB0_23/DQB_23
DQB0_24/DQB_24
DQB0_25/DQB_25
DQB0_26/DQB_26
DQB0_27/DQB_27
DQB0_28/DQB_28
DQB0_29/DQB_29
DQB0_30/DQB_30
DQB0_31/DQB_31
DQB1_0/DQB_32
DQB1_1/DQB_33
DQB1_2/DQB_34
DQB1_3/DQB_35
DQB1_4/DQB_36
DQB1_5/DQB_37
DQB1_6/DQB_38
DQB1_7/DQB_39
DQB1_8/DQB_40
DQB1_9/DQB_41
DQB1_10/DQB_42
DQB1_11/DQB_43
DQB1_12/DQB_44
DQB1_13/DQB_45
DQB1_14/DQB_46
DQB1_15/DQB_47
DQB1_16/DQB_48
DQB1_17/DQB_49
DQB1_18/DQB_50
DQB1_19/DQB_51
DQB1_20/DQB_52
DQB1_21/DQB_53
DQB1_22/DQB_54
DQB1_23/DQB_55
DQB1_24/DQB_56
DQB1_25/DQB_57
DQB1_26/DQB_58
DQB1_27/DQB_59
DQB1_28/DQB_60
DQB1_29/DQB_61
DQB1_30/DQB_62
DQB1_31/DQB_63

MAB[12..0]

MAB0_0/MAB_0
MAB0_1/MAB_1
MAB0_2/MAB_2
MAB0_3/MAB_3
MAB0_4/MAB_4
MAB0_5/MAB_5
MAB0_6/MAB_6
MAB0_7/MAB_7
MAB1_0/MAB_8
MAB1_1/MAB_9
MAB1_2/MAB_10
MAB1_3/MAB_11
MAB1_4/MAB_12
MAB1_5/BA2
MAB1_6/BA0
MAB1_7/BA1

WCKB0_0/DQMB_0
WCKB0B_0/DQMB_1
WCKB0_1/DQMB_2
WCKB0B_1/DQMB_3
WCKB1_0/DQMB_4
WCKB1B_0/DQMB_5
WCKB1_1/DQMB_6
WCKB1B_1/DQMB_7
GDDR5/DDR2/GDDR3
EDCB0_0/QSB_0/RDQSB_0
EDCB0_1/QSB_1/RDQSB_1
EDCB0_2/QSB_2/RDQSB_2
EDCB0_3/QSB_3/RDQSB_3
EDCB1_0/QSB_4/RDQSB_4
EDCB1_1/QSB_5/RDQSB_5
EDCB1_2/QSB_6/RDQSB_6
EDCB1_3/QSB_7/RDQSB_7

DDBIB0_0/QSB_0B/WDQSB_0
DDBIB0_1/QSB_1B/WDQSB_1
DDBIB0_2/QSB_2B/WDQSB_2
DDBIB0_3/QSB_3B/WDQSB_3
DDBIB1_0/QSB_4B/WDQSB_4
DDBIB1_1/QSB_5B/WDQSB_5
DDBIB1_2/QSB_6B/WDQSB_6
DDBIB1_3/QSB_7B/WDQSB_7
ADBIB0/ODTB0
ADBIB1/ODTB1
CLKB0
CLKB0B
CLKB1
CLKB1B
RASB0B
RASB1B
CASB0B
CASB1B
CSB0B_0
CSB0B_1
CSB1B_0
CSB1B_1
CKEB0
CKEB1

MVREFDB
MVREFSB

MDB[0..63]

<21> MDB[0..63]

DDR2
GDDR5/GDDR3
DDR3

WEB0B
WEB1B

P8
T9
P9
N7
N8
N9
U9
U8
Y9
W9
AC8
AC9
AA7
AA8
Y8
AA9

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
B_BA2
B_BA0
B_BA1

H3
H1
T3
T5
AE4
AF5
AK6
AK5

DQMB#0
DQMB#1
DQMB#2
DQMB#3
DQMB#4
DQMB#5
DQMB#6
DQMB#7

F6
K3
P3
V5
AB5
AH1
AJ9
AM5

QSB0
QSB1
QSB2
QSB3
QSB4
QSB5
QSB6
QSB7

G7
K1
P1
W4
AC4
AH3
AJ8
AM3

QSB#0
QSB#1
QSB#2
QSB#3
QSB#4
QSB#5
QSB#6
QSB#7

T7
W7

ODTB0
ODTB1

L9
L8

CLKB0
CLKB0#

AD8
AD7

CLKB1
CLKB1#

T10
Y10

RASB0#
RASB1#

W10
AA10

CASB0#
CASB1#

P10
L10

CSB0#_0

AD10
AC10

CSB1#_0

U10
AA11

CKEB0
CKEB1

N10
AB11

WEB0#
WEB1#

T8
W8

MAB13
MAB14

MAB[12..0] <21>

B_BA[2..0]

B_BA[2..0] <21>

DQMB#[7..0] <21>

QSB[7..0] <21>

QSB#[7..0] <21>

ODTB0 <21>
ODTB1 <21>
CLKB0 <21>
CLKB0# <21>
C

CLKB1 <21>
CLKB1# <21>
RASB0# <21>
RASB1# <21>
CASB0# <21>
CASB1# <21>
CSB0#_0 <21>
CSB1#_0 <21>
CKEB0 <21>
CKEB1 <21>
WEB0# <21>
WEB1# <21>

PX@

H23
J19

R303 1

TESTEN

2
5.11K_0402_1%

AD28
AK10
AL10

TESTEN

GDDR5

U6C
DDR2
GDDR3/GDDR5
DDR3

MEMORY INTERFACE B

CLKTESTA
CLKTESTB

MAB0_8
MAB1_8

DRAM_RST

AH11

MAB13 <21>
MAB14 <21>

DRAM_RST#_R

ROBSON XT M2
ROBSON XT M2
PX@

R304

POP

R305

R302

R301

This basic topology should be used for DRAM_RST for DDR3/GDDR5.These


Capacitors and Resistor values are an example only. The Series R and
|| Cap values will depend on the DRAM load and will have to be
calculated for different Memory ,DRAM Load and board to pass Reset
Signal Spec.
Place all these components very close to GPU (Within
25mm) and keep all component close to each Other (within
5mm) except Rser2

POP

R300

R299

@
R306
51.1_0402_1%

@
C428
0.1U_0402_16V7K

@
R307
51.1_0402_1%
2

@
C427
0.1U_0402_16V7K

route 50ohms single-ended/100ohms diff


and keep short
Debug only, for clock observation, if not needed, DNI
5mil 5mil

Rosbon M2

PX@

+1.5VGS

R308
4.7K_0402_5%
@

R311
40.2_0402_1%
PX@

DRAM_RST#_R

R312
40.2_0402_1%
PX@
2
R319
100_0402_1%
PX@

C433
0.1U_0402_16V7K
PX@

+VDD_MEM15_REFSB

R318
100_0402_1%
PX@

C432
0.1U_0402_16V7K
PX@

+VDD_MEM15_REFDB
PX@
R317
4.99K_0402_1%

PX@
C431
120P_0402_50V9

1 R314
2
10_0402_5%
PX@

1 R313
2
51.1_0402_1%
PX@

<21> DRAM_RST#

+1.5VGS

+1.5VGS

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ATI_RobsonXT_M2_MEM IF
Size
C
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

20

of

48

DQMB#[7..0]

<20> DQMB#[7..0]

<20> QSB[7..0]

<20> QSB#[7..0]

QSB[7..0]

<20> CLKB0
<20> CLKB0#
<20> CKEB0

J7
K7
K9

QSB#[7..0]

<20>
<20>
<20>
<20>
<20>

K1
L2
J3
K3
L3

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

PX@
CLKB0 1
R344

QSB2
QSB0

F3
C7

DQMB#2
DQMB#0

E7
D3

QSB#2
QSB#0

G3
B7

2
56_0402_1%
PX@

T2

<20> DRAM_RST#

2
56_0402_1%

L8

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

J1
L1
J9
L9

R346
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

2
56_0402_1%

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB0
CSB0#_0
RASB0#
CASB0#
WEB0#

K1
L2
J3
K3
L3

QSB3
QSB1

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#3
DQMB#1

E7
D3

QSB#3
QSB#1

G3
B7

U19

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

DRAM_RST# T2

RESET

L8

E3
F7
F2
F8
H3
H8
G2
H7

MDB26
MDB30
MDB24
MDB29
MDB27
MDB28
MDB25
MDB31

D7
C3
C8
C2
A7
A2
B8
A3

MDB15
MDB10
MDB14
MDB11
MDB12
MDB9
MDB13
MDB8

VREFC_A3_B
VREFD_Q3_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VGS

BA0
BA1
BA2

ZQ/ZQ0

J1
L1
J9
L9

R347
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

M2
N8
M3

<20> CLKB1
<20> CLKB1#
<20> CKEB1

J7
K7
K9

<20>
<20>
<20>
<20>
<20>

K1
L2
J3
K3
L3

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

QSB4
QSB5

F3
C7

DQMB#4
DQMB#5

E7
D3

QSB#4
QSB#5

G3
B7

DRAM_RST# T2
L8

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R348
240_0402_1%
PX@

96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C
X76@

2
56_0402_1%

CLKB0
CLKB0#
CKEB0

+1.5VGS

96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C

PX@
CLKB1# 1
R351

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

PX@
CLKB1 1
R350

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

B_BA0
B_BA1
B_BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

C481
0.01U_0402_16V7K
PX@

MDB0
MDB4
MDB1
MDB6
MDB3
MDB7
MDB2
MDB5

M8
H1

+1.5VGS

BA0
BA1
BA2

CLKB0# 1
R345

D7
C3
C8
C2
A7
A2
B8
A3

VREFC_A2_B
VREFD_Q2_B

M2
N8
M3

<20> B_BA0
<20> B_BA1
<20> B_BA2

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

MDB19
MDB20
MDB22
MDB16
MDB23
MDB17
MDB21
MDB18

U20

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB33
MDB37
MDB35
MDB39
MDB32
MDB36
MDB34
MDB38

D7
C3
C8
C2
A7
A2
B8
A3

MDB44
MDB41
MDB47
MDB43
MDB45
MDB40
MDB46
MDB42

VREFC_A4_B
VREFD_Q4_B

M8
H1

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

+1.5VGS

BA0
BA1
BA2

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

DQSL
DQSU
DML
DMU

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

B_BA0
B_BA1
B_BA2

M2
N8
M3

CLKB1
CLKB1#
CKEB1

J7
K7
K9

A1
A8
C1
C9
D2
E9
F1
H2
H9

ODTB1
CSB1#_0
RASB1#
CASB1#
WEB1#

K1
L2
J3
K3
L3

QSB6
QSB7

F3
C7

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

DQMB#6
DQMB#7

E7
D3

QSB#6
QSB#7

G3
B7

B2
D9
G7
K2
K8
N1
N9
R1
R9

+1.5VGS

DRAM_RST# T2
L8

MAB[14..0]

<20> MAB[14..0]

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

E3
F7
F2
F8
H3
H8
G2
H7

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

MDB[0..63]

<20> MDB[0..63]

N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
MAB13
MAB14

U18

VREFCA
VREFDQ

VREFCA
VREFDQ

DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13
A14
A15/BA3

DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7

E3
F7
F2
F8
H3
H8
G2
H7

MDB55
MDB50
MDB54
MDB51
MDB53
MDB49
MDB52
MDB48

D7
C3
C8
C2
A7
A2
B8
A3

MDB56
MDB59
MDB63
MDB62
MDB57
MDB61
MDB58
MDB60

+1.5VGS

BA0
BA1
BA2

B2
D9
G7
K2
K8
N1
N9
R1
R9

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

CK
CK
CKE/CKE0
ODT/ODT0
CS/CS0
RAS
CAS
WE
DQSL
DQSU
DML
DMU

A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

DQSL
DQSU

RESET
ZQ/ZQ0

+1.5VGS

A1
A8
C1
C9
D2
E9
F1
H2
H9

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

U17
VREFC_A1_B M8
VREFD_Q1_B H1

B1
B9
D1
D8
E2
E8
F9
G1
G9

J1
L1
J9
L9

R349
240_0402_1%
PX@

NC/ODT1
NC/CS1
NC/CE1
NCZQ1

96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C

B1
B9
D1
D8
E2
E8
F9
G1
G9

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

96-BALL
SDRAM DDR3
H5TQ1G63DFR-11C

X76@

X76@

X76@

C482
0.01U_0402_16V7K
PX@

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

+1.5VGS

VREFD_Q4_B
1

R363
4.99K_0402_1%
PX@

1
R367
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C490

VREFC_A4_B
0.1U_0402_16V7K
PX@
C489

0.1U_0402_16V7K
PX@
C488

0.1U_0402_16V7K
PX@
C487

R359
4.99K_0402_1%
PX@

VREFD_Q3_B

R366
4.99K_0402_1%
PX@

1
2

R365
4.99K_0402_1%
PX@

R358
4.99K_0402_1%
PX@

VREFC_A3_B
1

R357
4.99K_0402_1%
PX@

VREFD_Q2_B

R364
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C486

R356
4.99K_0402_1%
PX@

VREFC_A2_B
1

R362
4.99K_0402_1%
PX@
2

R361
4.99K_0402_1%
PX@

0.1U_0402_16V7K
PX@
C485

VREFC_A1_B
0.1U_0402_16V7K
PX@
C484

0.1U_0402_16V7K
PX@
C483

VREFD_Q1_B

R360
4.99K_0402_1%
PX@

R355
4.99K_0402_1%
PX@
2

R354
4.99K_0402_1%
PX@
2

R353
4.99K_0402_1%
PX@
2

R352
4.99K_0402_1%
PX@

+1.5VGS
+1.5VGS

Compal Secret Data

Security Classification
Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


ATI_RobsonXT_M2_VRAM_B

Size
C
Date:

1U_0402_6.3V6K
PX@
C1067

1U_0402_6.3V6K
PX@
C1066

1U_0402_6.3V6K
PX@
C1065

1U_0402_6.3V6K
PX@
C1064

1U_0402_6.3V6K
PX@
C1061

1U_0402_6.3V6K
PX@
C1060

1U_0402_6.3V6K
PX@
C1063

1U_0402_6.3V6K
PX@
C1062

1U_0402_6.3V6K
PX@
C1059

1U_0402_6.3V6K
PX@
C1058

1U_0402_6.3V6K
PX@
C1057

1U_0402_6.3V6K
PX@
C1056

1U_0402_6.3V6K
PX@
C1055

1U_0402_6.3V6K
PX@
C1054

1U_0402_6.3V6K
PX@
C1053

1U_0402_6.3V6K
PX@
C1052

1U_0402_6.3V6K
PX@
C1051

1U_0402_6.3V6K
PX@
C1050

+1.5VGS

1U_0402_6.3V6K
PX@
C1049

1U_0402_6.3V6K
PX@
C1048

10U_0603_6.3V6M
PX@
C507

10U_0603_6.3V6M
PX@
C506

10U_0603_6.3V6M
PX@
C505

10U_0603_6.3V6M
PX@
C504

0.1U_0402_16V7K
PX@
C503

0.1U_0402_16V7K
PX@
C502

0.1U_0402_16V7K
PX@
C501

0.1U_0402_16V7K
PX@
C500

0.1U_0402_16V7K
PX@
C499

0.1U_0402_16V7K
PX@
C498

0.1U_0402_16V7K
PX@
C497

0.1U_0402_16V7K
PX@
C496

0.1U_0402_16V7K
PX@
C495

0.1U_0402_16V7K
PX@
C494

0.1U_0402_16V7K
PX@
C493

0.1U_0402_16V7K
PX@
C492

0.1U_0402_16V7K
PX@
C491

+1.5VGS

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011
1

Sheet

21

of

48

LCD POWER CIRCUIT

+LCDVDD

+5VALW

R381
150_0603_1%

R382
100K_0402_5%

W=60mils

2
G

R383

1 2

D
Q35
2N7002K_SOT23-3

OUT

IN

GND

2 0_0402_5%

R389 1

220K_0402_5%

<5> APU_ENVDD

C1068
4.7U_0603_6.3V6K

+3VS

C1069

Q36
AP2301GN-HF_SOT23-3

W=60mils

0.1U_0402_16V4Z
+LCDVDD

+LCDVDD_CONN

L74
1

Q37
DTC124EKAT146_SC59-3

FBMA-L11-201209-221LMA30T_0805
C1070
4.7U_0603_6.3V6K

R390
@
100K_0402_5%

<30> EC_INVT_PWM

R697 1

2 0_0402_5%

<5> APU_BLPWM

R392 1

2 0_0402_5%

C1071
0.1U_0402_16V4Z

INVTPWM
2

+LEDVDD

B+

R395
100K_0402_5%
1

1 R822
2
0_0805_5%

@
C543
680P_0402_50V7K

C542
4.7U_0805_25V6-K

JLVDS1

+3VS
@ R982
R698 1

<30> BKOFF#

2 0_0402_5%

R1007 1

1
R984

2 10K_0402_5%

2
0_0402_5%

1
2
10K_0402_5%

DISPOFF#
INVTPWM
<5> LVDS_ACLK
<5> LVDS_ACLK#

DISPOFF#

RB751V_SOD323
D4 @

<5> LVDS_A2
<5> LVDS_A2#
<5> LVDS_A1
<5> LVDS_A1#
<5> LVDS_A0
<5> LVDS_A0#
<5> EDID_DATA
<5> EDID_CLK

R983 1

<5> APU_ENBKL

2 0_0402_5%

ENBKL <30>

+3VS

R396
2

@
C544
680P_0402_50V7K

1
100K_0402_5%

+LCDVDD_CONN

(60 MIL)

+3VS
2

+3VS_CMOS
<12> USB20_P3
<12> USB20_N3

USB20_P3
USB20_N3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

31
32
33
34

G1
G2
G3
G4

ACES_88341-3001
ME@

CMOS Camera
Q39
AP2301GN-HF_SOT23-3
3

+3VS

+CMOS_PW

C1091
2

1
A

R986
0_0603_5%
CMOS@

C1090
0.1U_0402_16V4Z
CMOS@

+3VS_CMOS

0.1U_0402_16V4Z
CMOS@

R987
10K_0402_5%
CMOS@

10U_0603_6.3V6M
C1092
CMOS@

Compal Secret Data

Security Classification

CMOS@

<30> CMOS_ON#

2011/10/12

Issued Date

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


LVDS/CAMERA

Size
B
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet
1

22

of

48

EMI request
@L75
@
L75
<5> HDMI_CLKP

R988 HDMI@ 1

<5> HDMI_CLKN

R989 HDMI@ 1

0_0402_5%

HDMI_CLK+_CONN

HDMI_CLKP

0_0402_5%

HDMI_CLK-_CONN

HDMI_CLKN

1
4

1
4

2
3

HDMI_CLK+_CONN

C1025

2 10P_0402_50V8J

HDMI_CLK-_CONN

C1026

2 10P_0402_50V8J
D

WCM-2012-900T_4P
@L33
@
L33
R412 HDMI@ 1

<5> HDMI_TX0P

R991 HDMI@ 1

<5> HDMI_TX0N

0_0402_5%

HDMI_TX0+_CONN

HDMI_TX0P

0_0402_5%

HDMI_TX0-_CONN

HDMI_TX0N

1
4

1
4

2
3

HDMI_TX0+_CONN

C1027

2 10P_0402_50V8J

HDMI_TX0-_CONN

C1028

2 10P_0402_50V8J

HDMI_TX1+_CONN

C1029

2 10P_0402_50V8J

HDMI_TX1-_CONN

C1030

2 10P_0402_50V8J

HDMI_TX2+_CONN

C1031

2 10P_0402_50V8J

HDMI_TX2-_CONN

C1032

2 10P_0402_50V8J

WCM-2012-900T_4P
@L34
@
L34
<5> HDMI_TX1P

R414 HDMI@ 1

0_0402_5%

HDMI_TX1+_CONN

HDMI_TX1P

<5> HDMI_TX1N

R993 HDMI@ 1

0_0402_5%

HDMI_TX1-_CONN

HDMI_TX1N

WCM-2012-900T_4P
@L35
@
L35
<5> HDMI_TX2P

R994 HDMI@ 1

0_0402_5%

HDMI_TX2+_CONN

HDMI_TX2P

<5> HDMI_TX2N

R995 HDMI@ 1

0_0402_5%

HDMI_TX2-_CONN

HDMI_TX2N

WCM-2012-900T_4P

HDMI_TX2+_CONN

HDMI@
2 R262
1 499_0402_1%

HDMI_TX2-_CONN

HDMI@
2 R264
1 499_0402_1%

HDMI@
F1
1.1A_6V_SMD1812P110TF

HDMI@
R430
2K_0402_5%

Q42
2N7002K_SOT23-3
HDMI@

+5VS

+5VS_HDMI

HDMI@
R431
2K_0402_5%

C1093
0.1U_0402_16V4Z
HDMI@

JHDMI1
HDMI_HPD

<5> HDMI_CLK

R451 HDMI@
0_0402_5%
2
1

HDMICLK_R

<5> HDMI_DATA

R452 HDMI@
0_0402_5%
2
1

HDMIDAT_R

<5> HDMI_DET

R450 HDMI@
0_0402_5%
2
1

HDMI_HPD

HDMIDAT_R
HDMICLK_R
HDMI_CLK-_CONN
HDMI_CLK+_CONN
HDMI_TX0-_CONN
HDMI_TX0+_CONN
HDMI_TX1-_CONN

NEAR CONNECTOR

RB491D_SC59-3
HDMI@
D7

2
G
@
R970
100K_0402_5%

+5VS_HDMI_F

@
D8
BAT54S-7-F_SOT23-3

ESD

+5VS
B

HDMI_HPD

HDMI@
2 R260
1 499_0402_1%

HDMI_TX1-_CONN

0_0805_5%
D5 @
PJDLC05_SOT23-3

HDMI@
2 R258
1 499_0402_1%

@R429
@
R429

ESD

HDMI_TX1+_CONN

+5VS

HDMI_TX0-_CONN

HDMI@
2 R255
1 499_0402_1%

HDMICLK_R

HDMI_TX0+_CONN

HDMI@
2 R253
1 499_0402_1%

HDMI@
2 R252
1 499_0402_1%
3

HDMI_CLK-_CONN

HDMIDAT_R

HDMI@
2 R418
1 499_0402_1%

HDMI_CLK+_CONN

HDMI_TX1+_CONN
HDMI_TX2-_CONN

HDMI@
R974
100K_0402_5%
2

HDMI_TX2+_CONN

19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+

20
21
22
23

SUYIN_100042GR019M23DZL
ME@

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

HDMI Connector
Size Document Number
Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet
1

23

of

48

<5> DAC_GRN

FCM1608CF-121T03 0603
1
2
L36
FCM1608CF-121T03 0603
1
2
L37
FCM1608CF-121T03 0603
1
2
L38
1
1

DAC_RED
DAC_GRN
DAC_BLU

<5> DAC_BLU

<5> DAC_RED

1
R977
150_0402_1%

R976
150_0402_1%

R975
150_0402_1%

1
C1094

C1103

C1104
10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

RED

GREEN
D2107
BLUE

C1105

1
C1106

BLUE

I/O4

I/O2

VDD

GND

I/O3

I/O1

GREEN

+5VS
C1107
10P_0402_50V8J

10P_0402_50V8J 10P_0402_50V8J

RED

AZC099-04S.R7G_SOT23-6
D2108
CRT_DDC_DATA_R
+CRT_VCC

I/O2

VDD

GND

I/O3

I/O1

1K_0402_5%
CRT_DDC_CLK_R

2
OE#

JVGA_HS

+5VS

R978

I/O4

1
C1108
0.1U_0402_16V4Z

A
G

<5> CRT_HSYNC

JVGA_VS
2

AZC099-04S.R7G_SOT23-6

CRT_HSYNC_1

+CRT_VCC

JVGA_HS

1
2
L39
FCM1608CF-121T03 0603

U23
SN74AHCT1G125DCKR_SC70-5

R979

@
C1120
10P_0402_50V8J

A
3

<5> CRT_VSYNC

OE#

C1109
0.1U_0402_16V4Z

1K_0402_5%

CRT_VSYNC_1

JVGA_VS

1
2
L40
FCM1608CF-121T03 0603

U24
SN74AHCT1G125DCKR_SC70-5

@
C1110
10P_0402_50V8J

+CRT_VCC

+5VS
D14

2
3

F2

2
1

RB491D_SC59-3
+CRT_VCC

1.1A_6V_SMD1812P110TF

C568
0.1U_0402_16V4Z

R981
4.7K_0402_5%
JCRT1

R980
4.7K_0402_5%

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

RED
R104 1

<5> CRT_DDC_DATA

2 0_0402_5%

CRT_DDC_DATA_R

CRT_DDC_DATA_R
GREEN
JVGA_HS
BLUE
JVGA_VS

R109 1

<5> CRT_DDC_CLK

2 0_0402_5%

CRT_DDC_CLK_R
CRT_DDC_CLK_R
@
C1112
100P_0402_50V8J

@
C1121
68P_0402_50V8K

Compal Secret Data

Security Classification
2011/10/12

Issued Date

Deciphered Date

2013/10/12

16
17

CONTE_80431-5K1-152
ME@

100P_0402_50V8J

Compal Electronics, Inc.


CRT Connector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

C1122

G
G

Size
Document Number
Custom
Date:

Rev
0.1

LA8681P

W ednesday, November 30, 2011

Sheet
E

24

of

48

Layout Notice : Place as close


chip as possible.
+3V_LAN

+3VALW

J3

JUMP_43X79

8105@

L76

AO3413_SOT23
D

C1125
4.7U_0603_6.3V6K

X5R

R145
C738
0.1U_0402_16V4Z

<30> LAN_PWR_ON#

@ Q150

1
2
10K_0402_5%

U41

HSIP
HSIN

16

CLKREQB

<10,30> PLT_RST#

25

PERSTB

<10> CLK_PCIE_LAN
<10> CLK_PCIE_LAN#

19
20

REFCLK_P
REFCLK_N

Pin 16 and Pin 28 are OD pins

1 R1370
1 R1369
@

<30> LAN_WAKE#
<12,29> FCH_PCIE_WAKE#

+3V_LAN

+3V_LAN

LAN_XTALI

43

CKXTAL1

LAN_XTALO

44

CKXTAL2

PCIE_WAKE#_R

2 0_0402_5%
2 0_0402_5%

ISOLATEB 26

GIGA@ 2 R569
GIGA@ 1 R577

1 10K_0402_5%
2 1K_0402_5%

ENSWREG
R570
10K_0402_5%
@

28

1
2
R575 2.49K_0402_1%
LAN_CLKREQ#

30
32

R571 2
R573 2

MDIP0
MDIN0
MDIP1
MDIN1
NC/MDIP2
NC/MDIN2
NC/MDIP3
NC/MDIN3

1
2
4
5
7
8
10
11

DVDD10
DVDD10
DVDD10

13
29
41

+LAN_VDD10

DVDD33
DVDD33

27
39

+3V_LAN

AVDD33
AVDD33
AVDD33
AVDD33

12
42
47
48

+3V_LAN

EVDD10

21

+LAN_EVDD10

AVDD10
AVDD10
AVDD10
AVDD10

3
6
9
45

+LAN_VDD10

REGOUT

36

+LAN_VDD10

1 10K_0402_5%
1 10K_0402_5%

MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-

MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-

<26>
<26>
<26>
<26>
<26>
<26>
<26>
<26>

Close to Pin 12,27,39,42,47,48

1
L48
C732
1U_0402_6.3V4Z

C695
0.1U_0402_16V4Z

+3V_LAN

Close to Pin 21

1
0.1U_0402_16V4Z

1
0.1U_0402_16V4Z
0.1U_0402_16V4Z

1
+3V_LAN

LANW AKEB

GIGA@ 0.1U_0402_16V4Z

+LAN_VDDREG

1
GIGA@ 0.1U_0402_16V4Z

ISOLATEB

14
15
38

NC/SMBCLK
NC/SMBDATA
GPO/SMBALERT

33

ENSW REG

34
35

VDDREG
VDDREG

46

RSET

24
49

GND
PGND

2
0_0603_5%

1
L77

C1131
4.7U_0603_6.3V6K

X5R

GIGA@ 0.1U_0402_16V4Z

2
C745
2
C1128
2
C742
2
C1129
2
C731
2
C1130

C1132
0.1U_0402_16V4Z

Close to Pin 3,6,9,13,29,41,45


+LAN_VDD10
+3VS

+3V_LAN

1
0.1U_0402_16V4Z

+LAN_REGOUT

1
0.1U_0402_16V4Z

R576
1K_0402_1%

RTL8111F-CGT_QFN48_6x6
GIGA@

Rising time (10%~90%)1mS <Rising time <100mS

+LAN_EVDD10

2
0_0603_5%

+LAN_VDDREG

EECS
EEDI

Layout Notice : Place as close


chip as possible.

11/08 Increase for LAN S5 power saving

LAN_LINK# <26>
LAN_ACTIVITY# <26>

R572
0_0402_5%

1
0.1U_0402_16V4Z

1
2

LAN_LINK#
LAN_ACTIVITY#

<12> LAN_CLKREQ#

31
37
40

17
18

LED3/EEDO
LED1/EESK
LED0

HSON

C1021
0.1U_0402_16V7K
@

HSOP

23

22

PCIE_PRX_C_DTX_N0

PCIE_PRX_C_DTX_P0

2 0.1U_0402_16V7K

2 0.1U_0402_16V7K

C1127 1

C1126 1

<10> PCIE_FRX_DTX_N0

<10> PCIE_FRX_DTX_P0

<10> PCIE_FTX_C_DRX_P0
<10> PCIE_FTX_C_DRX_N0

Layout Note: L39 must be


within 200mil to Pin36,
C700,C738 must be within
200mil to LL1
+LAN_REGOUT: Width
=60mil

RTL8105E-VL-CGT

+LAN_REGOUT
1
2
2.2UH +-5% NLC252018T-2R2J-N

U44

+LAN_VDD10

ISOLATEB

GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

GIGA@

0.1U_0402_16V4Z

ENSWREG

SA00004Y700

1
R574
0_0402_5%
@

R578
15K_0402_5%

2
C737
2
C1133
2
C694
2
C743
2
C741
2
C739
2
C740

LAN_XTALI
LAN_XTALO

NC

OSC

NC

OSC

C1135

1 25MHZ_20PF_FSX3M-25.M20FDO 1
C1134

27P_0402_50V8J

R02

H: Enable internal Regular


L: Disable

27P_0402_50V8J

Y6

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/15

2012/07/11

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LAN-RTL8111F/8105E
Size Document Number
Custom
Date:

Rev
0.1

LA-7984P

Wednesday, November 30, 2011

Sheet
1

25

of

48

MDI3MDI3+
T2

6
7
8
9
10
6
7
8
9
10

MDI3+
MDI3-

<25> MDI3+
<25> MDI3-

11

GND
MDI2+
MDI2-

<25> MDI2+
<25> MDI2-

TD+
TDCT
NC
NC
CT
RD+
RD-

TX+
TXCT
NC
NC
CT
RX+
RX-

16
15
14
13
12
11
10
9

MDO3+
MDO3MCT3

1
2
R1374 75_0603_5%

GIGA@
1
2
R1375 75_0603_5%

MCT2
MDO2+
MDO2-

GIGA@

5
4
3
2
1

5
4
3
2
1

RCLAMP3304N.TCT_SLP2626P10-10
D69 @

1
2
3
4
5
6
7
8

BOTHHAND_NS0013LF
GIGA@
MDI2R02

MDI2+
T1

Place Close to T2

MDI0+
MDI0-

<25> MDI0+
<25> MDI0-

MDI1MDI1+

6
7
8
9
10

MDI1+
MDI1-

<25> MDI1+
<25> MDI1-

C1136
0.01U_0402_16V7K

TD+
TDCT
NC
NC
CT
RD+
RD-

TX+
TXCT
NC
NC
CT
RX+
RX-

16
15
14
13
12
11
10
9

MDO0+
MDO0MCT0

1 R1376 2
75_0603_5%

MCT1

1 R1377 2
75_0603_5%

MDO1+
MDO1-

6
7
8
9
10

BOTHHAND_NS0013LF

GND
RCLAMP3304N.TCT_SLP2626P10-10
D68 @

5
4
3
2
1

5
4
3
2
1

11

1
2
3
4
5
6
7
8

C973
1000P_1206_2KV7K

Reserve gas tube for EMI go rural solution


MDI0-

Place Close to T1,T2

MDI0+

LAN_ACTIVITY# R1448

PR2+

MDO2+

PR3+

MDO2-

PR3-

MDO1-

PR2-

MDO3+

PR4+

G2

14

MDO3-

PR4-

G1

13

1 510_0402_5%

11
12

+3V_LAN
@
C1138
470P_0402_50V7K

Yellow LED-

MCT0

MDO1+

DL4

PR1-

@
1

MCT1

MDO0-

LSE-200NX3216TRLF_1206-2

<25> LAN_ACTIVITY#

PR1+

LSE-200NX3216TRLF_1206-2

Overclocking mode stick

DL3

MCT2

MDO0+

MCT3

Green LED+

LSE-200NX3216TRLF_1206-2

C1137 @
470P_0402_50V7K

Green LED-

9
10

DL2

+3V_LAN

1 510_0402_5%

R1449

DL1

LAN_LINK#

<25> LAN_LINK#

LSE-200NX3216TRLF_1206-2

JRJ1

Place Close to T1

Yellow LED+
SANTA_130452-D ME@

Reserve for EMI go rural solution

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/06/15

Deciphered Date

2012/07/11

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

LAN_Transformer
Size
B
Date:

Document Number

Rev
0.1

LA-7984P
Wednesday, November 30, 2011

Sheet
1

26

of

48

+3VS

CX20671
High Definition Audio Codec SoC
With Integrated Class-D Stereo
Amplifier.
An integrated 5 V to 3.3 V Low-dropout
voltage regulator (LDO).
An integrated 3.3 V to 1.8V Low-dropout
voltage regulator (LDO).

HDA_RST_AUDIO#

EMI

HDA_SYNC_AUDIO

R837 @
4.7K_0402_5%

HDA_SDOUT_AUDIO

1 R838
2
0_0402_5%

HDA_BITCLK_AUDIO

HDA_RST_AUDIO#

C990

1
22P_0402_50V8J
C991

1
22P_0402_50V8J
C989

1
22P_0402_50V8J
C988

22P_0402_50V8J
C987

100P_0402_50V8J

2
D

ESD Reserve

R839

<32> CX_GPIO0
<30> EAPD
<30> EC_MUTE#

0_0402_5%
0_0402_5%

1
2

10

CX_GPIO0

2 R1003
1
R850

38
37

40
1
SPK_L2+
SPK_L1-

11
13

SPK_R2+
SPK_R1-

16
14

Internal SPEAKER

DMIC_CLK
DMIC_1/2

NC
NC
NC

LEFT+
LEFTAVEE
FLY_P
FLY_N

RIGHT+
RIGHT-

SENSE_A

36

R1001
1

4.7U_0603_6.3V6K

0.1U_0402_16V4Z
C1000

0_0402_5%
2.2U_0603_6.3V4Z @
2

+MICBIASB

32
31
30

+3VS

MIC_INR
MIC_INL

Changed from 5.1ohm to 15ohm


for "zi zi"noise.

4.7K_0402_5%
1

1
1

2
2

15_0402_5%
15_0402_5%

HP_OUTR <32>
HP_OUTL <32>

Headphone

Combo Jack detect (normal close)

MIC_JD

D
Q107
LBSS138LT1G_SOT-23-3

33K_0402_5%
R854 1
2

EXT_MIC

2
G

+5VS

C1008
1U_0402_6.3V6K

PLUG_IN_R
R855
10K_0402_5%

GNDA
R857 47K_0402_5%
1
2
@
1
C1011

CX_GPIO0

PC Beep

<32> PLUG_IN

R856
20K_0402_5%

Q108
2N7002_SOT23

2
G

PC_BEEP

R860
2.2K_0402_5%

2011/10/12

GND1
GND2

@ D41
TVNST52302AB0 C/C SOT523

D42 @
TVNST52302AB0 C/C SOT523

Deciphered Date

1
2
3
4

ACES_88231-04001
ME@

Compal Electronics, Inc.


2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

5
6

Compal Secret Data

Security Classification
Issued Date

wide 30MIL

1
2
3
4

MIC_INL

JSPK1
SPK_R1-_CONN
SPK_R2+_CONN
SPK_L1-_CONN
SPK_L2+_CONN

FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603
FBMA-L11-160808-121LMT_0603

MIC_INR

2
2
2
2

GNDA

2 2.2U_0603_6.3V4Z

1
1
1
1

220P_0402_50V7K

C1012 1

L70
L71
L72
L73

220P_0402_50V7K
C1016

1
2
WM-64PCY_2P
45@

close to Codec
SPK_R1SPK_R2+
SPK_L1SPK_L2+

MIC1

@
R859
10K_0402_5%

220P_0402_50V7K
C1015

R858
1
2
33_0402_5%

PC_BEEP1

C1018
0.1U_0402_16V4Z

C1017
0.1U_0402_16V4Z

0.1U_0402_16V4Z

C1010

<12> FCH_SPKR

0.1U_0402_16V4Z

+MICBIASC

C1013

220P_0402_50V7K
C1014

C1009

<30> BEEP#

0.1U_0402_16V4Z

ICH Beep

un-pop

EXT_MIC <32>

Internal MIC

Place colose to Codec chip

EC Beep

External MIC

24
25
39

2
1U_0603_10V4Z

R1000
2

PLUG_IN_R

GND

Port B
Port A

MIC_JD
PLUG_IN_R

AN@

EXT_MIC

R1005
R1006

CX20671-21Z_QFN40_6X6

2 20K_0402_1%
2 39.2K_0402_1%

2.2U_0603_6.3V4Z

+MICBIASC

1
C1005

2 5.11K_0402_1%

1
1

R1000 & R700 for App & Nokia combo ear phone
R1002 100_0402_1%

2
2

23
22

21
19
20

R997
R998

+MICBIASB

C1003 1
C1004 1

35
34
33

R996

2K_0402_5%
1

2
0_0402_5%
2
0_0402_5%
2
0_0402_5%
2
0_0402_5%

SENSE_A

AN@

41

4.7U_0603_6.3V6K
C1001

0.1U_0402_16V4Z
C999

C996
C1002

GPIO0/EAPD#
GPIO1/SPK_MUTE#

Please bypass caps very close to device.

PC_BEEP
C_BIAS
PORTC_R
PORTC_L

Sense resistors must be


connected same power
that is used for VAUX_3.3

R999

GND

Short GND and GNDA on


GND1 & GND2 on layout

0.1U_0402_16V4Z

C994

PORTB_R
PORTB_L
B_BIAS

PORTA_R
PORTA_L

EAPD active low


0=power down ex AMP
1=power up ex AMP

4.7U_0603_6.3V6K
C995

27
28
26
SENSE_A

PC_BEEP

BIT_CLK
SYNC
SDATA_IN
SDATA_OUT

12
15
17

HDA_SDOUT_AUDIO

LPWR_5.0
RPWR_5.0
CLASS-D_REF

5
8
6
4

2
1

C1007

2 33_0402_5%

HDA_BITCLK_AUDIO
HDA_SYNC_AUDIO

RESET#

4.7U_0603_6.3V6K

R841 1

+5VS

C1006

<12> HDA_SYNC_AUDIO
<12> HDA_SDIN0
<12> HDA_SDOUT_AUDIO

HDA_RST_AUDIO#

0.1U_0402_16V4Z

<12> HDA_BITCLK_AUDIO

Layout Note:Path from +5VS to LPWR_5.0


RPWR_5.0 must be very low
resistance (<0.01 ohms)

0.1U_0402_16V4Z

<12> HDA_RST_AUDIO#

AVDD_3.3
AVDD_5V
AVDD_HP

29

U45

FILT_1.65

3
7
2
18

FILT_1.8
VDD_IO
VAUX_3.3
DVDD_3.3

0.1U_0402_16V4Z

10U_0603_6.3V6M
C998

AVDD_3.3 pinis output of


internal LDO. NOT connect
to external supply.

+5VS

10 mils
C997

0.1U_0402_16V4Z

C992

1R840 @ 2 0_0402_5%

R853
1
R861
1
R863
1
R867
1

0_0402_5%

0.1U_0402_16V4Z

+LDO_OUT_3.3V

C985

4.7U_0603_6.3V6K
C986

C983

0.1U_0402_16V4Z

1U_0603_10V4Z
C993

+3VS
+3VALW

1U_0603_10V4Z
C984

0.1U_0402_16V4Z

C981

4.7U_0603_6.3V6K
C982

0.1U_0402_16V4Z

0.1U_0402_16V4Z
C980

C978
+3VS

4.7U_0603_6.3V6K
C979

+3VS

Title

CX20671 Codec
Size Document Number
Custom

Rev
0.1

LA8681P

Date: Wednesday, November 30, 2011


1

Sheet

27

of

48

HDD CONN

BT MODULE CONN
JHDD1

<11> SATA_FTX_C_DRX_P0
<11> SATA_FTX_C_DRX_N0
<11> SATA_FRX_C_DTX_N0
<11> SATA_FRX_C_DTX_P0

C161 1
C162 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FTX_DRX_P0
SATA_FTX_DRX_N0

C1075 1
C1074 1

2 0.01U_0402_16V7K
2 0.01U_0402_16V7K

SATA_FRX_DTX_N0
SATA_FRX_DTX_P0

1
2
3
4
5
6
7

+5VS_HDD

J10

JUMP_43X79

+3VS

1
C1076
1000P_0402_50V7K

1
C616
0.1U_0402_16V4Z

1
C617
1U_0603_10V6K

1
C1079
10U_0603_6.3V6M

GND
GND

+3VS_BT_R

0_0603_5%
R815 BT@
1

30mils
1

Q81
PMV65XP_SOT23-3~D
BT@

<12> USB20_P6
<12> USB20_N6

0.1U_0402_16V4Z
C930
BT@
JBT1
1
1
2 2
3 3
4 4
5
5 G1
6 6 G2

23
24

SUYIN_127043FB022G278ZR
ME@

@
C620
0.1U_0402_16V4Z

+5VS_HDD

+3VS_BT
+3VS
D

+5VS_HDD

<11> BT_ON#
3.3V
3.3V
3.3V
GND
GND
GND
5V
5V
5V
GND
Reserved
GND
12V
12V
12V

BT@
C929
0.1U_0402_16V4Z
1
2

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

+3VS

BT@
R814
100K_0402_5%
1
2

+5VS

GND
RX+
RXGND
TXTX+
GND

BTON_LED:NC

<29> BT_ACTIVE

7
8

ACES_87213-0600G
ME@

ODD CONN 15''

JODD1

0.01U_0402_16V7K
0.01U_0402_16V7K
2 0_0402_5%

<12> ODD_DETECT#
<30> ODD_DA#

R873 1
R820 1

2 0_0402_5%
2 0_0402_5%

SATA_FTX_DRX_P1_15
SATA_FTX_DRX_N1_15
SATA_FRX_DTX_N1_15
SATA_FRX_DTX_P1_15
ODD_DETECT#
+5V_ODD
ODD_DA#_R

11
12

GND
GND

@
R821 1

+3VS

2 10K_0402_5%
@
@ Q46

2N7002_SOT23

J12

@
R817
10K_0402_5%

2
G

ME@

1
OUT
IN

ODD CONN 14''

2
GND

<11> ODD_EN

JODD2
SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1
SATA_FRX_C_DTX_N1
SATA_FRX_C_DTX_P1

14@
2
2
14@
C965 1 14@2
C964 1
2
14@
C967 1
C966 1

0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_FTX_DRX_P1_14
SATA_FTX_DRX_N1_14

0.01U_0402_16V7K
0.01U_0402_16V7K

SATA_FRX_DTX_N1_14
SATA_FRX_DTX_P1_14

1
2
3
4
5
6
7

ODD_DETECT#
+5V_ODD

8
9
10
11
12
13

ODD_DA#_R

+5V_ODD

Q82
PMV65XP_SOT23-3~D
@

1
C936
10U_0603_6.3V6M

C932
0.1U_0402_16V4Z

@
1 R818
2
100K_0402_5%

+3VS
3

JUMP_43X79

+5VS

ACES_87056-01001-001

<12> ODD_DA#_FCH

short J12, no zero power ODD function

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

<11> SATA_FRX_C_DTX_N1
<11> SATA_FRX_C_DTX_P1

0.01U_0402_16V7K
0.01U_0402_16V7K

15@
2
2
15@
C934 1 15@2
C935 1
2
R819 1
15@
C969 1
C968 1

<11> SATA_FTX_C_DRX_P1
<11> SATA_FTX_C_DRX_N1

@
C937
0.01U_0402_16V7K

Q83
DTC124EKAT146_SC59-3
@

ME@

GND
RX+
RXGND
TXTX+
GND
DP
+5V
+5V
MD
GND
GND

GND1
GND2

14
15

TYCO_2-1759838-8~D

Issued Date

2011/10/12

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Title

HDD/ODD/BT
Size
B

Document Number

Rev
0.1

LA8681P

Date:

Wednesday, November 30, 2011


G

Sheet

28
H

of

48

Mini-Express Card for WLAN/WiMAX(Half)


+1.5VS
+3VS

R525 1

<11> BT_DISABLE#

<10> CLK_PCIE_WLAN#
<10> CLK_PCIE_WLAN
PCI_RST#_R
CLK_PCI_DB
<10> PCIE_FRX_DTX_N1
<10> PCIE_FRX_DTX_P1
<10> PCIE_FTX_C_DRX_N1
<10> PCIE_FTX_C_DRX_P1
+3VS_WLAN

100_0402_1%
R490
2
2
R491
100_0402_1%

53

For EC to detect
debug card insert.

1
1

C1081
0.1U_0402_16V4Z

@
C1023
4.7U_0603_6.3V6K

@
C1036
0.1U_0402_16V4Z

@
C1037
0.1U_0402_16V4Z

WAKE#
3.3V
NC
GND
NC
1.5V
CLKREQ#
NC
GND
NC
REFCLKNC
REFCLK+
NC
GND
NC
NC
GND
NC
NC
GND
PERST#
PERn0
+3.3Vaux
PERp0
GND
GND
+1.5V
GND
SMB_CLK
PETn0
SMB_DATA
PETp0
GND
GND
USB_DNC
USB_D+
NC
GND
NC
LED_WWAN#
NC
LED_WLAN#
NC
LED_WPAN#
NC
+1.5V
NC
GND
NC
+3.3V
GND

GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52

+1.5VS_WLAN
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R

R484 1
R485 1

R486 1
R487 1

2
2

WL_OFF# <11>
APU_PCIE_RST#
+3VALW
+3VS_WLAN

0_0402_5%
0_0402_5%

2 @ 0_0402_5%
2 @ 0_0402_5%

FCH_SMCLK0
FCH_SMDAT0
USB20_N2
USB20_P2

<10,15>

<8,9,12>
<8,9,12>

<12>
<12>

54

TAITW_PFPET0-AFGLBG1ZZ4N0
ME@

1
1

JWLN1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51

J6
JUMP_43X79
@

2 0_0402_5%

2 0_0402_5%
<12> WLAN_CLKREQ#

<30,31> EC_TX_P80_DATA
<30,31> EC_RX_P80_CLK

JUMP_43X79

+1.5VS

R481 1

<28> BT_ACTIVE

2 0_0402_5% WLAN_WAKE#

R480 1

<12,25> FCH_PCIE_WAKE#

+3VS_WLAN

+3VS_WLAN
J5

R492
100K_0402_5%

Reserve for SW mini-pcie debug card.


Series resistors closed to KBC side.
LPC_FRAME#_R
LPC_AD3_R
LPC_AD2_R
LPC_AD1_R
LPC_AD0_R
PCI_RST#_R
CLK_PCI_DB

R493
R494
R495
R496
R497
R498

1
1
1
1
1
1

@
@
@
@
@
@

2
2
2
2
2
2

0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%

LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
APU_PCIE_RST#

LPC_FRAME# <10,30>
LPC_AD3 <10,30>
LPC_AD2 <10,30>
LPC_AD1 <10,30>
LPC_AD0 <10,30>
CLK_PCI_DB

<10>

Close U33

REMOTE2+

@
C784
2200P_0402_50V7K

2
2

REMOTE2-

C785
0.1U_0402_16V4Z

REMOTE1+

REMOTE1-

REMOTE2+

REMOTE2-

SMCLK

DP1

SMDATA

DN1

ALERT#

DP2

THERM#

DN2

GND

10

EC_SMB_CK2

<5,16,30>

EC_SMB_DA2

<5,16,30>

REMOTE2+

@
C786
100P_0402_50V8J

Q72
MMST3904-7-F_SOT323-3

2
B
E

REMOTE1-

VDD

REMOTE1U33

@
C783
100P_0402_50V8J

Under WLAN
1

Close to DDR

REMOTE1+
R674
10K_0402_5%
@

C
Q73 @
MMST3904-7-F_SOT323-3

2
B

REMOTE2-

Fintek thermal sensor


placed near by VRAM

+3VS

REMOTE1+
1
C782
2200P_0402_50V7K

+3VS

EMC1403-2-AIZL-TR_MSOP10

Address 1001_101xb
Change from SA000029210 to SA000046C00 for main source

REMOTE1,2+/-:
Trace width/space:10/10 mil
Trace length:<8"

Compal Secret Data

Security Classification

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Mini PCIE/Thermal IC
Size

Document Number

Rev
0.1

LA8681P
Date:

Compal Electronics, Inc.

Wednesday, November 30, 2011


E

Sheet

29

of

48

+3VALW

<12> EC_SCI#
<37> BATT_LEN#

2
C1117
0.1U_0402_16V4Z

<32> KSO[0..17]
KSI[0..7]
<32> KSI[0..7]

+3VALW
R507 1

2 47K_0402_5% KSO1

R508 1

2 47K_0402_5% KSO2

12
13
37
20
38

EC_RST#
EC_SCI#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
KSO16
KSO17

KSO[0..17]

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

<37,38> EC_SMB_CK1
<37,38> EC_SMB_DA1

55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82

EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2

77
78
79
80

TP_CLK

EC_SMB_CK1/GPIO44
EC_SMB_DA1/GPIO45
SM
EC_SMB_CK2/GPIO46
EC_SMB_DA2/GPIO47

GPIO0F
BEEP#/GPIO10
GPIO12
ACOFF/GPIO13
BATT_TEMP/GPIO38
GPIO39
ADP_I/GPIO3A
GPIO3B
GPIO42
IMON/GPIO43

AD Input

1
C1114
1
C1115

21
23
26
27
63
64
65
66
75
76

BEEP#
ACOFF
BATT_TEMP

DAC_BRIG/GPIO3C
EN_DFAN1/GPIO3D
IREF/GPIO3E
CHGVADJ/GPIO3F

+5VALW

BATT_TEMP <37>

USB_ON#

R504 1

ADP_I <37,38>
+3VALW

Ra

T59

68
70
71
72

PS2 Interface

CPU1.5V_S3_GATE/GPXIOA00
WOL_EN/GPXIOA01
HDA_SDO/GPXIOA02
VCIN0_PH/GPXIOD00

83
84
85
86
87
88

GPIO
Bus

SPIDI/GPIO5B
SPIDO/GPIO5C
SPICLK/GPIO58
SPICS#/GPIO5A

ENBKL/GPIO40
PECI_KB930/GPIO41
FSTCHG/GPIO50
BATT_CHG_LED#/GPIO52
CAPS_LED#/GPIO53
PWR_LED#/GPIO54
BATT_LOW_LED#/GPIO55
SYSON/GPIO56
VR_ON/GPIO57
PM_SLP_S4#/GPIO59

R503 1

R505 1

2 100K_0402_5%

R506 1

2 33K_0402_5%

Rb

+3VALW
10K_0402_5%

USB_ON#
INT#

EC_MUTE# <27>
USB_ON# <32,33,34>

ID

TP_CLK
TP_DATA

EAPD <27>
TP_CLK <32>
TP_DATA <32>

R10 MP

0V

R03 PVT

100K

8.2K

0.25V

R02 DVT

100K

18K

0.5V

R01 EVT

100K

33K

0.82V

97
98
99
109

BRD ID

Ra

Rb

NTC_V <37>

119
120
126
128

+3VS
73
74
89
90
91
92
93
95
121
127

ENBKL
RST#
CAPS_LED#
SYSON
VSB_ON_R

ENBKL <22>
LAN_PWR_ON# <25>
BATT_CHG_LED# <32>
CAPS_LED# <32>
PWR_LED# <32>
BATT_LOW_LED# <32>
SYSON <35,40>
VR_ON <44>
2

11/08 Increase for LAN S5 power saving

R509
10K_0402_5%
EC_TACH

@ R1450
1

SUSP#

VSB_ON <37>

0_0402_5%

EC_SMB_CK1

R518

2.2K_0402_5%

R516
100K_0402_5%

C1119
20P_0402_50V8

+3VS

POP for susclk implemented


20100810
R523
2.2K_0402_5%

@
C1123
100P_0402_50V8J

PROCHOT <37>

LID_SW#
SUSP#

ACIN <16,38>
EC_ON <32,39>
ON/OFF <32>
LID_SW# <32>
SUSP# <35,40,41,43>

H_PROCHOT# <5,10,37>

H_PROCHOT#_EC

Q109
2N7002H_SOT23-3

2
G

V18R

+3VALW

C1118
4.7U_0603_6.3V6K

R517
10K_0402_5%

KB9012QF A3 LQFP 128P_14X14

<25> LAN_WAKE#

1
R520

EC_PME#

2
0_0402_5%

JCAP1
1
2
3
4
5
6
7
8

RST#

R524
2.2K_0402_5%
EC_SMB_CK2
EC_SMB_DA2

124

2
1
0_0402_5%

@
C1043
1000P_0402_50V7K

VGA_GATE# <12>
ACIN
EC_ON

EC_SMB_DA1

2.2K_0402_5%
R519

V18R

1
R513

XCLKI/GPIO5D
XCLKO/GPIO5E

MAINPWON <37,39>
BKOFF# <22>
PBTN_OUT# <12>

@
R757

<10,14> RTC_CLK

122
123

BKOFF#
PBTN_OUT#

EC_RSMRST# <12>
EC_LID_OUT# <12>
Turbo_V <37>

+3VALW

XCLKI
XCLKO
2
0_0402_5%

110
112
114
115
116
117
118

EC_LID_OUT#
Turbo_V
H_PROCHOT#_EC

T98

AC_IN/GPXIOD01
EC_ON/GPXIOD02
ON/OFF/GPXIOD03
GPI
LID_SW#/GPXIOD04
SUSP#/GPXIOD05
GPXIOD06
PECI_KB9012/GPXIOD07
AGND/AGND

EC_PME#
EC_TX_P80_DATA
EC_RX_P80_CLK

<29,31> EC_TX_P80_DATA
<29,31> EC_RX_P80_CLK
<12,44> FCH_PWRGD
<31> EC_FAN_PWM

100
101
102
103
104
105
106
107
108

69

R512
10K_0402_5%
@
EC_FAN_PWM

GPIO

EC_RSMRST#/GPXIOA03
EC_LID_OUT#/GPXIOA04
PROCHOT_IN/GPXIOA05
H_PROCHOT#_EC/GPXIOA06
VCOUT0_PH/GPXIOA07
GPO
BKOFF#/GPXIOA08
PBTN_OUT#/GPXIOA09
PCH_APWROK/GPXIOA10
SA_PGOOD/GPXIOA11

ECAGND

<28> ODD_DA#
<22> EC_INVT_PWM
<31> EC_TACH

1
2

EC_SMI#

PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
GPIO0A
GPIO0B
GPIO0C
GPIO0D
EC_INVT_PWM/GPIO11
FAN_SPEED1/GPIO14
EC_PME#/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
PCH_PWROK/GPIO18
SUSP_LED#/GPIO19
NUM_LED#/GPIO1A

GND/GND
GND/GND
GND/GND
GND/GND
GND0

+3VS

PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
CMOS_ON#

11
24
35
94
113

<12>
<12>
<12>
<22>

6
14
15
16
17
18
19
25
28
29
30
31
32
34
36

Vab

VGATE <44>
T60

SPI Device Interface


SPI Flash ROM

2 10K_0402_5%

BRDID

EC_MUTE#
EC_MUTE#/GPIO4A
USB_EN#/GPIO4B
CAP_INT#/GPIO4C
EAPD/GPIO4D
TP_CLK/GPIO4E
TP_DATA/GPIO4F

2
100P_0402_50V8J
2
100P_0402_50V8J

BEEP# <27>
NOVO# <32>
ACOFF <38>

BRDID

DA Output
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49

2 4.7K_0402_5%

ACIN

PWM Output

CLK_PCI_EC
PCIRST#/GPIO05
EC_RST#
EC_SCII#/GPIO0E
GPIO1D

TP_DATA R500 1

BATT_TEMP

EC_VDD/AVCC

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD0
EC_VDD/VCC

GATEA20/GPIO00
KBRST#/GPIO01
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC & MISC
LPC_AD0

2 4.7K_0402_5%

U31

67

9
22
33
96
111
125

R499 1

<10,14> CLK_PCI_EC
<10,25> PLT_RST#

1
2
3
4
5
7
8
10

2
47K_0402_5%

C1096
1000P_0402_50V7K

1
R502

@
1
R501 10_0402_5%

<12> GATEA20
<12> KBRST#
<10> SERIRQ
<10,29> LPC_FRAME#
<10,29> LPC_AD3
<10,29> LPC_AD2
<10,29> LPC_AD1
<10,29> LPC_AD0

C1095
1000P_0402_50V7K

2
1
2
C1116 22P_0402_50V8J

C1041
0.1U_0402_16V4Z

C1040
0.1U_0402_16V4Z

C1113
1000P_0402_50V7K

C1039
0.1U_0402_16V4Z

+EC_AVCC

1 ECAGND 2
2
FBM-11-160808-601-T_0603

1
L46

+3VALW

C1038
0.1U_0402_16V4Z

C1042
0.1U_0402_16V4Z

+5VS

+EC_AVCC

+3VLP
L45 1
2
+3VALW
FBM-11-160808-601-T_0603

+3VS
EC_SMB_CK2 <5,16,29>
EC_SMB_DA2 <5,16,29>

EC_SMB_DA2
EC_SMB_CK2
INT#

+5VS

@
C1124
100P_0402_50V8J

9
10

1
2
3
4
5
6
7
8
GND1
GND2
ACES_50521-0084N-P01
ME@

For Cap sensor function


Compal Secret Data

Security Classification
Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Compal Electronics, Inc.


KB9012/Cap sensor

Size Document Number


Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet

30

of

48

FAN CONN

EC DEBUG PORT

+5VS
JFAN1

1
2
3
4
5
6

<30> EC_TACH
<30> EC_FAN_PW M
C1082
10U_0603_6.3V6M

JECDP1

1
2
3
4

+3VALW
<29,30> EC_TX_P80_DATA
<29,30> EC_RX_P80_CLK

1
2
3
4
G5
G6

1
2
3
4

ACES_85205-0400
ME@

ACES_85205-04001
ME@

CPU

H3
HOLEA

VGA_L

VGA_R

H4
HOLEA

H5
HOLEA

H_3P8

FD2

FD3

FD4

H_3P8
H_3P3

H6
HOLEA

1
H_3P8

FD1

H2
HOLEA

H1
HOLEA

H_3P3

H7
HOLEA

H8
HOLEA

H9
HOLEA

H10
HOLEA

H11
HOLEA

H12
HOLEA

H13
HOLEA

H14
HOLEA

M/B
L

H15
HOLEA

M/B

H17
HOLEA

H16
HOLEA

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

H_2P8

1
1

H_3P0N

H_3P0X4P0N H_3P0X4P0N

D
E

2P8 * 9 pcd

Compal Secret Data

Security Classification
2011/10/12

Issued Date

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


FAN/SCREW/EC Debug

Size
B
Date:

Document Number

Rev
0.1

LA8681P
W ednesday, November 30, 2011

Sheet
1

31

of

48

ON/OFF switch

TOP Side

R535 @
100K_0402_5%

R720

J13
1

2
R701
100K_0402_5%

1
2
0_0402_5%

SHORT PADS

Bottom Side

D24

@
3

ON/OFFBTN#

KSI[0..7]

KSO[0..17]

6
5

Power Button

+3VALW

SW3 @
SMT1-05_4P
1

INT_KBD Conn.

KSI[0..7]
+3VLP

ON/OFF

1
2

<30>

51_ON# <36>

KSO[0..17]

KSO16

<30>

C938 1

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
KSO16
KSO17

2 @ 100P_0402_50V8J

KSO17

C939 1

2 @ 100P_0402_50V8J

KSO2

C940 1

2 @ 100P_0402_50V8J

KSO1

C941 1

2 @ 100P_0402_50V8J

KSO15

C942 1

2 @ 100P_0402_50V8J

KSO7

C943 1

2 @ 100P_0402_50V8J

KSO6

C944 1

2 @ 100P_0402_50V8J

KSI2

C945 1

2 @ 100P_0402_50V8J

KSO8

C946 1

2 @ 100P_0402_50V8J

KSO5

C947 1

2 @ 100P_0402_50V8J

KSO13

C948 1

2 @ 100P_0402_50V8J

KSI3

C949 1

2 @ 100P_0402_50V8J

KSO12

C950 1

2 @ 100P_0402_50V8J

KSO14

C951 1

2 @ 100P_0402_50V8J

KSO11

C952 1

2 @ 100P_0402_50V8J

KSI7

C953 1

2 @ 100P_0402_50V8J

KSO10

C954 1

2 @ 100P_0402_50V8J

KSI6

C955 1

2 @ 100P_0402_50V8J

KSO3

C956 1

2 @ 100P_0402_50V8J

KSI5

C957 1

2 @ 100P_0402_50V8J

KSO4

C958 1

2 @ 100P_0402_50V8J

KSI4

C959 1

2 @ 100P_0402_50V8J

KSI0

C960 1

2 @ 100P_0402_50V8J

KSO9

C961 1

2 @ 100P_0402_50V8J

KSO0

C962 1

2 @ 100P_0402_50V8J

KSI1

C963 1

2 @ 100P_0402_50V8J

DAN202UT106_SC70-3

2
G
3

<30,39> EC_ON

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Reserve for ESD.

CONN PIN define need double check

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

JKB2
26
25

GND
GND

KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15

31
32

GND2
GND1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

ACES_88514-2401
ME@

ACES_88514-3001
ME@

@
R641
10K_0402_5%

@
Q106
2N7002_SOT23-3

FOR 14"

JKB1

<30>

Power Button Board Conn. 8pin


+3VLP

+3VALW
JPWRB1
ME@

+5VALW

R642
100K_0402_5%

NOVO_BTN#

R725
10_0402_5% 2

51_ON#

G1
G2

5
6

E-T_7182K-F04N-00R

3
ON/OFF

1
2
3
4

D26

NOVO#

<30> NOVO#

1
2
3
4

NOVO_BTN#
ON/OFFBTN#

R532@
100K_0402_5%

D25 @
PJSOT24C 3P C/A SOT-23

DAN202UT106_SC70-3
1

2
R722 @
0_0402_5%

IO board USB port

FOR 14"

+USB_VCCA

+5VALW

Card Reader/Audio Jack SB CONN

+USB_VCCB
J14 @

+USB_VCCB

1
2MM

LED1 14@

White
PWR_LED#

<30> PWR_LED#

0.1U_0402_16V4Z
2 R644
1 14@
300_0402_5%

C1020
2
1
<30,33,34>

+5VALW

19-213A-T1D-CP2Q2HY-3T_WHITE

U42
1
2
3
4

USB_ON#

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

+5VS
USB_OC2#

G547I2P81U_MSOP8

BATT_LOW_LED#

BATT_LOW_LED#

<30> BATT_LOW_LED#

LED2

Orange

14@

2 R764
1 14@
470_0402_5%

+3VALW

JCR1

check BOM structure

check U40 !

8
7
6
5

<12>

AN@
2 R894

1 0_0402_5% CR_GND

2 R895

1 0_0402_5%

1 @
C1019
1000P_0402_50V7K

<27> HP_OUTR
<27> HP_OUTL
<27> EXT_MIC
<27> PLUG_IN

+3VS

A@

+USB_VCCB

2nd source SC500005910 S


LED LTST-C191KFKT-5A 0603 ORANGE HT-191UD5_AMBER

BATT_CHG_LED#

LED5

White

BATT_CHG_LED#

<30> BATT_CHG_LED#

L47
2

2 R765
1 14@
300_0402_5%

USB20_N1

+5VALW

USB20_P1

19-213A-T1D-CP2Q2HY-3T_WHITE

1
4

LED6 14@

White
CAPS_LED#

<30> CAPS_LED#

2
2

<12> USB20_N5
<12> USB20_P5

2
2

EMI request

14@

<12> USB20_N1
<12> USB20_P1

L57 @

2
3

USB20_N1_R
USB20_P1_R

WCM-2012-900T_4P
2

R8
1 14@
300_0402_5%

USB20_N5
USB20_P5

1
4

C734
220U_6.3V_M
6.3 * 5.9
SF000001500

USB20_P5_R

<27> CX_GPIO0
+MICBIASB

USB20_N5_R

+
2

C733
470P_0402_50V7K

1
2
3
4
5
6
R687
1 0_0402_5% USB20_N1_R 7
R686
1 0_0402_5% USB20_P1_R
8
9
CR_GND
10
R534
1 0_0402_5% USB20_N5_R 11
R533
1 0_0402_5% USB20_P5_R 12
13
14
2 R690AN@1 0_0402_5%
15
2 R689AN@1 0_0402_5%
16
2 R699A@ 1 0_0402_5%
A@ 1 0_0402_5%
2
17
R691
18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
GND

ACES_51524-0160N-001
ME@

WCM-2012-900T_4P

+5VS

reserve for EMI, which follow GIWG5/6

19-213A-T1D-CP2Q2HY-3T_WHITE

LED B/D Conn


VDD
OUTPUT

+5VALW
+3VALW
+5VS

LID_SW#

GND

Lid Switch

JLED1

14@
C716
0.1U_0402_16V4Z

U37 14@

LID_SW#

<30>

LID_SW#
PWR_LED#
BATT_LOW_LED#
BATT_CHG_LED#
CAPS_LED#
SW_R
SW_L

14@
C717
10P_0402_50V8J

S-5711ACDL-M3T1S_SOT23-3

1
2
3
4
5
6
7
8
9
10
11
12
13
14

14

VDD

CLK

15

VDD

CLK

BB-H

VDD

BB-L

VDD

1
2
3
4
5
6
7
8
9
10
11
12
GND
GND

DAT

GND

DAT

GND

CLK

DAT

GND

NC

NC

CLK

DAT

GND

SW_L

R628 nonBBH@
0_0402_5%
2
1 TP_2
R629 14@
0_0402_5%
2
1

5
6

5
6

SW4 14@
SMT1-05_4P

TP_3

SW5 14@
SMT1-05_4P

SW_R

2 R889
1 0_0402_5%
nonBBH@

+3VS

2 R890
BBH@

C696
<30> TP_CLK
<30> TP_DATA
@
C697
100P_0402_50V8J

1 0_0402_5%

JTP1
8
7

0.1U_0402_16V4Z

6
5
4
3
2
1

TP_CLK
TP_DATA
TP_3
TP_2
TP_1

@
C698
100P_0402_50V8J

@
D15
PSOT24C_SOT23-3

15@
2 R643
1
0_0402_5%
1

ACES_88058-120N
ME@

To TP/B Conn.
+5VS

2 R619
1
0_0402_5%
14@

TP_3

TP_1

0.1U_0402_10V6K
C540

FOR 15"

1 R616
2
100K_0402_5%

+VCC_LID

R615
0_0402_5%

+3VALW

0.1U_0402_10V6K
C541

pin

GND
GND
6
5
4
3
2
1

ACES_88058-060N
ME@
1

R626 nonBBH@
0_0402_5%
2
1 TP_1
R627 14@
0_0402_5%
2
1

TP_2

Compal Secret Data

Security Classification

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

Compal Electronics, Inc.


KBD/PWR/CR/LED/TP Conn.
Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet

32

of

48

+5VALW

+USB_VCCA
@
U40
1
2
3
4

C976
2
1 0.1U_0402_16V4Z
<30,32,34> USB_ON#

8
7
6
5

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

USB_OC1# <12>

G547I2P81U_MSOP8

1 @
C977
1000P_0402_50V7K
2

Right Ext.USB FFC Conn.

4
1
L69

3
2

USB20_N0_R

R836 2
R835 2

<12> USB20_P0
<12> USB20_N0

1 0_0402_5%
1 0_0402_5%

Update to SM070001S00 for EMI request

USB20_P0_R
USB20_N0_R

USB20_P0_R

USB20_N0

1
2
3
4
5
6
7
8

PJDLC05_SOT23-3

ME@
ACES_88058-060N

W=80mils

WCM-2012-900T_4P
USB20_P0

1
2
3
4
5
6
3

GND
GND
JUSB4

D40 @

+USB_VCCA

C974
220U_6.3V_M

+USB_VCCA
1
1
+
C975
470P_0402_50V7K
2
2

6.3 * 5.9
SF000001500

Compal Secret Data

Security Classification
Issued Date

2011/10/12

Deciphered Date

2013/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.


USB cable port

Size
B
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet
E

33

of

48

For EMI/ESD request


@
U3RXDN1 9 10

+5VALW

+USB3_VCCA

W=80mils
U39
1
2
3
4

<30,32,33> USB_ON#

GND VOUT
VIN VOUT
VIN VOUT
EN
FLG

8
7
6
5

G547I2P81U_MSOP8

2A/Active Low

USB_OC0# <12>
1 @
C1024
1000P_0402_50V7K

470P_0402_50V7K
C749

C692
0.1U_0402_16V7K
1
2

+USB3_VCCA

220U_6.3V_M
C748

D23
1

1U3RXDN1

U3RXDP1 8

2U3RXDP1

U3TXDN1 7

4U3TXDN1

U3TXDP1 6

5U3TXDP1

D22
U2DP1

I/O2

I/O4

GND

VDD

I/O1

I/O3

+5VALW

U2DN1

AZC099-04S.R7G_SOT23-6
YSCLAMP0524P_SLP2510P8-10-9

@
U3RXDN2 9 10

D29
1

1U3RXDN2

U3RXDP2 8

2U3RXDP2

U3TXDN2 7

4U3TXDN2

U3TXDP2 6

5U3TXDP2

D30

U2DP2

I/O2

I/O4

GND

VDD

I/O1

I/O3

U2DN2

+5VALW

AZC099-04S.R7G_SOT23-6
C

YSCLAMP0524P_SLP2510P8-10-9
<12> USB30_N10

<12> USB30_N11

<12> USB30_P10

<12> USB30_P11

<12> USB30_FTX_DRX_P0

C847 1

<12> USB30_FTX_DRX_N0

C849 1

U3TXDP1_L
2
0.1U_0402_16V7K
U3TXDN1_L
2
0.1U_0402_16V7K

<12> USB30_FTX_DRX_P1

C848 1

<12> USB30_FTX_DRX_N1

C850 1

<12> USB30_FRX_DTX_P0

<12> USB30_FRX_DTX_P1

<12> USB30_FRX_DTX_N0

<12> USB30_FRX_DTX_N1

WCM-2012-900T_4P

U3TXDP2_L
2
0.1U_0402_16V7K
U3TXDN2_L
2
0.1U_0402_16V7K

U3TXDN1_L 1
U3TXDP1_L 4

WCM-2012-900T_4P

U3TXDN1

U3TXDN2_L

U3TXDN2

4
L49 @

U3TXDP1

U3TXDP2_L

4
L53 @

U3TXDP2

WCM-2012-900T_4P

LP1
+USB3_VCCA

LP2
+USB3_VCCA

W=80mils

U3RXDN1

USB30_FRX_DTX_N1 1

USB30_FRX_DTX_P0

4
L50 @

U3RXDP1

USB30_FRX_DTX_P1 4

W=80mils

JUSB2
U3TXDP1

9
1
8
3
7
2
6
4
5

U3TXDN1
U2DP1
U2DN1
U3RXDP1
U3RXDN1

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

WCM-2012-900T_4P

JUSB3
U3TXDP2
U3TXDN2
U2DP2
GND
GND
GND
GND

10
11
12
13

U2DN2
U3RXDP2
U3RXDN2

TAITW_PUBAU1-09FNLSCNN4H0
ME@

9
1
8
3
7
2
6
4
5

SSTX+
VBUS
SSTXD+
GND
DSSRX+
GND
SSRX-

WCM-2012-900T_4P

USB30_FRX_DTX_N0

USB30_N10 1
USB30_P10 4
GND
GND
GND
GND

10
11
12
13

TAITW_PUBAU1-09FNLSCNN4H0
ME@

U3RXDN2

4
L54 @

U3RXDP2

WCM-2012-900T_4P

U2DN1

USB30_P11

U2DP2

4
L51 @

U2DP1

USB30_N11

4
L55 @

U2DN2

U3TXDN1_L 1 R544

U3TXDP1_L 1 R545

USB30_FRX_DTX_N0

1 R546

USB30_FRX_DTX_P0

1 R547

USB30_P10 1 R550

USB30_N10 1 R551

U3TXDN1
0_0402_5%
U3TXDP1
0_0402_5%
U3RXDN1
0_0402_5%
U3RXDP1
0_0402_5%
U2DP1
0_0402_5%
U2DN1
0_0402_5%

U3TXDN2_L

1 R631

U3TXDP2_L

1 R632

USB30_FRX_DTX_N1 1 R633

USB30_FRX_DTX_P1 1 R634

USB30_P11

1 R635

USB30_N11

1 R636

U3TXDN2
0_0402_5%
U3TXDP2
0_0402_5%
U3RXDN2
0_0402_5%
U3RXDP2
0_0402_5%
U2DP2
0_0402_5%
U2DN2
0_0402_5%

Compal Secret Data

Security Classification
Issued Date

2011/10/12

Deciphered Date

2013/10/12

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.


Left USB3.0

Size
B
Date:

Document Number

Rev
0.1

LA8681P
Wednesday, November 30, 2011

Sheet
1

34

of

48

+5VALW TO +5VS

+3VALW TO +3VS

+1.5V to +1.5VS
+1.5V

+VSB

+VSB

2 SUSP
G
Q56
2N7002_SOT23
@

Q59
2N7002K_SOT23-3
3

C1
0.1U_0402_25V6

C708 @
0.1U_0603_25V7K

1
3

SUSP

C701
1U_0603_10V6K
2

3VS_GATE_R
1

Q60
S 2N7002K_SOT23-3

C2
0.1U_0402_25V6

C709 @
0.1U_0603_25V7K

100K_0402_5%
R586
R588
22K_0402_1%
1.5VS_GATE 1
21.5VS_GATE_R
1
D

SUSP# 2
G

R581
470_0603_5%
@

43K_0402_5%

2
G

2 SUSP
G
Q57
2N7002_SOT23
@

R668
3VS_GATE

+5VALW

Q61
2N7002K_SOT23-3
3

5VS_GATE2 R587
15VS_GATE_R
10K_0402_5%
1

2
G

1
SUSP

R585
47K_0402_5%
2

S
R584
20K_0402_5%

D
1

R583
470_0603_5%
@

1
C700
10U_0603_6.3V6M

R582
470_0603_5%
@

1
AP2301GN-HF_SOT23-3

C704
1U_0603_10V6K

1
C699
10U_0603_6.3V6M

C703
10U_0603_6.3V6M

+1.5VS

Q55
3

1 2

C702
10U_0603_6.3V6M

DMN3030LSS-13_SOP8L-8
8
1
7
2
6
3
5

U35
+3VALW
+3VS
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
6
3
C705
C706
C707
5
10U_0603_6.3V6M
10U_0603_6.3V6M 1U_0603_10V6K
2
2
2

+5VS

1 2

U34

+5VALW

2 SUSP
G
Q58
2N7002_SOT23
@

C3
0.1U_0402_25V6

C711 @
0.1U_0603_25V7K

+VSB

+RTCBATT

2
G

R669

2 1.1VS_GATE_R
1
1
160K_0402_1%
C4
C715 @
Q65
0.1U_0402_25V6 0.1U_0603_25V7K
2
2
S 2N7002K_SOT23-3
1

1
2
OUT
<30,40> SYSON

SYSON

IN

Q64
DTC124EKAT146_SC59-3
@

IN

GND

<30,40,41,43> SUSP#

GND

OUT

SYSON#
Q63
DTC124EKAT146_SC59-3

2 SUSP
G
Q62 @
2N7002_SOT23

@
R593
100K_0402_5%

SUSP

@
R592
100K_0402_5%

<42> SUSP

R591
220K_0402_5%

1.1VS_GATE

2
2
3

2
1
SUSP

R590
470_0603_5%
@

S
75K_0402_5%
R594

+5VALW
+5VALW

U36
+1.1VALW
+1.1VS
DMN3030LSS-13_SOP8L-8
8
1
7
2
1
1
1
6
3
C712
C713
C714
5
10U_0603_6.3V6M
10U_0603_6.3V6M 1U_0603_10V6K
2
2
2

+1.1VALW to +1.1VS

R597
470_0603_5%
@

1 2

1 2

+0.75VS

+1.5V

D
2 SYSON#
G
Q66
2N7002_SOT23
@

R598
470_0603_5%
@
2 SUSP
G
Q67
2N7002_SOT23
@

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

DC Interface
Size Document Number
Custom
Date:

Rev
0.1

LA8681P

Wednesday, November 30, 2011

Sheet
E

35

of

48

1
2

1
2

PC104
1000P_0402_50V7K
PD103 @
1
2

PJ101
@ JUMP_43X39
1 1
2 2

1
PC113
2
1

2
2@

PR128

10U_0603_6.3V6M

@ PC114
2
1

VOUT

2 CHGRTCIN

VIN
GND
1

VS

200_0603_5%

2
1

@ PU102
APL5156-33DI-TRL_SOT89-3
3

51ON-3

RTCVREF

3.3V

@ PC115
2
1

2
PR127

0_0402_5%

@ PR124
22K_0402_1%
1
2

@ PC112
0.22U_0603_25V7K

PR123 @
2
1
100K_0402_1%

<32> 51_ON#

+3VLP

@
51ON-2

1U_0805_25V6K

@PR120
@
PR120
200_0603_5%
1
2

68_1206_5%
PR119
2
1
68_1206_5%

@ PQ104
TP0610K-T1-E3_SOT23-3
CHGRTCP

51ON-1

PR118

@ PD104
LL4148_LL34-2
2
1

BATT+

LL4148_LL34-2

VIN

Unpop for KB9012

0.1U_0603_25V7K

ME@

PC103
100P_0402_50V8J

4602-Q04C-09R 4P P2.5
JDCIN1

PC102
100P_0402_50V8J

PL101
SMB3025500YA_2P
1
2

PF101
7A_24VDC_429007.WRML
1
2 APDIN1

PC101
1000P_0402_50V7K

APDIN

VIN

DC030006J00

+CHGRTC

JRTC2

@ MAXEL_ML1220T10

PR131
560_0603_5%
1
2

PR132
560_0603_5%
1
2

PD109
RB751V-40_SOD323-2
2
1

+RTCBATT

RTCVREF

PD108
RB751V-40_SOD323-2

RTC Battery

Compal Secret Data

Security Classification
Issued Date

2011/10/12

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR DCIN

Size Document Number


Custom
Date:

Rev
0.1

Wednesday, November 30, 2011

Sheet
1

36

of

48

VMB2
1
2
3
4
5
6
7
8
9

PL201
SMB3025500YA_2P
1
2

BATT+

1
PC201
1000P_0402_50V7K

2
1
PR202
100_0402_1%

PC202
0.01U_0402_25V7K
D

ADP_I need to write Charge Options Register (0x12H)=> bit6=1


0: IOUT is the 20x current amplifier output <default @ POR>
1: IOUT is the 40x current amplifier output
EC_SMB_CK1 <30,38>

1
2
PR203
6.49K_0402_1%

VL

+3VALW

12.7K_0402_1%

PR206

1
PR227

0_0402_5%

+3VLP

MAINPWON <30,39>
2

5.11K_0402_1%

PR228
0_0402_5%
@

+3VLP

PR230
47K_0402_1%

1
PR209
10K_0402_1%

PR213 0_0402_5%

1
PR229
47K_0402_1%

PR231
2

1
@

<30>

NTC_V

<30>

Turbo_V

0_0402_5%

PH201
100K_0402_1%_NCP15WF104F03RC

ADP_OCP_2 1

PR212
@ 0_0402_5%
1
2

PR210
5

2
Turbo_V_2

OT2 RHYST2

OTP_N_002

G718TM1U_SOT23-8

2 ADP_OCP_1
G
S SSM3K7002FU_SC70-3

<30> PROCHOT

OT1 TMSNS2

GND RHYST1

@
NTC_V_2

PQ201

OTP_N_003

<5,10,30> H_PROCHOT#

PR208

TYCO_1775789-1
@

VCC TMSNS1

PU201
1

+3VS

PC203
0.1U_0603_16V7K

A/D
1

BATT_TEMP <30>

PR205
402_0402_1%

1
2
PR204
10K_0402_5%

2
1
PR207
21.5K_0402_1%

+3VLP
<30,38> ADP_I

100K_0402_1%

1
2
3
4
5
6
7
8
9

10K_0402_1%

JBATT2

For KB930 --> Keep PU201 circuit


(Vth = 0.825V)
For KB9012 (Red square) --> Remove PU201 circuit, but keep PR206
PH201, PR205, PR211,PQ201,PR208,PR212

PH1 under CPU botten side :


CPU thermal protection at 93 +-3 degree C
Recovery at 56 +-3 degree C

EC_SMB_DA1 <30,38>

PR211

TYCO_1775789-1
@

1
2
3
4
5
6
7
GND
GND

EC_SMCA
EC_SMDA

2
1
PR201
100_0402_1%

VMB
PF201
12A_65V_451012MRL
1
2

JBATT1
1
2
3
4
5
6
7
GND
GND

PR224
1K_0402_5%
2

RTCVREF

PR225
10K_0402_1%
@

1
<39,41> SPOK

1
2

PQ204
2N7002W-T/R7_SOT323-3

2
G
1

2
PR226
100K_0402_1%

2
G
3

PR223
10K_0402_1%
2
1

2VREF_8205

PQ203
D 2N7002KW_SOT323-3

S
<30> VSB_ON

2
1
PR216
100K_0402_1%

2
1

PC206
0.1U_0603_25V7K

PR222
100K_0402_1%

+3VLP

PC207
1U_0402_6.3V6K

PU202A
LM393DG_SO8

PC205
0.22U_0603_25V7K

VL

2
G

PQ202
D 2N7002KW_SOT323-3

PR220
22K_0402_1%
1
2

+VSBP

2
1

BATT_OUT <38>

2
1

PR215
100K_0402_1%

B+

PR214
100K_0402_1%
<BOM Structure>

1
O
4

PQ205
TP0610K-T1-E3_SOT23-3

PR221
221K_0402_1%

+3VALW

8
3

PR218
10M_0402_5%
1

PR219
10K_0402_1%
1
2

+3VLP

PR217
768K_0402_1%

1
1

VMB2

PC204
0.01U_0402_25V7K

P2

+VSBP

PJ201
@ JUMP_43X39
1 1
2 2

+VSB

<30> BATT_LEN#

Compal Secret Data

Security Classification
Issued Date

2011/10/12

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR-BATTERY CONN/OTP

Size Document Number


Custom
Date:

Rev
0.1

Wednesday, November 30, 2011

Sheet
1

37

of

48

B+

P3
P2
PQ301
AO4407A_SO8

PR304
47K_0402_1%
1
2

PD302
1SS355_SOD323-2
2

PC310

PQ309
P2

PHASE

19

HIDRV

18

BTST

17

5
6
7
8
4

PC313
BQ24727VCC1

2
3
2
1

3
2
1

15

14

PR328
10_0603_5%

13
1
2

11

6.8_0603_5%
1 12
PR327

RB751V-40_SOD323-2
PC318
1U_0603_25V6K

BQ24727VDD

DL_CHG

PC320
0.1U_0603_25V7K
2
1

1
3

CHG
1

PR322
4.7_1206_5%

16251_SN
2

BATT+

SRP

SRN

PC319
680P_0603_50V7K

16

5
6
7
8

PD303
REGN

PQ312
AO4466L_SO8

LODRV

PR324
PC314
2.2_0603_5%
0.047U_0603_25V7M
1
2
2
1

BST_CHG

SRP

DH_CHG

PACIN

PL302
4.7U_LF919AS-4R7M-P3_5.2A_20%
PR320
0.01_1206_1%

LX_CHG

SA000051W00

BM

1U_0603_25V6K

2
G
S

PC317
10U_0805_25V6K
2
1

20

2N7002W -T/R7_SOT323-3

PC316
10U_0805_25V6K
2
1

VCC

PQ310
AO4466L_SO8

21

ACN
TP

PR319
10_1206_5%
2

2
ACP

CMPIN

CMPOUT

<BOM Structure>

PC311
0.1U_0603_25V7K
2
1

PU301
SDA
BQ24727RGRR_VQFN20_3P5X3P5

PR326
100K_0402_1%

PC321
0.1U_0603_25V7K

1DISCHG_G-1
1

PR310
2
1
10K_0603_1%

100K_0402_1%

PR309
2
ILIM

+3VALW

5
SCL

10

PR306
200K_0402_1%

1
0.1U_0603_25V7K

ACOK
9

<30,37> EC_SMB_CK1
PR323
1
2
316K_0402_1%

PQ306
DTC115EUA_SC70-3

IOUT

100P_0603_50V8
8

2
1

ACDET

<30,37> EC_SMB_DA1

2N7002KW_SOT323-3

PQ313

PC312
1
2

PC323
0.1U_0603_25V7K

0.1U_0603_25V7K

PR313
@
@
1
2
4.7M_0603_1%

SRN

64.9K_0603_1%

PR321
1
2ACOFF-12
10K_0402_5%

2
G

PC309

39.2K_0402_1%

<30,37> ADP_I

PR325
0_0402_5%

<37> BATT_OUT

@ PR312
2

PR315
10K_0402_5%
1
2
PR316
10K_0402_5%
1
2

2
1
390K_0603_1%

PR314
PR317
1

<30> ACOFF

@
VIN

GND

PQ311
DTC115EUA_SC70-3

ACON

1
5

PR308
150K_0402_1%

2
3

P2-2
PR318
47K_0402_1%
1
2

PACIN

PACIN

PQ307B

PQ308
2N7002KW _SOT323-3
2
BATT_OUT <37>
G

2N7002KDW-2N_SOT363-6

1 2

3
6
PQ307A
2N7002KDW -2N_SOT363-6

+3VALW

<39> ACPRN

PR307
20K_0402_1%

0.1U_0603_25V7K

1
DTC115EUA_SC70-3

PC308

PD301

+3VALW

PR305
10K_0402_1%

2ACOFF-1

VIN

ACN

P2-1
PQ305

DISCHG_G

ACP

8
7
6
5

1SS355_SOD323-2

PC304
5600P_0402_25V7K

PQ303
AO4407A_SO8
1
2
3

3
PC307
2200P_0402_50V7K

PC306
4.7U_0805_25V6-K
1
2

PL301
1UH_PCMB061H-1R0MS_7A_20%

PC301
0.1U_0603_25V7K
2
1
PR303
200K_0402_1%

1
DTA144EUA_SC70-3

1
PR301
47K_0402_5%

B+

PQ304

PR302
0.01_1206_1%

PC305
4.7U_0805_25V6-K
1
2

SH00000AA00

PC303
4.7U_0805_25V6-K
1
2

8
7
6
5

PC315
10U_0805_25V6K

1
2
3

1
2
3

8
7
6
5

PC302
10U_0805_25V6K

VIN

PQ302
AO4423L SO8

@
PC322
0.1U_0603_25V7K

PR337
10K_0402_1%
1
2

BQ24727VDD

PR336
10K_0402_1%

ACIN <16,30>

PACIN
1

1 2

PR335
47K_0402_1%

ACPRN <39>

PR339
2

2
PQ316

DTC115EUA_SC70-3

12K_0402_1%

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2013/10/12

Deciphered Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

CHARGER
Size
Date:

Document Number

Rev
0.1

W ednesday, November 30, 2011

Sheet
1

38

of

48

Note:
Use TPS51125 IC can remove RTC refernece LDO
Use TPS51427 IC must keep RTC refernece LDO

2VREF_8205

PJ402

+3VALW P

+3VALW

PC401
1U_0603_10V6K

@ JUMP_43X118

PJ403

+5VALW P

RT8205_B+
PJ401

PR403
20K_0402_1%
1
2

PR404
19.6K_0402_1%
1
2

+5VALW

21

UG_5V

PHASE1

20

LX_5V

LGATE2

LGATE1

19

LG_5V

PQ402

3
2
1
1
2
1
2
3
2
1

PC419
680P_0603_50V7K

PC421
4.7U_0805_10V6K

1
2
1
2
PC422
0.1U_0603_25V7K

Typ: 175mA

+5VALWP

1
+

4
TPC8A03-H_SO8

PC420
1U_0603_10V6K
2
1

2VREF_8205

5
4

PR410
4.7_1206_5%

5
6
7
8
PQ404

NC

RT8205EGQW _W QFN24_4X4

18

VIN

VREG5
17

EN
13

PL402
4.7UH_PCMB104E-4R7MS_10A_20%
1
2

VL

RT8205_B+

TPC8065-H_SO8

UGATE1

PHASE2

VFB=2.0V

5
6
7
8

PC410
0.1U_0603_25V7K
2
1

PC409
2200P_0402_50V7K
2
1

PC408
4.7U_0805_25V6-K
2
1

2
FB1

REF

FB2

PC407
4.7U_0805_25V6-K
2
1

ENTRIP1

ENTRIP2

UGATE2

ENTRIP2

6
PQ405A
2N7002KDW -2N_SOT363-6

PR413
0_0402_5%
2
1

PR408 PC413
2.2_0603_5% 0.1U_0603_25V7K
BST_5V 1
2 1
2

PQ405B
2N7002KDW -2N_SOT363-6

<30,37> MAINPWON

22

16

8
7
6
5
ENTRIP1

PR418
10K_0402_5%
2
1

23

BOOT1

SPOK <37,41>

B+

For KB9012

PGOOD

BOOT2

PR411
499K_0402_1%
1
2

12

VREG3

PC415
150U_B2_6.3VM_R45M

PC418
680P_0603_50V7K
2
1

PQ403
AO4712_SO8

PR412
100K_0402_1%

LG_3V

1
2
3

+3VALWP

PR409
4.7_1206_5%
2
1

PL401
4.7UH +-20% PCMC063T-4R7MN 5.5A
1
2

24

GND

1
2
3

8
PR407
2 1
2 BST_3V 9
2.2_0603_5%
PC412
UG_3V 10
0.1U_0603_25V7K
LX_3V
11
1

<30,32> EC_ON

RT8205_B+

VO1

VO2

SKIPSEL

PR406
66.5K_0402_1%
2

ENTRIP1

TONSEL

P PAD

15

25

14

AO4466L_SO8

PU401

PQ401

PC411
4.7U_0805_10V6K

8
7
6
5

PC403
4.7U_0805_25V6-K
2
1

PR405
130K_0402_1%
1
2

ENTRIP2

+3VLP

PC406
2200P_0402_50V7K
2
1

@ JUMP_43X118

PC404
4.7U_0805_25V6-K
2
1

PR402
30K_0402_1%
1
2

Typ: 175mA
PC402
0.1U_0603_25V7K
2
1

PC405
0.1U_0603_25V7K
2
1

B+

PR401
13K_0402_1%
1
2

JUMP_43X118

PC417
150U_B2_6.3VM_R45M

+3.3VALWP OCP(min)=5.81A
+5VALWP OCP(min)=8.44A

PR414
100K_0402_1%
2
1

<30,32> EC_ON

PQ408
DTC115EUA_SC70-3

PQ406
DTC115EUA_SC70-3

PR416
100K_0402_1%

VS

PC423
4.7U_0603_6.3V6M

2
G

2
1
PR417
40.2K_0402_1%

PR415
200K_0402_1%
2
1

2N7002W-T/R7_SOT323-3

<38> ACPRN

PQ407
3

VL

2011/10/12

Issued Date

For KB9012

@
5

Compal Secret Data

Security Classification

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

Title

Compal Electronics, Inc.


3VALWP/5VALWP

Size
Document Number
Custom
Date:

W ednesday, November 30, 2011

Rev
0.1
Sheet
1

39

of

48

PJ501
1.5V_B+
PC505
2
1

2200P_0402_50V7K

PC504
2
1

0.1U_0402_25V6

B+

JUMP_43X118

3
2
1

PC503
10U_0805_25V6K
2
1

PQ501
TPC8065-H_SO8

PC502
10U_0805_25V6K
2
1

5
6
7
8

2
@

PGOOD

VBST

10

BST_1.5V

TRIP

DRVH

DH_1.5V

EN

SW

LX_1.5V

VFB

V5IN

DRVL

PR503
PC506
0_0603_5%
0.22U_0603_16V7K
1
2BST_1.5V-1 1
2

PL501
1UH_PCMC063T-1R0MN_11A_20%
1
2

RF

TP

+5VALW

PQ502

DL_1.5V

11

PC508
1U_0603_10V6K
4

TPS51212DSCR_SON10_3X3

VFB=0.7V
3
2
1

11.5K_0402_1%

TPC8A03-H_SO8

PC507
220U_6.3V_M

+1.5VP OCP(min)=15.6A

2
PJ502
2

JUMP_43X118

PJ503
+1.5VP

PR508
10K_0402_1%

+1.5VP

470K_0402_1%

PR507
1

PR5062

1
2

PC501 @
.1U_0402_16V7K

5
6
7
8

PR502
47K_0402_5%

<30,35> SYSON

PR501
0_0402_5%
1
2

PU501

PR505

PR504
4.7_1206_5%

100K_0402_1%

PC509
1000P_0603_50V7K

+1.5V
1

JUMP_43X118

PR512
1M_0402_5%

PC514
22U_0603_6.3V6K
2
1

SY8033BDBC_DFN10_3X3

PC511
68P_0402_50V8J
2
1

FB=0.6Volt

PR510
20K_0402_1%
2

PC513
22U_0603_6.3V6K
2
1

47K_0402_5%

FB

+1.8VSP

PJ504
+1.8VSP

2
@

+1.8VS

JUMP_43X118

1.8VSP max current=4A


1.8VSP_FB
1

EN_1.8VSP

1 2

EN

LX

1.8VSP_LX

SVIN

PC512
PR509
680P_0603_50V7K 4.7_1206_5%

LX

PG

PVIN

TP

11

<30,35,41,43> SUSP#

1 PR511

PC515
0.1U_0402_10V7K

PVIN

NC

JUMP_43X118

10

NC

1.8VSP_VIN

PC510
22U_0603_6.3V6K
2
1

PL503
1UH_PH041H-1R0MS_3.8A_20%
1
2

PU502
PJ505

+5VALW

PR513
10K_0402_1%

Compal Secret Data

Security Classification
Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Title

Compal Electronics, Inc.


PWR-+1.5VP/+1.8VSP

Size Document Number


Custom
Date:

Rev
0.1

W ednesday, November 30, 2011


D

Sheet

40

of

48

PR601
2
1
1

PU601
SY8809DFC_DFN8_2X2
1

PJ601
1

PG

LX

LX

8
PL603
1UH_PCMC063T-1R0MN_11A_20%

7
1.1V_LX

+1.1VALWP

<BOM Structure>

GND

GND

PR604

PC627
22U_0805_6.3V6M

PC606
22U_0603_6.3V6K
2
1

FB

IN

1.1V_LX

EN

1 2

JUMP_43X118

2
1

PC601
22U_0603_6.3V6K

+5VALW

PC605
22U_0603_6.3V6K
2
1

1M_0402_5%

PR603
4.7_1206_5%

PR602

PC603
680P_0603_50V7K

0_0402_5%

PC602
@
0.1U_0402_10V7K

<37,39> SPOK

@
8.25K_0402_1%
1

+1.1VALWP

PJ602

2
PC604
@
2

PR605
10K_0402_1%

+1.1VALW
1

JUMP_43X118
2

68P_0402_50V8J

PJ603
+1.2VSP_B+
PC614
4.7U_0805_25V6-K

3
2
1
PQ604

PC617
1U_0603_6.3V6M

TPC8A03-H_SO8

11
2

TP

TPS51212DSCR_SON10_3X3

+1.05VSP

+5VALW

PR613
470K_0402_1%

3
2
1

1
+
2

PC619
2
1

LG_+1.0VSP

PL602
1UH_PCMC063T-1R0MN_11A_20%
1
2

1U_0603_10V6K

DRVL

+1.0VSP_5V

B+

220U_D2_4VY_R15M

RF

PC618

V5IN

SW_+1.0VSP

VFB

UG_+1.0VSP

PR614

SW

BST_+1.0VSP

EN

10

RF_+1.0VSP

DRVH

PC616
2
1

0.1U_0402_16V7K

PR612

160K_0402_1%

FB_+1.0VSP

VBST

TRIP

4.7_1206_5%

PGOOD

PC620
2
1

EN_+1.0VSP

47K_0402_1%

<30,35,40,43> SUSP#

5
6
7
8

PR611

TRIP_+1.0VSP

JUMP_43X118

680P_0603_50V7K

PU602
1
PR610
1
2
75K_0402_1%

PC615
0.1U_0603_25V7K
1
2

PR609
1
2
0_0603_5%

PC613
4.7U_0805_25V6-K
2
1

PQ603
TPC8065-H_SO8

PC612
2200P_0402_50V7K
2
1

PC611
0.1U_0402_25V6
2
1

5
6
7
8

+1.05VSP

PJ604
2

+1.05VS
1

JUMP_43X118
@

PR615
5.1K_0402_1%
2
1
A

PR616
10K_0402_1%

Compal Secret Data

Security Classification

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
C
Date:

Compal Electronics, Inc.


PWR +1.1VALWP/+1.0VSP
Document Number

Rev
0.1

Wednesday, November 30, 2011


1

Sheet

41

of

48

PJ701
JUMP_43X118
@

PU701

VREF VCNTL

VOUT

NC

TP

+3VALW

PJ702

+0.75VSP

NC

+0.75VS

JUMP_43X118

PC703

NC

GND

1U_0603_10V6K

+0.75VSP
2

PR703

PC705
10U_0603_6.3V6M
2
1

2
G

PC704
.1U_0402_16V7K
2
1

VIN

APL5336KAI-TRL_SOP8P8

1K_0402_1%

PC701
0.1U_0402_10V7K
2
1

PR701
49.9K_0402_1%
1
2

PQ701
2N7002W -T/R7_SOT323-3

<35> SUSP

PR702
1K_0402_1%

PC702
4.7U_0805_6.3V6K

PC706
10U_0603_6.3V6M

+1.5V

Compal Secret Data

Security Classification
2011/10/12

Issued Date

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR +0.75VSP

Size
Document Number
Custom
Date:

W ednesday, November 30, 2011

Rev
0.1
Sheet
1

42

of

48

<19> VCCSENSE_VGA

@
2

VGA_CORE_B+

PJ801
2

B+

JUMP_43X118

16

PC814
10U_0603_6.3V6M

PC813
10U_0603_6.3V6M

2 @

PC812
10U_0603_6.3V6M

PC811
470U_D2_2VM_R4.5M

2
1

PC810
470U_D2_2VM_R4.5M

PC816
0.1U_0603_25V7K
BOOT2_2_VGA1
2

PC815
680P_0603_50V7K

PC809
470U_D2_2VM_R4.5M

PR808
2.2_0603_5%
2
1

BOOT2_VGA
11

12

13

PR806
4.7_1206_5%

EN

LGATE2_VGA

10

VID1

VID0

VREF
6
1
2

UGATE2_VGA

PQ803
TPCA8057-H 1N PPAK56-8

BST

PC808
1U_0603_10V6K

3
2
1

14

PQ802
TPCA8057-H 1N PPAK56-8

SW

V0
PGOOD

V1

97.6K_0402_1%
1
2

DRVH

TPS51518RUKR_QFN20_3X3

+VGA_COREP

+5VALW

3
2
1

DRVL

V2

PL801
0.36UH_PCMC104T-R36MN1R17_30A_20%
1
2

MODE

GND

17

3
2
1

PC807
1
TRIP

V3

1 1
PR811

10K_0402_1%

VGA_PWRGD

15

+VGA_COREP
Iocp=32.5A

PC817
0.1U_0402_10V7K

PR809
7.68K_0402_1%

21

4
5

2
<12,15,17>

V5IN

+3VS

PR812
0_0402_5%
1
2

18

20

GSNS

21
PR807
5.11K_0402_1%

PR810

PR805
11.8K_0402_1%

100K_0402_1%
<BOM Structure>

4700P_0402_25V7K
19 1
2

2
1

SLEW

1
2

VSNS

PAD

PU801
PR804

PR803
41.2K_0402_1%

PC805
4.7U_0805_25V6-K

5
2
1

10P_0402_25V8J

21

<19> VSSSENSE_VGA

PC801

PR801
0_0402_5%
1
2

PQ801
TPCA8065-H_SOP-ADV8-5

10P_0402_25V8J
1
2

PC806
2

PC802
0.1U_0402_25V6
2
1

1
PR802
0_0402_5%

PC804
4.7U_0805_25V6-K
2
1

PC803
2200P_0402_50V7K
2
1

PJ802
2

+VGA_COREP

Seymour

+VGA_CORE

@ JUMP_43X118

GPU_VID1

GPU_VID0

Core Voltage Level

0.9V

1.0V

1.05V

1.12V

PJ803

<16> GPU_VID0
PR822
10k_0402_5%
1
2

@ JUMP_43X118

<16> GPU_VID1

<17> PX_MODE
<30,35,40,41>

SUSP#

PR813
33K_0402_5%
1
2VRON_VGA
PR814
0_0402_5%
1
2

PR823
10k_0402_5%
1
2

+1.5V

@
1

+VGA_PCIEP

+1.0VGS

JUMP_43X79
@

PC819
1U_0402_6.3V6K

1
EN

FB
VIN

+VGA_PCIEP
1

3
2
PR817
1.15K_0402_1%

8
PR818
20K_0402_1%

4
PC823
22U_0603_6.3V6K
2
1

GND

VOUT
1

PXS_PWREN

VOUT

POK

APL5912-KAC-TRL_SO8

<12,17> PXS_PWREN

PR816
40.2K_0402_1%
1
2

VIN

GPU_VID1

PC822
0.1U_0603_25V7K
2
1

PR821
10k_0402_5%
1
2

PC820
4.7U_0805_6.3V6K

PU802
@

+3VS

PR815
0_0402_5%

PD801

RB751V-40_SOD323-2
1
2

VCNTL

GPU_VID0

@ PR820
10k_0402_5%
1
2

+3VS

@
PJ804
JUMP_43X79

PC818
0.1U_0402_16V7K
+5VALW

PJ805

+5VALW

VGA_PCIE

1.0V

1.1 V

PR819

4.53K

3K

PC821
0.01U_0402_25V7K

PR819
4.53K_0402_1%

Compal Secret Data

Security Classification

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
Date:

Compal Electronics, Inc.


PWR-VGA_CORE/VGA_PCIE
Document Number

Rev
0.1

Wednesday, November 30, 2011


D

Sheet

43

of

48

PL901
HCB2012KF-121T50_0805

CPU_B+
PC901
33P_0402_50V8J
2
1

PR902
2_0603_5%
1
2

1 2

PC908
0.22U_0603_25V7K
4

APU_VDDNB_RUN_FB_H

<5>

AO4712L_SO8

PR923
10_0402_5%
PR938
0_0402_5%

PR925
95.3K_0402_1%
2
1

LGATE0

ISL6265CHRTZ-T_TQFN48_6X6

RBIAS

OCSET

LGATE1

VDIFF0

PGND1

32

3
2
1
4

+5VS
LGATE0

31
30
29
28

PC918
1U_0603_16V6K

LGATE0

PC924
PC913
4.7U_0805_25V6-K
2
1

PC912
4.7U_0805_25V6-K
2
1

@ PR920
4.7_1206_5%

PR922
9.31K_0402_1%

@PC916
@PC916
680P_0603_50V7K

PC917
2
1
0.1U_0603_16V7K
2

27

APU_VDD0_RUN_FB_L

26

TP

25

ISN0

VSEN0

+VDDNBP
Iocp~15A

PR930

PR932
10_0402_5%
1
2
DIFF_0

+1.5VS

1
PR931
0_0402_5%

+CPU_CORE
Iocp~15A

VW0

PR933
PC919
255_0402_1% 2200P_0402_25V7K
FB_0
2
1 2
1

COMP0

PC920
180P_0402_50V8J
PR934
1K_0402_5%
2
1

PR935
2

PC922
2
1

PC921
1000P_0402_50V7K
4

PR936
6.81K_0402_1%
2
1

54.9K_0402_1% 1200P_0402_50V7K
@

PR937
36.5K_0402_1%

Compal Secret Data

Security Classification
2010/06/30

Issued Date

2012/06/30

Deciphered Date

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A

Compal Electronics, Inc.


+CPU_CORE/VDDNBP

PR926
5.11K_0402_1%

0_0402_5%
2
1 RTN0
<5>

+APU_CORE

49

ISN1
24

ISP1
23

VW1
22

COMP1
21

FB1
20

VDIFF1
19

VSEN1
18

RTN1
17

RTN0

ISN0

ISP0
ISN0

BOOT1

ISP0

PR929
2
0_0402_5%

14

13

PR928
0_0402_5%

VSEN1

APU_VDD0_RUN_FB_H

ISP0

2 VSEN1

PR927
2
1
10_0402_5%

<5>

UGATE1

VW0

+APU_CORE

COMP0
VSEN0

12

PHASE1

16

11

FB0

15

10

S TR AON7518 1N DFN

PHASE0

PVCC

UGATE0

33

2
2

PGND0

34

PC915
0.22U_0603_25V7K

38

39

40

41

42

43

44

37
UGATE_NB

PHASE_NB

LGATE_NB

PGND_NB

OCSET_NB

RTN_NB

VSEN_NB

45

SVC
ENABLE

FSET_NB

46

PHASE0

BOOT0

ISN0

UGATE0

SVD

35

PWROK

36

ISP0

BOOT0

PL903
0.36UH_ETQP4LR36WFC_24A_20%

BOOT_NB

PGOOD

BOOT_NB

PR918
2.2_0603_5%
BOOT0 1
2 1

1 2

<30> VR_ON
PR924
21.5K_0402_1%
2
1

1
PR921
0_0402_5%2

PC909
220U_D2_4VM

ISL6265_PWROK
2

PQ904
TPCA8059-H_SOP-ADVANCE8-5

<5> APU_SVD
<5> APU_SVC

OFS/VFIXEN

PR939
0_0603_5%
1
2

3
2
1

<5,10> APU_PWRGD

2
@ PR917 100K_0402_5%
2
PR919 100K_0402_5%

PHASE0

FB_NB

1
1

COMP_NB

47
VCC

VIN

48

2
<30> VGATE
<12,30> FCH_PWRGD

PQ903

1
2

UGATE0
PU901

@ PC910
680P_0603_50V7K

LGATE_NB

UGATE_NB

@ PR916
105K_0402_1%

CPU_B+

@ PR915
10K_0402_1%

@PR905
4.7_1206_5%

1 @ PR9102
10_0402_5%
PHASE_NB

PHASE_NB

PR914
105K_0402_1%

+APU_CORE_NB

3
2
1
5
6
7
8
PQ902

APU_VDD0_RUN_FB_L

PR911
27.4K_0402_1%
2
1

PL902
3.3UH_PCMB104E-3R3MS_11A_20%
1
2

@ PR913
105K_0402_1%

+
2

PR908
0_0402_5%
2
1
PR909
0_0402_5%
2
1

1
PR912
0_0402_5%

PR903
2.2_0603_1%
BOOT_NB 1
2 1
@ PR907
10_0402_5%
1
2 +APU_CORE_NB LGATE_NB

PC911
0.1U_0603_25V7K

PHASE_NB

PR904
22K_0402_1%
2
1

PR906
2_0603_5%

+3VS

+5VS

PQ901
AO4466L_SO8

B+
1

2
1

UGATE_NB

PC906
1000P_0402_50V7K
2
1

PC907
0.1U_0603_16V7K

CPU_B+

PC902
1000P_0402_50V7K

3
2
1

+5VS

5
6
7
8

PC905
4.7U_0805_25V6-K
2
1

PR901
44.2K_0402_1%

PC904
4.7U_0805_25V6-K
2
1

220U_25V_M

PC914
4.7U_0805_25V6-K
2
1

Size Document Number


Custom
Date:

Rev
0.1

Wednesday, November 30, 2011

Sheet
E

44

of

48

+CPU_CORE

+CPU_CORE_NB
+APU_CORE_NB

+APU_CORE

1
+

1
+

PC1006
10U_0603_6.3V6K
2
1

PC1007
10U_0603_6.3V6K
2
1

PC1008
10U_0603_6.3V6K
2
1

PC1014
10U_0603_6.3V6K
2
1

PC1015
10U_0603_6.3V6K
2
1

PC1016
10U_0603_6.3V6K
2
1

PC1020
330U_D2_2V5M_R9M

PC1019
330U_D2_2V5M_R9M

PC1018
330U_D2_2V5M_R9M

PC1017
330U_D2_2V5M_R9M

1
1

PC1022
220U_D2_4VM

PC1005
10U_0603_6.3V6K
2
1
PC1013
10U_0603_6.3V6K
2
1

PC1004
10U_0603_6.3V6K
2
1
PC1012
10U_0603_6.3V6K
2
1

PC1003
10U_0603_6.3V6K
2
1
PC1011
10U_0603_6.3V6K
2
1

PC1002
10U_0603_6.3V6K
2
1

PC1010
10U_0603_6.3V6K
2
1

PC1009
10U_0603_6.3V6K
2
1

PC1001
10U_0603_6.3V6K
2
1

1
2

PC1026
10U_0603_6.3V6K

PC1025
330U_D2_2VM_R7M

2
B

+1.8VS

PC1024
10U_0603_6.3V6K

PC1023
330U_D2_2VM_R7M

+1.05VS

Compal Secret Data

Security Classification
2011/10/12

Issued Date

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

Compal Electronics, Inc.


PWR - PROCESSOR DECOUPLING

Size
Date:

Document Number
Tuesday, November 29, 2011

Rev
0.1
Sheet
1

45

of

48

Version change list (P.I.R. List)


Item
1
D

2
3

Page 1 of 1
for PWR

Reason for change

PG#

Modify List

Date

Phase

PR938

(CPU CORE/VDDNBP)...VR_ON
0402 0

APU_CORE_NB....PC1021

4
5
6
7
8
C

9
10
11
12
13

14
B

15
16
17
A

2011/10/12

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR (PWR)
Size Document Number
Custom
Date:

Rev
0.1

Tuesday, November 29, 2011

Sheet
1

46

of

48

QAWGE Power Sequence (AC mode)


EC_ON

EC -> PWR

+3VALW
+5VALW
D

1ms< T1 < 100ms : +3VALW rising time, for LAN chip request
+3VALW need rampe up before +1.1VALW or at the same time.

T1

SPOK

PWR -> PWR

+1.1VALW

Switch -> EC

ON/OFFBTN#

EC -> FCH

EC_RSMRST#

FCH -> EC

RTC_CLK

EC -> FCH

PBTN_OUT#

FCH -> EC

PM_SLP_S5#
PM_SLP_S3#

EC -> PWR

SYSON

EC -> PWR

SUSP#

T2

T2 < 50ms

: EC_RSMRST# rising time

T3 > 16ms

: EC_RSMRST# de-assert to start RTCCLK

+3VALW need rampe up before EC_RSMRST# de-assertion at least 10ms


+1.1VALW need rampe up before EC_RSMRST# de-assertion

T3

T13

T13 > 200ns

: PBTN_OUT# to SLP_S3#/S5# de-assertion

1.5V

+1.8VS
+1.5VS
+1.05VS
C

+5VS
+3VS
+1.1VS

+3VS need rampe up before +1.1VS or at the same time.

+0.75VS

DIS sequence

The time delay between PXS_PWREN assertion


and PXS_RST# de-assertion must be more than 100ms.

PXS_PWREN
+3VGS
+1.0VGS
+1.5VGS
+VGA_CORE
+1.8VGS
CLK_PCIE_VGA

CLK_PCIE_VGA should be 100us earlier than PXS_RST# de-assert.

PXS_RST#
B

VR_ON

EC -> PWR

+APU_CORE
+APU_CORE_NB

PWR -> EC

VGATE

EC -> FCH

FCH_PWRGD

FCH -> APU

APU_CLK
DISP_CLK

FCH -> APU

APU_PWRGD

T11

T11< 32ms

: FCH_POK assertion to clock out

T7

98ms< T7< 150ms

KB_RST#

FCH -> EC

KB_RST# should

: FCH_POK assertion to APU_PWRGD


be de-asserted before FCH_POK

T9

A_RST#

FCH -> Device (PLT_RST#)

101ms< T9< 113ms :


FCH_POK assertion to

A_RST# de-assertion

APU_RST#

FCH -> APU

Compal Secret Data

Security Classification

Issued Date

2011/10/12

Deciphered Date

2013/10/12

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title
Size
Date:

Compal Electronics, Inc.


PWR - PROCESSOR DECOUPLING
Document Number

Rev
0.1

Tuesday, November 29, 2011


1

Sheet

47

of

47